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Relevant bibliographies by topics / VLSI physical design automation

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Academic literature on the topic 'VLSI physical design automation'

Author: Grafiati

Published: 4 June 2021

Last updated: 5 February 2022

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Journal articles on the topic "VLSI physical design automation"

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Bell, I. M. "Physical design automation of VLSI systems." Microelectronics Journal 24, no. 5 (August 1993): 592–93. http://dx.doi.org/10.1016/0026-2692(93)90141-z.

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Shanavas, I. Hameem, and R. K. Gnanamurthy. "Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.

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In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

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YEAP, GARY, and ANDREAS WILD. "INTRODUCTION TO LOW-POWER VLSI DESIGN." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 223–48. http://dx.doi.org/10.1142/s0129156496000098.

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The paper is a survey of the current status of research and practices in various disciplines of low-power VLSI developments. After briefly discussing the rationale of the contemporary focus on low-power design, it presents the metrics and techniques used to assess the merits of the various solutions proposed for improved energy efficiency. The requirements to be fulfilled by process technologies and device structures are reviewed as well as several promising circuit design styles and ad hoc design techniques. The impact of the design automation tools is analyzed with a special emphasis on physical design and logic synthesis. A review of various architectural trade-offs, including power management, parallelism and pipelining, synchronous versus asynchronous architectures and dataflow transformations are covered, followed by a brief discussion of the impact of the system definition, software and algorithms to the overall power efficiency. Emerging semiconductor technologies and device structures are discussed and the paper is concluded with the trends and research topics for the future.

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Saha Sau, Swagata, and Rajat Kumar Pal. "Difficult Channel Instance Generator for VLSI Physical Design Automation using Genetic Algorithm." Indian Journal of Science and Technology 10, no. 13 (April 1, 2017): 1–8. http://dx.doi.org/10.17485/ijst/2017/v10i13/102925.

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Shanavas, I. Hameem, and Ramaswamy Kannan Gnanamurthy. "Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms." VLSI Design 2011 (October 12, 2011): 1–9. http://dx.doi.org/10.1155/2011/896241.

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Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

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Kundu, Sudeshna, Suchismita Roy, and Shyamapada Mukherjee. "Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology." Journal of Circuits, Systems and Computers 29, no. 04 (July 5, 2019): 2050057. http://dx.doi.org/10.1142/s0218126620500577.

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Rectilinear Steiner Tree (RST) construction is a fundamental problem in very large scale integration (VLSI) physical design. Its applications include placement and routing in VLSI physical design automation (PDA) where wire length and timing estimations for signal nets are obtained. In this paper, a pseudo-Boolean satisfiability (PB-SAT)-based approach is presented to solve rectilinear Steiner tree problem. But large nets are a bottleneck for any SAT-based approach. Hence, to deal with large nets, a region-partitioning-based algorithm is taken into consideration, which eventually achieves a reasonable running time. Furthermore, a clustering-based approach is also explored to improve the partitioning of nets by identifying clusters and then applying a heuristic-based approach to get the minimum wire length for each set of the clusters. Experimental results obtained by these techniques show that the proposed algorithm can solve the RST problem very effectively even on large circuits and it outperforms the widely used RST algorithm FLUTE with 3[Formula: see text][Formula: see text][Formula: see text]to 9[Formula: see text][Formula: see text][Formula: see text]speedups.

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CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (December 1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.

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In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.

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Palchaudhuri, Ayan, Sandeep Sharma, and Anindya Sundar Dhar. "Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion." ACM Transactions on Design Automation of Electronic Systems 26, no. 4 (April 2021): 1–34. http://dx.doi.org/10.1145/3446206.

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Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.

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Topisirovic, Dragan. "Advances in VLSI testing at MultiGb per second rates." Serbian Journal of Electrical Engineering 2, no. 1 (2005): 43–55. http://dx.doi.org/10.2298/sjee0501043t.

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Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps). Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability) methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment) resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator) patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

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Chaudhry, M. A. R., Z. Asad, A. Sprintson, and J. Hu. "Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies." VLSI Design 2011 (April 28, 2011): 1–9. http://dx.doi.org/10.1155/2011/892310.

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In the advent of smaller devices, a significant increase in the density of on-chip components has raised congestion and overflow as critical issues in VLSI physical design automation. In this paper, we present novel techniques for reducing congestion and minimizing overflows. Our methods are based on ripping up nets that go through the congested areas and replacing them with congestion-aware topologies. Our contributions can be summarized as follows. First, we present several efficient algorithms for finding congestion-aware Steiner trees that is, trees that avoid congested areas of the chip. Next, we show that the novel technique of network coding can lead to further improvements in routability, reduction of congestion, and overflow avoidance. Finally, we present an algorithm for identifying efficient congestion-aware network coding topologies. We evaluate the performance of the proposed algorithms through extensive simulations.

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Dissertations / Theses on the topic "VLSI physical design automation"

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Pang, Yingxin. "Floorplanning algorithms for VLSI physical design automation /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970677.

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Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.

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Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation
Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich

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Davoodi, Azadeh. "Optimization schemes for variability-driven VLSI design automation." College Park, Md. : University of Maryland, 2006. http://hdl.handle.net/1903/3713.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2006.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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Khandelwal, Vishal. "Variability-aware VLSI design automation for nanoscale technologies." College Park, Md. : University of Maryland, 2007. http://hdl.handle.net/1903/7000.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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Jiang, Zhanyuan. "Performance and power optimization in VLSI physical design." Texas A&M University, 2007. http://hdl.handle.net/1969.1/85791.

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As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay.

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Guo, Pei-Ning. "Floorplan and placement approaches for VLSI physical design /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1998. http://wwwlib.umi.com/cr/ucsd/fullcit?p9914071.

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Herrigel, Alexander. "New approaches to physical synthesis in VLSI macrocell design /." [S.l.] : [s.n.], 1990. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=9112.

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Wrzyszcz, Artur. "Employing Petri nets in digital design : an area and power minimization perspective." Thesis, University of Bristol, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.265361.

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Sze, Chin Ngai. "Algorithms for the scaling toward nanometer VLSI physical synthesis." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4922.

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Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) and the number of transistors in a chip - these are just a few examples of our achievement in VLSI scaling. It is projected to enter the nanometer (timing estimation and buffer planning for global routing and other early stages such as floorplanning. A novel path based buffer insertion scheme is also included, which can overcome the weakness of the net based approaches. Part-2 Circuit clustering techniques with the application in Field-Programmable Gate Array (FPGA) technology mapping The problem of timing driven n-way circuit partitioning with application to FPGA technology mapping is studied and a hierarchical clustering approach is presented for the latest multi-level FPGA architectures. Moreover, a more general delay model is included in order to accurately characterize the delay behavior of the clusters and circuit elements.

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Hu, Shiyan. "Algorithmic techniques for nanometer VLSI design and manufacturing closure." Texas A&M University, 2008. http://hdl.handle.net/1969.1/85905.

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As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's law as well as the growth of semiconductor industry. Efforts are needed in both deterministic design stage and variation-aware design stage. This research proposes various innovative algorithms to address both stages for obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For variation-aware optimizations, new lithography-driven and post-silicon tuning-driven design techniques are proposed. For buffer insertion, a new slew buffering formulation is presented and is proved to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster than the best alternatives is proposed. The algorithm is also extended to handle continuous buffer locations and blockages. For gate sizing, a new algorithm is proposed to handle discrete gate library in contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which integrates the high solution quality of dynamic programming with the short runtime of rounding continuous solution. For lithography-driven optimization, the problem of cell placement considering manufacturability is studied. Three algorithms are proposed to handle cell flipping and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire- length increase. For post-silicon tuning-driven optimization, the problem of unified adaptivity optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming formulation which is solved by an advanced robust linear programming technique. The continuous solution is then discretized using binary search accelerated dynamic programming, batch based optimization, and Latin Hypercube sampling based fast simulation.

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Books on the topic "VLSI physical design automation"

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Sherwani, N. A. Algorithms for VLSI physical design automation. Boston: Kluwer Academic Publishers, 1993.

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Sherwani, N. A. Algorithms for VLSI physical design automation. 3rd ed. Boston: Kluwer Academic Publishers, 1999.

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Sherwani, Naveed. Algorithms for VLSI Physical Design Automation. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2351-2.

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Sherwani, Naveed A. Algorithms for VLSI Physical Design Automation. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2219-2.

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Algorithms for VLSI physical design automation. 2nd ed. Boston: Kluwer Academic Publishers, 1995.

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Sherwani, Naveed. Algorithms for VLSI Physical Design Automation. Boston, MA: Springer US, 1995.

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Habib, Youssef, ed. VLSI physical design automation: Theory and practice. London: McGraw-Hill, 1995.

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service), SpringerLink (Online, ed. Practical Problems in VLSI Physical Design Automation. Dordrecht: Springer Science + Business Media B.V, 2008.

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Lim, Sung Kyu. Practical Problems in VLSI Physical Design Automation. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-6627-6.

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1959-, Dündar Günhan, and Öğrenci A. Selçuk, eds. Analog VLSI design automation. Boca Raton, Fla: CRC Press, 2003.

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Book chapters on the topic "VLSI physical design automation"

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Sherwani, Naveed. "VLSI Physical Design Automation." In Algorithms for VLSI Physical Design Automation, 1–35. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2351-2_1.

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Sherwani, Naveed A. "VLSI Physical Design Automation." In Algorithms for VLSI Physical Design Automation, 1–27. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2219-2_1.

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Sherwani, Naveed. "Physical Design Automation of FPGAs." In Algorithms for VLSI Physical Design Automation, 451–71. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2351-2_11.

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Sherwani, Naveed. "Physical Design Automation of MCMs." In Algorithms for VLSI Physical Design Automation, 473–95. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2351-2_12.

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Sherwani, Naveed A. "Physical Design Automation of FPGAs." In Algorithms for VLSI Physical Design Automation, 409–27. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2219-2_11.

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Sherwani, Naveed A. "Physical Design Automation of MCMs." In Algorithms for VLSI Physical Design Automation, 429–51. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2219-2_12.

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Sherwani, Naveed. "Design and Fabrication of VLSI Devices." In Algorithms for VLSI Physical Design Automation, 37–79. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2351-2_2.

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Sherwani, Naveed A. "Design and Fabrication of VLSI Devices." In Algorithms for VLSI Physical Design Automation, 29–65. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2219-2_2.

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Shyu, Fong-Ming, Po-Hsun Cheng, and Sao-Jie Chen. "Using XML for VLSI Physical Design Automation." In Algorithms and Architectures for Parallel Processing, 821–31. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03095-6_77.

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Sherwani, Naveed. "Compaction." In Algorithms for VLSI Physical Design Automation, 423–50. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2351-2_10.

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Conference papers on the topic "VLSI physical design automation"

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Li-Yi Lin, Hsin-Chang Lin, and Shih-Arn Hwang. "Incremental physical design method for flat SOC design." In 2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2009. http://dx.doi.org/10.1109/vdat.2009.5158167.

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Yangdong Deng and Shuai Mu. "The potential of GPUs for VLSI physical design automation." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4735023.

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3

Konstadinidis, Georgios K. "Challenges in microprocessor physical and power management design." In 2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2009. http://dx.doi.org/10.1109/vdat.2009.5158083.

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4

Sang, Tzu-Hsien. "SPAD LiDAR: From Physical Properties to Signal Processing." In 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2021. http://dx.doi.org/10.1109/vlsi-dat52063.2021.9427324.

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5

Johann, Marcelo. "Recent advances and challenges in physical design automation." In 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2013. http://dx.doi.org/10.1109/isvlsi.2013.6654613.

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Nam, Gi-Joon, David Papa, Michael Moffitt, and Charles Alpert. "Toward the integration of incremental physical synthesis optimizations." In 2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2009. http://dx.doi.org/10.1109/vdat.2009.5158085.

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Saxena, Prashant. "The evolution of interconnect management in physical synthesis." In 2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2009. http://dx.doi.org/10.1109/vdat.2009.5158086.

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8

Patel, Dipesh. "Internet of Things: Connecting the physical and digital worlds." In 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-dat.2014.6834925.

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Lin, Lan, Tong Wu, and Zhifeng Zhang. "A diameter-based model of the rectilinear partitioning problem in VLSI physical design." In 2020 Chinese Automation Congress (CAC). IEEE, 2020. http://dx.doi.org/10.1109/cac51589.2020.9327644.

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Sabbavarapu, Srinivas, B. Karunakar Reddy, Rayapati Prabhat, Kshitiz Gupta, Amit Acharyya, Rishad Ahmed Shafik, and Jimson Matthew. "A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept." In 2013 International Symposium on Electronic System Design (ISED). IEEE, 2013. http://dx.doi.org/10.1109/ised.2013.27.

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Reports on the topic "VLSI physical design automation"

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Parker, Alice C. Formal Models of Hardware and Their Applications to VLSI Design Automation. Fort Belvoir, VA: Defense Technical Information Center, December 1986. http://dx.doi.org/10.21236/ada178837.

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