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1
Pang, Yingxin. "Floorplanning algorithms for VLSI physical design automation /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970677.
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Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.
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Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automationDreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
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Davoodi, Azadeh. "Optimization schemes for variability-driven VLSI design automation." College Park, Md. : University of Maryland, 2006. http://hdl.handle.net/1903/3713.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2006.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
4
Khandelwal, Vishal. "Variability-aware VLSI design automation for nanoscale technologies." College Park, Md. : University of Maryland, 2007. http://hdl.handle.net/1903/7000.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
5
Jiang, Zhanyuan. "Performance and power optimization in VLSI physical design." Texas A&M University, 2007. http://hdl.handle.net/1969.1/85791.
Full textAbstract:
As VLSI technology enters the nanoscale regime, a great amount of efforts have
been made to reduce interconnect delay. Among them, buffer insertion stands out
as an effective technique for timing optimization. A dramatic rise in on-chip buffer
density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates
are buffers.
In this thesis, three buffer insertion algorithms are presented for the procedure
of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under
the dynamic programming framework and runs in provably linear time for multiple
buffer types due to two novel techniques: restrictive cost bucketing and efficient delay
update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution
quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter
time and the buffered tree has better timing.
The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce
via variation and signal distortion in twisted differential line. In addition, a new
buffer insertion technique is proposed to synchronize the transmitted signals, thus
further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new
approaches. In contrast, only a 100MHz signal can be reliably transmitted using a
single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45%
as witnessed in our simulation.
The fourth chapter proposes a buffer insertion and gate sizing algorithm for
million plus gates. The algorithm takes a combinational circuit as input instead of
individual nets and greatly reduces the buffer and gate cost of the entire circuit.
The algorithm has two main features: 1) A circuit partition technique based on the
criticality of the primary inputs, which provides the scalability for the algorithm, and
2) A linear programming formulation of non-linear delay versus cost tradeoff, which
formulates the simultaneous buffer insertion and gate sizing into linear programming
problem. Experimental results on ISCAS85 circuits show that even without the circuit
partition technique, the new algorithm achieves 17X speedup compared with path
based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9%
gate cost, 5.8% total cost and results in less circuit delay.
6
Guo, Pei-Ning. "Floorplan and placement approaches for VLSI physical design /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1998. http://wwwlib.umi.com/cr/ucsd/fullcit?p9914071.
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Herrigel, Alexander. "New approaches to physical synthesis in VLSI macrocell design /." [S.l.] : [s.n.], 1990. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=9112.
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Wrzyszcz, Artur. "Employing Petri nets in digital design : an area and power minimization perspective." Thesis, University of Bristol, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.265361.
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Sze, Chin Ngai. "Algorithms for the scaling toward nanometer VLSI physical synthesis." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4922.
Full textAbstract:
Along the history of Very Large Scale Integration (VLSI), we have successfully scaled
down the size of transistors, scaled up the speed of integrated circuits (IC) and the number
of transistors in a chip - these are just a few examples of our achievement in VLSI scaling.
It is projected to enter the nanometer (timing estimation and buffer planning for global routing and other early stages such
as floorplanning. A novel path based buffer insertion scheme is also included, which
can overcome the weakness of the net based approaches. Part-2 Circuit clustering techniques with the application in Field-Programmable
Gate Array (FPGA) technology mapping
The problem of timing driven n-way circuit partitioning with application to FPGA
technology mapping is studied and a hierarchical clustering approach is presented for the latest multi-level FPGA architectures. Moreover, a more general delay model is included in order to accurately characterize the delay behavior of the clusters and circuit elements.
10
Hu, Shiyan. "Algorithmic techniques for nanometer VLSI design and manufacturing closure." Texas A&M University, 2008. http://hdl.handle.net/1969.1/85905.
Full textAbstract:
As Very Large Scale Integration (VLSI) technology moves to the nanoscale
regime, design and manufacturing closure becomes very difficult to achieve due to
increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of
individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's
law as well as the growth of semiconductor industry.
Efforts are needed in both deterministic design stage and variation-aware design
stage. This research proposes various innovative algorithms to address both stages for
obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For
variation-aware optimizations, new lithography-driven and post-silicon tuning-driven
design techniques are proposed.
For buffer insertion, a new slew buffering formulation is presented and is proved
to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster
than the best alternatives is proposed. The algorithm is also extended to handle
continuous buffer locations and blockages.
For gate sizing, a new algorithm is proposed to handle discrete gate library in
contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which
integrates the high solution quality of dynamic programming with the short runtime
of rounding continuous solution.
For lithography-driven optimization, the problem of cell placement considering
manufacturability is studied. Three algorithms are proposed to handle cell flipping
and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire-
length increase.
For post-silicon tuning-driven optimization, the problem of unified adaptivity
optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming
formulation which is solved by an advanced robust linear programming technique.
The continuous solution is then discretized using binary search accelerated dynamic
programming, batch based optimization, and Latin Hypercube sampling based fast
simulation.
11
Baskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.
12
Wu, Di. "Layout optimization in ultra deep submicron VLSI design." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3759.
Full textAbstract:
As fabrication technology keeps advancing, many deep submicron (DSM) effects have become
increasingly evident and can no longer be ignored in Very Large Scale Integration
(VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling
capacitance, antenna effect and delay variation) and propose optimization techniques
to mitigate these DSM effects in the place-and-route stage of VLSI physical design.
The place-and-route stage of physical design can be further divided into several steps:
(1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed
routing. Among them, layer/track assignment assigns major trunks of wire segments
to specific layers/tracks in order to guide the underlying detailed router. In this dissertation,
we have proposed techniques to handle coupling capacitance at the layer/track assignment
stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering
Change Order) placement stage, respectively. More specifically, at layer assignment, we
have proposed an improved probabilistic model to quickly estimate the amount of coupling
capacitance for timing optimization. Antenna effects are also handled at layer assignment
through a linear-time tree partitioning algorithm. At the track assignment stage, timing is
further optimized using a graph based technique. In addition, we have proposed a novel
gate splitting methodology to reduce delay variation in the ECO placement considering
spatial correlations. Experimental results on benchmark circuits showed the effectiveness
of our approaches.
13
Minz, Jacob Rajkumar. "Physical Design Automation for System-on-Packages and 3D-Integrated Circuits." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14012.
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The focus of this research was to develop interconnect-centric
physical design tools for 3D technologies.
A new routing model for the SOP structure was developed which
incorporated the 3D structure and formalized the resource structure
that facilitated the development of the global routing tool.
The challenge of this
work was to intelligently convert the 3D SOP routing problem into a set
of 2D problems which could be solved efficiently.
On the lines of MCM, the global routing problem
was divided into a number of phases namely, coarse pin distribution,
net distribution, detailed pin distribution, topology generation, layer
assignment, channel assignment and local routing. The novelty in this
paradigm is due to the feed-through vias needed by the nets which traverse
through multiple placement layers. To gain further improvements in
performance, optical
routing was proposed and a cost analysis study was done. The areas for
the placement of waveguides were efficiently determined, which reduced
delays and maximized utilization.
The global router developed was integrated into a simulated-annealing based
floorplanner to investigate trade-offs of various objectives. Since power-supply
noise suppression is of paramount importance in SOP, a model was developed
for the SOP power-supply network. Decap allocation, and
insertion were also integrated into the framework. The challenges
in this work were to integrate computationally intensive analysis tools with
a floorplanning that works to its best efficency provided the evaluation of
the cost functions are rapid. Trajectory-based approaches were used to sample
representative data points for congestion analysis and interpolate the
the congestion metric during the optimization schedule. Efficient
algorithms were also proposed for 3D clock routing, which acheived
equal skews under uniform and worst thermal profiles. Other
objectives such as wirelength, through-vias, and
power were also handled.
14
Tam, King Ho. "Power and variability aware modeling and optimization for physical design automation." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1709026341&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Djigbenou, Jeannette Donan. "Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/32269.
Full textAbstract:
Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain.
Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us.Master of Science
16
GIBSON, DENNIS. "INTEGRATING BEHAVIORAL MODELING AND SIMULATION FOR MEMS COMPONENTS INTO CAD FOR VLSI." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1029435944.
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Bhattacharya, Koustav. "Architectures and algorithms for mitigation of soft errors in nanoscale VLSI circuits." [Tampa, Fla] : University of South Florida, 2009. http://purl.fcla.edu/usf/dc/et/SFE0003280.
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Dilli, Zeynep. "Physical aspects of VLSI design with a focus on three-dimensional integrated circuit applications." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7717.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Lemaitre, Laurent. "Theoretical aspects of the VLSI implementation of fuzzy algorithms : application to the design automation of current mode fuzzy units /." [S.l.] : [s.n.], 1994. http://library.epfl.ch/theses/?nr=1226.
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Casagrande, Anthony Joseph. "Robust, Low Power, Discrete Gate Sizing." Scholar Commons, 2015. http://scholarcommons.usf.edu/etd/5656.
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Ultra-deep submicron circuits require accurate modeling of gate delay in order to meetaggressive timing constraints. With the lack of statistical data, variability due to the mechanical manufacturing process and its chemical properties poses a challenging problem. Discrete gate sizing requires (i) accurate models that take into account random parametric variation and (ii) a fair allocation of resources to optimize the solution. The proposed GTFUZZ gate sizing algorithm handles both tasks. Gate sizing is modeled as a resource allocation problem using fuzzy game theory. Delay is modeled as a constraint and power is optimized in this algorithm. In GTFUZZ, delay is modeled as a fuzzy goal with fuzzy parameters to
capture the imprecision of gate delay early in the design phase when extensive empirical data is absent. Dynamic power is modeled as a fuzzy goal without varying coefficients. The fuzzy goals provide a flexible platform for multimetric optimization. The robust GTFUZZ algorithm is compared against fuzzy linear programming (FLP) and deterministic worst-case FLP (DWCFLP) algorithms. The benchmark circuits are first synthesized, placed, routed, and optimized for performance using the Synopsys University 32/28nm standard cell library and technology files. Operating at the optimized clock frequency, results show an average
power reduction of about 20% versus DWCFLP and 9% against variation-aware gate sizing with FLP. Timing and timing yield are verified by both Synopsys PrimeTime and Monte Carlo simulations of the critical paths using HSPICE.
21
Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.
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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.
22
Li, Zhuo. "Fast interconnect optimization." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3250.
Full textAbstract:
As the continuous trend of Very Large Scale Integration (VLSI) circuits technology
scaling and frequency increases, delay optimization techniques for interconnect
are increasingly important for achieving timing closure of high performance designs.
For the gigahertz microprocessor and multi-million gate ASIC designs it is crucial to
have fast algorithms in the design automation tools for many classical problems in
the field to shorten time to market of the VLSI chip. This research presents algorithmic
techniques and constructive models for two such problems: (1) Fast buffer
insertion for delay optimization, (2) Wire sizing for delay optimization and variation
minimization on non-tree networks.
For the buffer insertion problem, this dissertation proposes several innovative
speedup techniques for different problem formulations and the realistic requirement.
For the basic buffer insertion problem, an O(n log2 n) optimal algorithm that runs
much faster than the previous classical van GinnekenÂs O(n2) algorithm is proposed,
where n is the number of buffer positions. For modern design libraries that contain
hundreds of buffers, this research also proposes an optimal algorithm in O(bn2) time
for b buffer types, a significant improvement over the previous O(b2n2) algorithm
by Lillis, Cheng and Lin. For nets with small numbers of sinks and large numbers
of buffer positions, a simple O(mn) optimal algorithm is proposed, where m is the
number of sinks. For the buffer insertion with minimum cost problem, the problem is first proved to be NP-complete. Then several optimal and approximation techniques
are proposed to further speed up the buffer insertion algorithm with resource control
for big industrial designs.
For the wire sizing problem, we propose a systematic method to size the wires of
general non-tree RC networks. The new method can be used for delay optimization
and variation reduction.
23
Mahalik, Subrat. "Automating Variation and Repeater Analysis in Physical Design of Integrated Circuits." PDXScholar, 2018. https://pdxscholar.library.pdx.edu/open_access_etds/4555.
Full textAbstract:
Rapid advancement and innovation in semiconductor research have continuously helped in designing efficient and complex integrated circuits in miniature size. As the device technology, is aggressively scaling to improve the device performance, the issues related to device interconnects, power, and reliability have become a major concern for the designers. These challenges make the design and validation of ASIC extremely complicated.
The primary idea of this work is to develop automation tools, to be used in the physical design flows to improve the efficiency of the design flow. The first tool named as variation analysis tool automates the on-chip variation modeling used in the post-layout timing closure phase in the physical design flows. The proposed variation analysis tool models three types of variations such as on-chip variation (OCV), advanced on-chip variation (AOCV) and parametric on-chip variation (POCV). The results of the proposed tool have compared with the Synopsys PrimeTime™ results, and the results show average around 98% accuracy compared to the PrimeTime™. The second tool is for automating repeater analysis in the physical design flows. The repeater automation tool can be used to automate the repeater or buffer insertion process, while technology process is changed from one to another. The tool can calculate the best possible repeater distance for any given metal layer and also, the number of repeaters, combinational or sequential for the user given distance and frequency. The accuracy of this script is compared with the repeater insertion based on the synthesis tools and also, the SPICE simulation.
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Rasheed, Farhan [Verfasser], and M. B. [Akademischer Betreuer] Tahoori. "Compact Modeling and Physical Design Automation of Inkjet-Printed Electronics Technology / Farhan Rasheed ; Betreuer: M. B.Tahoori." Karlsruhe : KIT-Bibliothek, 2020. http://d-nb.info/1214301436/34.
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Nunes, Leandro de Morais. "Redução de congestionamento em roteamento global de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/151338.
Full textAbstract:
O Roteamento Global é responsável pelo planejamento da distribuição dos meios de interconexão dentro da área do circuito. Dentro da fase do projeto de circuitos conhecida como Síntese Física, essa fase situa-se após a etapa de posicionamento, que define uma posição exata para cada célula do circuito, e antes da etapa de roteamento detalhado que irá definir uma posição para cada meio de interconexão. Os roteadores globais utilizam uma versão abstrata e simplificada do circuito, que agrega uma região e toda a capacidade de fios que esta região comporta, trabalhando com o planejamento dessas capacidades em relação a demanda de interconexão entre as células do circuito. Este trabalho, apresenta um conjunto de técnicas para delimitação e tratamento de áreas que possuem alta demanda por meios de interconexão em circuitos VLSI. As técnicas são aplicadas em duas fases do fluxo de rotamento global: a primeira é executada na fase de pré-roteamento, onde são identificadas as regiões que possuem alta demanda por interconexão, isto é, são destino ou origem de um número elevado fios em relação a sua capacidade de alocar meios de interconexão; a segunda etapa ocorre dentro da fase de roteamento iterativo, identificando e protegendo aquelas que regiões que possuem os níveis mais elevados de congestionamento. Para avaliar os impactos da aplicação das técnicas propostas, foi feita a implementação em um fluxo de roteamento global existente. A avaliação foi partir da extração de quatro métricas de roteamento global comumente utilizadas na literatura de síntese física, para análise de roteamento global: comprimento dos fios, valor total de congestionamento, máximo congestionamento de aresta e tempo de execução. A partir da execução de experimentos utilizando as técnicas, foi possível verificar ganhos de até 11% em redução do congestionamento total no circuito, em benchmarks para os quais ainda não se tem soluções válidas na literatura. Os tempos de execução obtiveram um redução de até 35%, quando comparados com a implementação usada como referência para aplicação das técnicas, o roteador GR-WL. Um dos efeitos colaterais da aplicação de técnicas de calibração de custos é o aumento do comprimento médio dos fios. Os resultados dos experimentos mostram que as técnicas propostas conseguem reduzir este efeito colateral para, no máximo, 1.39% de acordo com os benchmarks executados.Global routing phase is responsible for the interconnect planning and distribution across the circuit area. During the integrated circuit project flow, the global routing is contained in the Physical Synthesis, after the placement, that is when the position of all circuit cells are defined, and before the detailed routing, when the position of all interonnection wires is realized. A simplified and abstrate version of the circuit routing area is used by the global router, that will agregate in a single vertex, an specific region of the circuit, that represents a bunch of interconnection with their total capacity. This work presents a set of techniques to delimit and threat areas that have high interconnection demand in VLSI circuits. These techniques are applied in two steps of the global routing flow: the first is executed during the initial routing, where the high interconnection demanding regions are identified. the second step is executed during the iterative routing, where the top offender regions are identified and heva their costs pre-allocated. In order to evaluate the impact of the proposed techniques, they are implemented in an existing global routing flow, and four metrics are collected: total wirelenght, execution time, total overflow and maximum overflow. Tha last two metrics will be different from zero just for the circuits that not have a valid solution. After the execution of the experiments it was possible to verify a reduction up to 11% in wirelenght, in some benchmarks that the literature do no have a valid solution. Furthermore, it was possible to verify a reduction up to 35% in the execution time, when compared to the reference implementation. Once we are including constraints in form of cost pre-allocation, it is possible to verify an wirelength increase in some cases. In this work, it was possible to observe a small presence of these side-effects, up to 1.39%, according to the executed benchmarks.
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Healy, Michael Benjamin. "Physical design for performance and thermal and power-supply reliability in modern 2D and 3D microarchitectures." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37093.
Full textAbstract:
The main objective of this research is to examine the performance, power noise, and thermal trade-offs in modern traditional (2D) and three-dimensionally-integrated (3D) architectures and to present design automation tools and physical design methodologies that enable higher reliability while maintaining microarchitectural performance for these systems. Five main research topics that support this goal are included. The first topic focuses on thermal reliability. The second, third, and fourth, topics examine power-supply noise. The final topic presents a set of physical design and analysis methodologies used to produce a 3D design that was sent for fabrication in March of 2010.
The first section of this dissertation details a microarchitectural floorplanning algorithm that enables the user to choose and adjust the trade-off between microarchitectural performance and general operating temperature in both 2D and 3D systems, which is a major determinant of overall reliability and chip lifetime. Simulation results demonstrate that the algorithm performs as expected and successfully provides the user with the desired trade-off. The first section also presents a thermal-aware microarchitectural floorplanning algorithm designed to help reduce the operating temperature of the cores in the unique environment present within multi-core processors. Heat-coupling between neighboring cores is considered during the optimization process to provide floorplans that result in lower maximum temperature.
The second section explores power-supply noise in processors caused by fine-grained clock-gating and describes a floorplanning algorithm created to work with an active noise-canceling clock-gating controller. Simulation results show that combining these two techniques results in lower power-supply noise with minimal processor performance impact. The third section turns to future 3D systems with a large number of stacked active layers (many-tier systems) and examines power-supply delivery challenges in these systems. Parasitic resistance, capacitance, and inductance are calculated for the 3D vias, and the results of scaling various parameters in the power-supply-network design are presented. Several techniques for reducing power-supply-network noise in these many-tier systems are explored. The fourth section describes a layout-level analysis of a novel power distribution through-silicon-via topology and it's effect on IR-drop and dynamic noise. Simulations show that both types of power-supply noise can be reduced by more than 20\% in systems with non-uniform per-tier power dissipation when using the proposed topology.
The final section explains the physical design and analysis techniques used to produce the layouts for 3D-MAPS, a 64-core 3D-stacked memory-on-processor system targeted at demonstration of large memory bandwidth using 3D connections. The 3D-aware physical design flow utilizing non-3D-aware commercial tools is detailed, along with the techniques and add-ons that were developed to enable this process.
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Farahini, Nasim. "SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms : Toward Next Generation Hardware Synthesis Methodologies." Doctoral thesis, KTH, Elektronik och Inbyggda System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-185787.
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Fernando, Pradeep R. "Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001549.
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Nateghi, Bahman. "Une methode orientee edif pour la conception des vlsi, et realisation de son systeme de cao." Paris 6, 1988. http://www.theses.fr/1988PA066435.
Full textAbstract:
Ce memoire traite de la conception assistee par ordinateur dans le domaine des circuits electroniques a haut niveau d'integration, en presentant une methode de conception pour ces circuits, et la chaine d'outils logiciels adaptes a cette methode. La premiere partie critique deux methodologies de conception typiques dans ce domaine. La seconde partie decrit les differentes phases de la methodologie s'inscrivant dans le cadre de la norme edif. La troisieme partie presente plusieurs outils de cao developpes au cours de l'etude, a savoir: une chaine complete d'edition; une chaine complete de verification; un routeur de canal; un routeur global; des post-processeurs de traduction et de visualisation
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Fogaça, Mateus Paiva. "A new quadratic formulation for incremental timing-driven placement." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/164067.
Full textAbstract:
O tempo de propagação dos sinais nas interconexões é um fator dominante para atingir a frequência de operação desejada em circuitos nanoCMOS. Durante a síntese física, o posicionamento visa espalhar as células na área disponível enquanto otimiza uma função custo obedecendo aos requisitos do projeto. Portanto, o posicionamento é uma etapa chave na determinação do comprimento total dos fios e, consequentemente, na obtenção da frequência de operação desejada. Técnicas de posicionamento incremental visam melhorar a qualidade de uma dada solução. Neste trabalho, são propostas duas abordagens para o posicionamento incremental guiado à tempos de propagação através de suavização de caminhos e balanceamento de redes. Ao contrário dos trabalhos existentes na literatura, a formulação proposta inclui um modelo de atraso na função quadrática. Além disso, o posicionamento quadrático é aplicado incrementalmente através de uma operação, chamada de neutralização, que ajuda a manter as qualidades da solução inicial. Em ambas as técnicas, o comprimento quadrático de fios é ponderado pelo drive strength das células e a criticalidade dos pinos. Os resultados obtidos superam o estado-da-arte em média 9,4% e 7,6% com relação ao WNS e TNS, respectivamente.The interconnection delay is a dominant factor for achieving timing closure in nanoCMOS circuits. During physical synthesis, placement aims to spread cells in the available area while optimizing an objective function w.r.t. the design constraints. Therefore, it is a key step to determine the total wirelength and hence to achieve timing closure. Incremental placement techniques aim to improve the quality of a given solution. Two quadratic approaches for incremental timing driven placement to mitigate late violations through path smoothing and net load balancing are proposed in this work. Unlike previous works, the proposed formulations include a delay model into the quadratic function. Quadratic placement is applied incrementally through an operation called neutralization which helps to keep the qualities of the initial placement solution. In both techniques, the quadratic wirelength is pondered by cell’s drive strengths and pin criticalities. The final results outperform the state-of-art by 9.4% and 7.6% on average for WNS and TNS, respectively.
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Hentschke, Renato Fernandes. "Algorithms for wire length improvement of VLSI circuits with concern to critical paths." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/16300.
Full textAbstract:
Esta tese objetiva propor algorítmos para a redução do tamanho dos fios em circuitos VLSI considerando elementos críticos dos circuitos. O problema é abordado em duas perspectivas diferentes: posicionamento e roteamento. Na abordagem de posicionamento, a tese explora métodos para realizar posicionamento de um tipo particular de circuito VLSI, que são conhecidos como circuitos 3D. Diferente de trabalhos anteriores, este tese aborda o problema considerando as conexões verticais (chamadas 3D-Vias) e as limitações impostas pelas mesmas. Foi realizado um fluxo completo, iniciando no tratamento de pinos de entrada e saída (E/S), posicionamento global, posicionamento detalhado e posicionamento das 3D-Vias. A primeira etapa espalha os pinos de E/S de maneira equilibrada objetivando auxiliar o posicionamento para obter uma quantidade reduzida de 3D-Vias. O mecanismo de posicionamento global baseado no algorítmo de Quadratic Placement considera informações da tecnologia e requerimento de espaçamento de 3D-Vias para reduzir o comprimento das conexões e equilibrar a distrubuição das células em 3D. Conexes críticas podem ser tratadas através da insercão de redes artificiais que auxiliam a evitar que 3D-Vias sejam usadas em conexões críticas do circuito. Finalmente, 3D-Vias são posicionadas por um algorítmo rápido baseado na legalizaçãao Tetris. O framework completo reforça os potenciais benefícios dos circuitos 3D para a melhora do comprimento das conexões e apresenta algorítmos eficientes projetados para circutos 3D podendo estes serem incorporados em novas ferramentas. Na abordagem de roteamento, um novo algorítmo para obtenção de árvores de Steiner chamado AMAZE é proposto, combinando métodos existentes com novos métodos que são efetivos para produzir fios curtos e de baixo atraso para elementos críticos. Um técnica de biasing atua na redução do tamanho dos fios, obtendo resultados próximos da solução ótima enquanto que dois fatores de timing chamados path-length factor e sharing factor propiciam melhora do atraso para conexões sabidas como críticas. Enquanto que AMAZE apresenta melhorias significativas em um algorítmo padrão na indústria de CAD (Maze Routers), ele produz árvores de roteamento com uso de CPU comparável com algorítmos heurísticos de árvore de Steiner e menor atraso.This thesis targets the wire length improvement of VLSI circuits considering critical elements of a circuit. It considers the problem from two different perspectives: placement and routing. On placement, it explores methods to perform placement of 3D circuits considering issues related to vertical interconnects (3D-Vias). A complete flow, starting from the I/O pins handling, global placement, detailed placement and 3D-Via placement is presented. The I/O pins algorithm spreads the I/Os evenly and aids the placer to obtain a reduced number of 3D-Vias. The global placement engine based on Quadratic algorithm considers the technology information and 3D-Via pitch to reduce wire length and balance the cells distribution on 3D. Critical connections can be handled by insertion of artificial nets that lead to 3D-Via avoidance for those nets. Finally, 3D-Vias are placed by a fast algorithm based on Tetris legalization. The whole framework enforces the potential benefits of 3DCircuits on wire length improvement and demonstrates efficient algorithms designed for 3D placement that can be incorporated in new tools. On routing, a new flexible Steiner tree algorithm called AMAZE is proposed, combining existing and new methods that are very effective to produce short wire length and low delay to critical elements. A biasing technique provides close to optimal wire lengths while a path length factor and a sharing factor enables a very wide delay and wire length trade-off. While AMAZE presents significant improvements on a industry standard routing algorithm (Maze Routers), it produces routing trees with comparable speed and beter delay than heuristic Steiner tree algorithms such as AHHK and P-Trees.
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Mukherjee, Valmiki. "A Dual Dielectric Approach for Performance Aware Reduction of Gate Leakage in Combinational Circuits." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5255/.
Full textAbstract:
Design of systems in the low-end nanometer domain has introduced new dimensions in power consumption and dissipation in CMOS devices. With continued and aggressive scaling, using low thickness SiO2 for the transistor gates, gate leakage due to gate oxide direct tunneling current has emerged as the major component of leakage in the CMOS circuits. Therefore, providing a solution to the issue of gate oxide leakage has become one of the key concerns in achieving low power and high performance CMOS VLSI circuits. In this thesis, a new approach is proposed involving dual dielectric of dual thicknesses (DKDT) for the reducing both ON and OFF state gate leakage. It is claimed that the simultaneous utilization of SiON and SiO2 each with multiple thicknesses is a better approach for gate leakage reduction than the conventional usage of a single gate dielectric (SiO2), possibly with multiple thicknesses. An algorithm is developed for DKDT assignment that minimizes the overall leakage for a circuit without compromising with the performance. Extensive experiments were carried out on ISCAS'85 benchmarks using 45nm technology which showed that the proposed approach can reduce the leakage, as much as 98% (in an average 89.5%), without degrading the performance.
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Choi, Jung Hyun. "Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2001. http://hdl.handle.net/10183/2884.
Full textAbstract:
The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.
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Cohen, Philippe. "Realisation dans le cadre d'une methode de conception orientee edif, d'un systeme de cao pour les vlsi." Paris 6, 1988. http://www.theses.fr/1988PA066156.
Full textAbstract:
Conception assistee par ordinateur dans le domaine des circuits electroniques a haut niveau d'integration en presentant une methode conception de ces circuits integres et la chaine d'outils logiciels adaptes a cette methode
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Yang, Xiaokun. "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.
Full textAbstract:
With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation.
Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations.
As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI.
Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.
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Yuan, Kun 1983. "VLSI physical design automation for double patterning and emerging lithography." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2249.
Full textAbstract:
Due to aggressive scaling in semiconductor industry, the traditional optical lithography system is facing great challenges printing 32nm and below circuit layouts. Various promising nanolithography techniques have been developed as alternative solutions for patterning sub-32nm feature size. This dissertation studies physical design related optimization problem for these
emerging methodologies, mainly focusing on double patterning and electronic beam lithography.
Double Patterning Lithography (DPL) decomposes a single layout into two masks, and patterns the chip in two exposure steps. As a benefit, the pitch size is doubled, which enhances the resolution. However, the decomposition process is not a trivial task. Conflict and stitch are its two main manufacturing
challenges.
First of all, a post-routing layout decomposer has been developed to perform simultaneous conflict and stitch minimization, making use of the integer linear programming and efficient graph reduction techniques. Compared to
the previous work which optimizes conflict and stitch separately, the proposed method produces significantly better result.
Redundant via insertion, another key yield improvement technique,
may increase the complexity in DPL-compliance. It could easily introduce unmanufacturable conflict, while not carefully planned and inserted. Two algo-
rithms have been developed to take care of this redundant via DPL-compliance problem in the design side.
While design itself is not DPL-friendly, post-routing decomposition may not achieve satisfactory solution quality. An efficient framework of WISDOM
has been further proposed to perform wire spreading for better conflict and stitch elimination. The solution quality has been improved in great extent,
with a little extra layout perturbations.
As another promising solution for sub-22nm, Electronic Beam Lithography (EBL) is a maskless technology which shoots desired patterns directly
into a silicon wafer, with charged particle beam. EBL overcomes the diffraction limit of light in current optical lithography system, however, the low
throughput becomes its key technical hurdle. The last work of my dissertation formulates and investigates a bin-packing problem for reducing the processing
time of EBL.text
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Shih, Po-Shu, and 施伯樹. "Power Routing in VLSI Physical Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/86525426526035172617.
Full textAbstract:
碩士逢甲大學
資訊工程所
93
In VLSI design flow, most commercial tool only support adding power trunks and power straps by hand. Therefore, we must route power lines by hand regardless of the size of the chip. And, the verification step must begin almost after going through the entire design flow. As the complexity of chips is getting higher and more and more reuse IPs, this kind of power routing becomes a challenge to performance and cost. For this reason, to generate the power routing and verify all power constraints automatically is a better way to correspond to performance and cost. This thesis proposed a methodology to generate power routing and calculate the width of the power lines automatically. Also, the power routing satisfied all power constraints.
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Walsh, Peter Anthony. "Combinatorial optimization in VLSI physical design." Thesis, 1992. https://dspace.library.uvic.ca//handle/1828/9608.
Full textAbstract:
Simulated Annealing is a general purpose combinatorial optimization technique which has been applied to many problems in VLSI design. In essence, simulated annealing is Monte Carlo iterative improvement with the ability to conditionally accept uphill moves. The notion of a cooling schedule is common to all simulated annealing implementations. A cooling schedule can be thought of as simulated annealing's control mechanisms.
Experiential work has been done on estimating the cost of an optimal solution to some combinatorial optimization problem instances. Such an estimate can be used to determine termination criteria for general purpose optimization techniques such as iterative improvement or simulated annealing. We have extended this idea and designed a complete simulated annealing general cooling schedule based on the cost of an optimal solution to a problem instance. We call the resultant schedule an extended goal-directed general cooling schedule.
One of the major problems with simulated annealing is its long computation times. This problem can be addressed by first using a fast heuristic to find a good initial configuration and then applying simulated annealing. This approach is called Simulated Sintering.
To exploit the potential of simulated sintering one needs an appropriate general cooling schedule. The extended goal-directed cooling schedule is equally applicable to simulated annealing and simulated sintering.
To date, no one cooling schedule has proven suitable for all optimization problem instances. In our view, no such cooling schedule exits. Consequently, we have attempted to identify the type of problem best suited to optimization by simulated annealing and simulated sintering using the extended goal-directed schedule.
We have applied the extended goal-directed schedule to standard-cell placement and floorplanning problems using both simulated annealing and simulated sintering. Within this context, we have compared the performance of the extended goal-directed schedule to other published schedules. Our results indicate that in terms of layout quality, the extended goal-directed schedule performs as well or better than the other schedules.
In this dissertation, we have developed a new general cooling schedule. Our evaluation of the extended goal-directed schedule suggests that it is a useful research contribution in the area of simulated annealing algorithms.Graduate
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Deng, Liang. "VLSI physical design for manufacturability and reliability /." 2007. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3290216.
Full textAbstract:
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007.Source: Dissertation Abstracts International, Volume: 68-11, Section: B, page: 7535. Adviser: Martin D. F. Wong. Includes bibliographical references (leaves 116-121) Available on microfilm from Pro Quest Information and Learning.
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"Interconnect planning in physical design of VLSI." Thesis, 2006. http://library.cuhk.edu.hk/record=b6074151.
Full textAbstract:
For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan.We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning.
Sham Chiu Wing.
"March 2006."
Adviser: Young Fung Yu.
Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2006.
Includes bibliographical references (p. 106-115).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstracts in English and Chinese.
School code: 1307.
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Lai, Minghorng. "New algorithms for physical design of VLSI circuits." 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3099471.
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Tang, Xiaoping. "Fundamental algorithms for physical design planning of VLSI." Thesis, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3086713.
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LI, SHI-GIN, and 李世欽. "In-memory data management supports for an integrated VLSI design automation framework." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/15398081368080525523.
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Cho, Minsik 1976. "Physical synthesis for nanometer VLSI and emerging technologies." 2008. http://hdl.handle.net/2152/17814.
Full textAbstract:
The unabated silicon technology scaling makes design and manufacturing increasingly harder in nanometer VLSI. Emerging technologies on the horizon require strong design automation to handle the large complexity of future systems. This dissertation studies eight related research topics in design and manufacturing closure in nanometer VLSI as well as design optimization for emerging technologies from physical synthesis perspective. In physical synthesis for design closure, we study three research topics, which are key challenges in nanometer VLSI designs: (a) We propose a highly efficient floorplanning algorithm to minimize substrate noise for mixed-signal system-on-a-chip designs. (b) We propose a clock tree synthesis algorithm to reduce clock skew under thermal variation. (c) We develop a global router, BoxRouter to enhance routability which is one of the classic but still critical challenges in modern VLSI. In physical synthesis for manufacturing closure, we propose the first systematic manufacturability aware routing framework to address three key manufacturing challenges: (a) We develop a predictive chemical-mechanical polishing model to guide global routing in order to reduce surface topography variation. (b) We formulate a random defect minimize problem in track routing, and develop a highly efficient algorithm. (b) We propose a lithography enhancement technique during detailed routing based on statistical and macro-level Post-OPC printability prediction. Regarding design optimization of emerging technologies, we focus on two topics, one in double patterning technology for future VLSI fabrication and the other in microfluidics for biochips: (a) We claim double patterning should be considered during physical synthesis, and propose an effective double patterning technology aware detailed routing algorithm. (b) We propose a droplet routing algorithm to improve routability in digital microfluidic biochip design.text
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Chy-Hui, Hong. "Interconnect Delay Bound Generator for VLSI Physical Design Synthesis." 2000. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611304167.
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Hong, Chy-Hui, and 洪旗徽. "Interconnect Delay Bound Generator for VLSI Physical Design Synthesis." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/57972351684588043282.
Full textAbstract:
碩士元智大學
資訊工程研究所
88
Though the net-length bound driven placement has long been questioned by many designers about its feasibility, it is worth revisiting this approach given that net length bounds can be adapted for the progress of the placement process. In response to an attempt to develop an interconnect length driven standard cell placer (ILDPer) by a colleague in our laboratory, this thesis proposes to develop a net delay (length) bound generator to support its development. The past research has been focused more on generating bound for each net without considering the influence of false paths. To consider the interconnect RC effect, our bound generator will compute for each source-sink pair a delay bound with exclusion of static false paths. Several strategies of net weight assignment and the limitation of the maximum and minimum delay bounds are employed to make the delay bound more reasonable. The bound generator which is integrated into the ILDPer can dynamically generate, upon a request by the ILDPer, a new set of delay bound based on current partial placement. As time goes by, the partial placement will provide more accurate cell position such that the new set of net delay bounds is easier to satisfy. Some MCNC benchmark circuits are used to evaluate the efficiency and correctness. The experimental results show the employment of using delay bounds to influence the movement of cells is viable. The longest path delays are improved up to 32% when compared to those obtained by Cadence Silicon Ensemble.
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Samanta, Radhamanjari. "Timing-Driven Routing in VLSI Physical Design Under Uncertainty." Thesis, 2013. http://etd.iisc.ernet.in/2005/3444.
Full textAbstract:
The multi-net Global Routing Problem (GRP) in VLSI physical design is a problem of routing a set of nets subject to limited resources and delay constraints. Various state-of-the-art routers are available but their main focus is to optimize the wire length and minimize the over ow. However optimizing wire length do not necessarily meet timing constraints at the sink nodes. Also, in modern nano-meter scale VLSI process the consideration of process variations is a necessity for ensuring reasonable yield at the fab. In this work, we try to nd a fundamental strategy to address the timing-driven Steiner tree construction (i.e., the routing) problem subject to congestion constraints and process variation.
For congestion mitigation, a gradient based concurrent approach (over all nets) of Erzin et. al., rather than the traditional (sequential) rip-and-reroute is adopted in or- der to propagate the timing/delay-driven property of the Steiner tree candidates. The existing sequential rip-up and reroute methods meet the over ow constraint locally but cannot propagate the timing constraint which is non-local in nature. We build on this approach to accommodate the variation-aware statistical delay/timing requirements.
To further reduce the congestion, the cost function of the tree generation method is updated by adding history based congestion penalty to the base cost (delay). Iterative use of the timing-driven Steiner tree construction method and history based tree construction procedure generate a diverse pool of candidate Steiner trees for each net. The gradient algorithm picks one tree for each net from the pool of trees such that congestion is e ciently controlled.
As the technology scales down, process variation makes process dependent param- eters like resistance, capacitance etc non-deterministic. As a result, Statistical Static Timing Analysis or SSTA has replaced the traditional static timing in nano-meter scale VLSI processes. However, this poses a challenge regarding the max/min-plus algebra of Dijkstra like approximation algorithm that builds the Steiner trees. A new approach based on distance between distributions for nding maximum/minimum at the nodes is presented in this thesis. Under this metric, the approximation algorithm for variation aware timing driven congestion constrained routing is shown to be provably tight and one order of magnitude faster than existing approaches (which are not tight) such as the MVERT.
The results (mean value) of our variation aware router are quite close to the mean of the several thousand Monte Carlo simulations of the deterministic router, i.e the results converge in mean. Therefore, instead of running so many deterministic Monte Carlo simulations, we can generate an average design with a probability distribution reasonably close to that of the actual behaviour of the design by running the proposed statistical router only once and at a small fraction of the computational e ort involved in physical design in the nano regime VLSI.
The above approximation algorithm is extended to local routing, especially non- Manhattan lambda routing which is increasingly being allowed by the recent VLSI tech- nology nodes. Here also, we can meet delay driven constraints better and keep related wire lengths reasonable.
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Liu, Yifang. "Algorithms for VLSI Circuit Optimization and GPU-Based Parallelization." 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7770.
Full textAbstract:
This research addresses some critical challenges in various problems of VLSI design
automation, including sophisticated solution search on DAG topology, simultaneous
multi-stage design optimization, optimization on multi-scenario and multi-core
designs, and GPU-based parallel computing for runtime acceleration.
Discrete optimization for VLSI design automation problems is often quite complex,
due to the inconsistency and interference between solutions on reconvergent
paths in directed acyclic graph (DAG). This research proposes a systematic solution
search guided by a global view of the solution space. The key idea of the proposal
is joint relaxation and restriction (JRR), which is similar in spirit to mathematical
relaxation techniques, such as Lagrangian relaxation. Here, the relaxation and
restriction together provides a global view, and iteratively improves the solution.
Traditionally, circuit optimization is carried out in a sequence of separate optimization
stages. The problem with sequential optimization is that the best solution
in one stage may be worse for another. To overcome this difficulty, we take the approach
of performing multiple optimization techniques simultaneously. By searching
in the combined solution space of multiple optimization techniques, a broader view
of the problem leads to the overall better optimization result. This research takes
this approach on two problems, namely, simultaneous technology mapping and cell placement, and simultaneous gate sizing and threshold voltage assignment.
Modern processors have multiple working modes, which trade off between power
consumption and performance, or to maintain certain performance level in a powerefficient
way. As a result, the design of a circuit needs to accommodate different
scenarios, such as different supply voltage settings. This research deals with this
multi-scenario optimization problem with Lagrangian relaxation technique. Multiple
scenarios are taken care of simultaneously through the balance by Lagrangian multipliers.
Similarly, multiple objective and constraints are simultaneously dealt with by
Lagrangian relaxation. This research proposed a new method to calculate the subgradients
of the Lagrangian function, and solve the Lagrangian dual problem more
effectively.
Multi-core architecture also poses new problems and challenges to design automation.
For example, multiple cores on the same chip may have identical design
in some part, while differ from each other in the rest. In the case of buffer insertion,
the identical part have to be carefully optimized for all the cores with different
environmental parameters. This problem has much higher complexity compared to
buffer insertion on single cores. This research proposes an algorithm that optimizes
the buffering solution for multiple cores simultaneously, based on critical component
analysis.
Under the intensifying time-to-market pressure, circuit optimization not only
needs to find high quality solutions, but also has to come up with the result fast.
Recent advance in general purpose graphics processing unit (GPGPU) technology
provides massive parallel computing power. This research turns the complex computation
task of circuit optimization into many subtasks processed by parallel threads.
The proposed task partitioning and scheduling methods take advantage of the GPU
computing power, achieve significant speedup without sacrifice on the solution quality.
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Ward, Samuel Isaac. "Physical design automation of structured high-performance integrated circuits." 2013. http://hdl.handle.net/2152/23089.
Full textAbstract:
During the last forty years, advancements have pushed state-of-the-art placers to impressive performance placing modern multimillion gate designs in under an hour.
Wide industry adoption of the analytical framework indicates the quality of these approaches. However, modern designs present significant challenges to address the multi objective requirements for multi GHz designs. As devices continue to scale, wires become more resistive and power constraints significantly dampen performance gains, continued improvement in placement quality is necessary. Additionally, placement has become more challenging with the integration of multi-objective constraints such as routability, timing and reliability. These constraints intensify the challenge of producing quality placement solutions and must be handled carefully. Exasperating the issue, shrinking schedules and budgets are requiring increased automation by blurring the boundary between manual and automated placement. An example of this new hybrid design style is the integration of structured placement constraints within traditional ASIC style circuit structures.
Structure aware placement is a significant challenge to modern high performance physical design flows. The goal of this dissertation is to develop enhancements to state-of-the-art placement flows overcoming inadequacies for structured circuits.
A key observation is that specific structures exist where modern analytical placement frameworks significantly underperform. Accurately measuring suboptimality of a particular placement solution however is very challenging. As such, this work begins by designing a series of structured placement benchmarks. Generating placement for the benchmarks manually offers the opportunity to accurately quantify placer performance. Then, the latest generation of academic placers is compared to evaluate how the placers performed for these design styles. Results of this work lead to discoveries in three key aspects of modern physical design flows.
Datapath placement is the first aspect to be examined.
This work narrows the focus to specifically target datapath style circuits that contain high fanout nets. As the datapath benchmarks showed, these high fanout nets misdirect analytical placement flows. To effectively handle these circuit styles, this work proposes a new unified placement flow that simultaneously places random-logic and datapath cells. The flow is built on top of a leading academic force-directed placer and significantly improves the quality of datapath placement while leveraging the speed and flexibility of existing algorithms.
Effectively placing these circuits is not enough because in modern high performance designs, datapath circuits are often embedded within a larger ASIC style circuit and thus are unknown. As such, the next aspect of structured placement applies novel data learning techniques to train, predict, and evaluate potential structured circuits. Extracted circuits are mapped to groups that are aligned and simultaneously placed with random logic.
The third aspect that can be enhanced with improved structured placement impacts local clock tree synthesis. Performance and power requirements for multi-GHz microprocessors necessitate the use of a grid-based clock network methodology, wherein a global clock grid is overlaid on the entire die area followed by local buffered clock trees. This clock mesh methodology is driven by three key reasons: First, full trees do not offer enough performance for modern microprocessors. Second, clock trees offer significant power savings over full clock meshes. Third, local clock trees reduce the local clock wiring demands compared to full meshes at lower level metal layers. To meet these demands, a shift in latch placement methodology is proposed by using structured placement templates.
Placement configurations are identified a priori with significantly lower capacitance and the solutions are developed into placement templates.
Results through careful experimentation demonstrate the effectiveness of these approaches and the impact potential for modern high-speed designs.text
50
Huang, Chun-wei, and 黃峻維. "PHYSICAL DESIGN AND DESIGN AUTOMATION OF FREEZE METAL-INTERCONNECTION-LAYER ECO ROUTING." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/15149838180663067688.
Full textAbstract:
碩士大同大學
電機工程學系(所)
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ECO routing is a key step in back-end place-and-route EDA tool. Right after functional ECO, a designer incrementally re-routes the IC design by re-connecting the new and broken nets due to ECO circuit reconstruction. Usually, due to time-to-market pressure at late design phase, Fully-ECO, Metal-Only ECO and Focused Ion Beam are selectively adopted to speed-out a chip’s production. Re-using and preserving existing routes like metal wires and vias in a design are becoming critical and important for better timing convergence and saving cost of lithography masks. However, many of current back-end tools do not fully support the feature of re-use-and-preserve existing routes, especially on lower metal layers. The cost of lithography mask synthesis on these lower layers is much higher than the others above. In this thesis, a new solution on freeze-layer ECO routing is proposed. It includes an automatic tracking and re-naming script utility and recommended routing methodology that ECO router can preserve and utilize the wire and via at lower layers. The experimental results show that the proposed ECO script utility and methodology save the manufacturing cost on lower mask layers and also optimize the design routes to achieve more possibility and layers for freeze-layer ECO routing.