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Journal articles on the topic 'VLSI physical design automation'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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1

Bell, I. M. "Physical design automation of VLSI systems." Microelectronics Journal 24, no. 5 (August 1993): 592–93. http://dx.doi.org/10.1016/0026-2692(93)90141-z.

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2

Shanavas, I. Hameem, and R. K. Gnanamurthy. "Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.

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In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.
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3

YEAP, GARY, and ANDREAS WILD. "INTRODUCTION TO LOW-POWER VLSI DESIGN." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 223–48. http://dx.doi.org/10.1142/s0129156496000098.

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The paper is a survey of the current status of research and practices in various disciplines of low-power VLSI developments. After briefly discussing the rationale of the contemporary focus on low-power design, it presents the metrics and techniques used to assess the merits of the various solutions proposed for improved energy efficiency. The requirements to be fulfilled by process technologies and device structures are reviewed as well as several promising circuit design styles and ad hoc design techniques. The impact of the design automation tools is analyzed with a special emphasis on physical design and logic synthesis. A review of various architectural trade-offs, including power management, parallelism and pipelining, synchronous versus asynchronous architectures and dataflow transformations are covered, followed by a brief discussion of the impact of the system definition, software and algorithms to the overall power efficiency. Emerging semiconductor technologies and device structures are discussed and the paper is concluded with the trends and research topics for the future.
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4

Saha Sau, Swagata, and Rajat Kumar Pal. "Difficult Channel Instance Generator for VLSI Physical Design Automation using Genetic Algorithm." Indian Journal of Science and Technology 10, no. 13 (April 1, 2017): 1–8. http://dx.doi.org/10.17485/ijst/2017/v10i13/102925.

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5

Shanavas, I. Hameem, and Ramaswamy Kannan Gnanamurthy. "Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms." VLSI Design 2011 (October 12, 2011): 1–9. http://dx.doi.org/10.1155/2011/896241.

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Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.
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Kundu, Sudeshna, Suchismita Roy, and Shyamapada Mukherjee. "Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology." Journal of Circuits, Systems and Computers 29, no. 04 (July 5, 2019): 2050057. http://dx.doi.org/10.1142/s0218126620500577.

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Rectilinear Steiner Tree (RST) construction is a fundamental problem in very large scale integration (VLSI) physical design. Its applications include placement and routing in VLSI physical design automation (PDA) where wire length and timing estimations for signal nets are obtained. In this paper, a pseudo-Boolean satisfiability (PB-SAT)-based approach is presented to solve rectilinear Steiner tree problem. But large nets are a bottleneck for any SAT-based approach. Hence, to deal with large nets, a region-partitioning-based algorithm is taken into consideration, which eventually achieves a reasonable running time. Furthermore, a clustering-based approach is also explored to improve the partitioning of nets by identifying clusters and then applying a heuristic-based approach to get the minimum wire length for each set of the clusters. Experimental results obtained by these techniques show that the proposed algorithm can solve the RST problem very effectively even on large circuits and it outperforms the widely used RST algorithm FLUTE with 3[Formula: see text][Formula: see text][Formula: see text]to 9[Formula: see text][Formula: see text][Formula: see text]speedups.
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7

CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (December 1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.

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In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.
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8

Palchaudhuri, Ayan, Sandeep Sharma, and Anindya Sundar Dhar. "Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion." ACM Transactions on Design Automation of Electronic Systems 26, no. 4 (April 2021): 1–34. http://dx.doi.org/10.1145/3446206.

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Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.
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9

Topisirovic, Dragan. "Advances in VLSI testing at MultiGb per second rates." Serbian Journal of Electrical Engineering 2, no. 1 (2005): 43–55. http://dx.doi.org/10.2298/sjee0501043t.

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Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps). Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability) methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment) resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator) patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.
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10

Chaudhry, M. A. R., Z. Asad, A. Sprintson, and J. Hu. "Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies." VLSI Design 2011 (April 28, 2011): 1–9. http://dx.doi.org/10.1155/2011/892310.

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In the advent of smaller devices, a significant increase in the density of on-chip components has raised congestion and overflow as critical issues in VLSI physical design automation. In this paper, we present novel techniques for reducing congestion and minimizing overflows. Our methods are based on ripping up nets that go through the congested areas and replacing them with congestion-aware topologies. Our contributions can be summarized as follows. First, we present several efficient algorithms for finding congestion-aware Steiner trees that is, trees that avoid congested areas of the chip. Next, we show that the novel technique of network coding can lead to further improvements in routability, reduction of congestion, and overflow avoidance. Finally, we present an algorithm for identifying efficient congestion-aware network coding topologies. We evaluate the performance of the proposed algorithms through extensive simulations.
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11

Yan, Jin-Tai. "An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement." VLSI Design 10, no. 2 (January 1, 1999): 169–76. http://dx.doi.org/10.1155/1999/59138.

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It is well known that standard cells have been widely used to implement VLSI circuits in the automation of physical design. Since one major aim of a cell-based design is to minimize total layout area in a standard cell placement, the number of feedthrough cells will be minimized to reduce total cell area in a standard cell placement. In this paper, first, we model a partitioning-based row assignment (PRA) problem to minimize the number of feedthrough cells in a standard cell placement. Furthermore, an integer linear programming (ILP) approach is proposed to solve the PRA problem in a standard cell placement. Finally, the ILP approach has been implemented and two standard-cell netlists, Primary 1 and Primary 2, have been tested by the proposed approach, Bose's approach [4] and an exhaustive search approach, respectively. The experimental results show that the ILP approach obtains fewer feedthrough cells than Bose's approach in a partitioning-based standard cell placement.
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12

Wu, P. "Analog VLSI Design Automation [Book Review]." IEEE Circuits and Devices Magazine 21, no. 3 (May 2005): 53–54. http://dx.doi.org/10.1109/mcd.2005.1438816.

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13

Kozawa, Tokinori, and Hidekazu Terai. "Research in Design Automation for VLSI Layout." IEEE Design & Test of Computers 2, no. 5 (1985): 43–53. http://dx.doi.org/10.1109/mdt.1985.294816.

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14

DeMaris, D. L. "Visualization in a VLSI design automation system." IBM Journal of Research and Development 35, no. 1.2 (January 1991): 238–43. http://dx.doi.org/10.1147/rd.351.0238.

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15

Karatsu, O., T. Hoshino, M. Endo, H. Kitazawa, T. Adachi, and K. Ueda. "An Integrated Design Automation System for VLSI Circuits." IEEE Design & Test of Computers 2, no. 5 (1985): 17–26. http://dx.doi.org/10.1109/mdt.1985.294812.

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16

Masud, Manzer, and Sadiq Sait M. "Universal AHPL — A language for VLSI design automation." IEEE Circuits and Devices Magazine 2, no. 5 (September 1986): 8–13. http://dx.doi.org/10.1109/mcd.1986.6311871.

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17

Kowalski, Thaddeus J. "The VLSI Design Automation Assistant: A Synthesis Expert." AT&T Technical Journal 67, no. 1 (January 2, 1988): 81–92. http://dx.doi.org/10.1002/j.1538-7305.1988.tb00236.x.

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18

Kowalski, T. J., D. J. Geiger, W. H. Wolf, and W. Fichtner. "The VLSI Design Automation Assistant: From Algorithms to Silicon." IEEE Design & Test of Computers 2, no. 4 (August 1985): 33–43. http://dx.doi.org/10.1109/mdt.1985.294721.

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19

Simunic, T., J. W. Rozenblit, and J. R. Brews. "VLSI interconnect design automation using quantitative and symbolic techniques." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 19, no. 4 (1996): 803–12. http://dx.doi.org/10.1109/96.544372.

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20

Manganaro, G. "Genetic algorithms for VLSI design, layout, and test automation [Reviews]." IEEE Circuits and Devices Magazine 16, no. 2 (March 2000): 34. http://dx.doi.org/10.1109/mcd.2000.833032.

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21

Liu, Yanpei. "Orthogonal drawings of graphs for the automation of VLSI circuit design." Journal of Computer Science and Technology 14, no. 5 (September 1999): 447–59. http://dx.doi.org/10.1007/bf02948786.

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22

Janiak, Adam, Andrzej Kozik, and Maciej Lichtenstein. "New perspectives in VLSI design automation: deterministic packing by Sequence Pair." Annals of Operations Research 179, no. 1 (November 13, 2008): 35–56. http://dx.doi.org/10.1007/s10479-008-0460-9.

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23

Szczęsny, S., M. Naumowicz, and A. Handkiewicz. "SI-Studio – environment for SI circuits design automation." Bulletin of the Polish Academy of Sciences: Technical Sciences 60, no. 4 (December 1, 2012): 757–62. http://dx.doi.org/10.2478/v10175-012-0087-5.

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Abstract The current work is an answer to the problem of designing switched-current (SI) circuits, which is usually a complex issue in the field of microelectronics. The mentioned task is a source of many mistakes and takes a lot of time for designers, therefore authors of the article decided to propose a software solution. This article presents an environment for design automation of analogue circuits in the switched currents technique. It points out the utility advantages of the described tools, which make the work of a VLSI designer much easier, moreover offering a possibility to parameterise the design process considering power consumption, chip area usage and its working speed. It also presents results of an automatic generation of a filter pair circuit, as well as a DCT circuit - automatically generated with the proposed SI-Studio software tools.
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24

Zhou, Dian, and Rui-Ming Li. "Design and Verification of High-Speed VLSI Physical Design." Journal of Computer Science and Technology 20, no. 2 (March 2005): 147–65. http://dx.doi.org/10.1007/s11390-005-0147-5.

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25

Ziesemer, Adriel Mota, and Ricardo Reis. "Physical design automation of transistor networks." Microelectronic Engineering 148 (December 2015): 122–28. http://dx.doi.org/10.1016/j.mee.2015.10.018.

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26

Lee, H. R., C. W. Jen, and C. M. Liu. "On the design automation of the memory-based VLSI architectures for FIR filters." IEEE Transactions on Consumer Electronics 39, no. 3 (1993): 619–29. http://dx.doi.org/10.1109/30.234644.

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27

Schulz, Uwe. "Hierarchical physical design system for VLSI-/370 microprocessor." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 131–35. http://dx.doi.org/10.1016/0165-6074(88)90042-7.

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28

Levitt, M. E., and J. A. Abraham. "Physical design of testable VLSI: techniques and experiments." IEEE Journal of Solid-State Circuits 25, no. 2 (April 1990): 474–81. http://dx.doi.org/10.1109/4.52172.

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29

Saha, D., and S. Sur-Kolay. "Robust intellectual property protection of VLSI physical design." IET Computers & Digital Techniques 4, no. 5 (September 1, 2010): 388–99. http://dx.doi.org/10.1049/iet-cdt.2008.0152.

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30

Wu, Clara. "VLSI-TSA and VLSI-DAT to Convene on 21–25 April in Hsinchu, Taiwan, 15th International Symposium on VLSI Technology, Systems, and Applications & 4th VLSI Design, Automation and Test." IEEE Solid-State Circuits Newsletter 13, no. 1 (2008): 69. http://dx.doi.org/10.1109/n-ssc.2008.4785705.

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31

Khan, Ajoy Kumar. "A Review on Channel Routing On VLSI Physical Design." IOSR Journal of Computer Engineering 5, no. 1 (2012): 41–48. http://dx.doi.org/10.9790/0661-0514148.

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32

Ravikumar, C. P. "Solving VLSI physical design problems on a vector machine." Computer-Aided Design 25, no. 1 (January 1993): 49–57. http://dx.doi.org/10.1016/0010-4485(93)90065-v.

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33

Howard, Neil J., Andrew M. Tyrrell, and Nigel M. Allinson. "The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks." VLSI Design 4, no. 2 (January 1, 1996): 135–39. http://dx.doi.org/10.1155/1996/17505.

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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.
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34

Dhiraj, Dhiraj, Seema Verma, Rajesh Kumar, and Himanshu Choudhary. "A enhanced algorithm for floorplan design using evolutionary technique." Artificial Intelligence Research 1, no. 2 (August 30, 2012): 38. http://dx.doi.org/10.5430/air.v1n2p38.

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Floor planning is an important problem in very large scale integrated-circuit (VLSI) design automation domain as it evaluates the performance, size, yield and reliability of ICs. Due to rapid increase in number of components on a chip, floor planning has gained its importance further in determining the quality of the design achieved. In this paper we have devised an approach for placement of modules in a given area with bounding constraints in terms of minimum placement area imposed. We have used Modified Genetic Algorithm (MGA) technique for determining and obtaining an optimal placement using an iterative approach.
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35

Wilson, John. "Automation and work design." Applied Ergonomics 17, no. 1 (March 1986): 67–68. http://dx.doi.org/10.1016/0003-6870(86)90200-0.

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36

AHMED, HASSAN M., and FAWAD RAUF. "PARALLEL, LOCALLY CONNECTED ALGORITHMS FOR NONLINEAR ADAPTIVE FILTERING." International Journal of High Speed Electronics and Systems 04, no. 01 (March 1993): 85–98. http://dx.doi.org/10.1142/s0129156493000066.

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A new adaptive modular realization for nonlinear filters is presented whereby construction is both computationally efficient and readily implemented. The proposed layered structure consists of locally connected, locally adapted linear filters. Modularity and local connectivity make efficient VLSI layout easy and amenable to automation. The layered structure is based on "state dependent embedding", a new approach to the design of series based nonlinear adaptive filters.
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37

Hu, Shiyan, Xiaobo Sharon Hu, and Albert Y. Zomaya. "Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 5 (May 2016): 697–98. http://dx.doi.org/10.1109/tcad.2016.2548179.

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38

Mukherjee, Maharaj, and Kanad Chakraborty. "A polynomial-time optimization algorithm for a rectilinear partitioning problem with applications in VLSI design automation." Information Processing Letters 83, no. 1 (July 2002): 41–48. http://dx.doi.org/10.1016/s0020-0190(01)00305-2.

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39

Souza, Ilan Schnitman, and V. T. Dos Reis. "A VLSI Design for the LTE Turbo Decoder." Journal of Integrated Circuits and Systems 7, no. 1 (December 27, 2012): 16–22. http://dx.doi.org/10.29292/jics.v7i1.352.

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Due to the need of high performance, new wireless telecommunications standards such asWIMAX and LTE are using turbo-codes as a forward error correction (FEC) choice.This design targets either a self-contained IP (Intellectual Property) or integration into the physical layer project. This work presents all steps for the implementation of an LTE standard turbo decoder: from algorithm modeling in high level programming language to architecture using a sliding window approach seeking throughput needed, getting into physical implementation at TSMC 65nm. Each aspect of the specification and performance were analyzed in their proper stages.
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40

Zhu, Qi, Alberto Sangiovanni-Vincentelli, Shiyan Hu, and Xin Li. "Design Automation for Cyber-Physical Systems [Scanning the Issue]." Proceedings of the IEEE 106, no. 9 (September 2018): 1479–83. http://dx.doi.org/10.1109/jproc.2018.2865229.

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41

Nazeer Hussain, S., and K. Hari Kishore. "Performance evaluation of heuristic algorithms in floor planning for ASIC design." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 56. http://dx.doi.org/10.14419/ijet.v7i1.5.9122.

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A study on physical design of VLSI Floor planning is discussed using optimization techniques for betterment in performance of VLSI chip. Floor planning in VLSI is considered to be a Non Polynomial problem. Such problems can be solved using computations. The initial step in floor plan is the representation of floor plan design. The floor plan representations show greater impact on the search space and the complexity of the floor plan design. The objective of this paper is to study different algorithms that addressees the problem of handling alignment constraints such as good placement, optimum area and short run time. Different heuristic and meta-heuristic algorithms are proposed and suggested by many researchers for solving the VLSI Floor plan problem. In this paper Simulated Annealing algorithm, Ant Colony Algorithm, Tabu search and Genetic algorithms are discussed.
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42

Seshia, Sanjit A., Shiyan Hu, Wenchao Li, and Qi Zhu. "Design Automation of Cyber-Physical Systems: Challenges, Advances, and Opportunities." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 9 (September 2017): 1421–34. http://dx.doi.org/10.1109/tcad.2016.2633961.

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43

Hurson, A. R., and S. Pakzad. "Modular Scheme for Designing Special Purpose Associative Memories and Beyond." VLSI Design 2, no. 3 (January 1, 1994): 267–86. http://dx.doi.org/10.1155/1994/83851.

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The use of associative memories—storage devices that allow data retrieval based on contents—has often been suggested to speed up the performance of many applications. Until recently, using such content-addressable memories (CAMs) was unfeasible due to their high hardware cost. However, the advent of VLSI has made the class of fully-parallel associative memory cost-effective for implementation. This paper briefly overviews design of several fully parallel associative memories proposed in the literature, concentrating on the design of fully-parallel θ-search CAMs.Existing market realities require that product development be fast and predictable. As a result, design flexibility and automation are becoming increasingly important design features. Using the various CAM designs reviewed, the paper collects the features of these designs into a general, modular CAM organization and describes its major components. The modular CAM organization can be used to design application specific CAMs of varying degrees of functionality. Design and space complexity of a sample associative memory suitable for relational database operations is studied. Finally, the application of genetic algorithms as a means to developing automated design tools for fabrication of modular VLSI design chips is discussed.Given a library of CAM modules, the desired functionality and a set of speed and area constraints, this optimization technique produces a suitable CAM design. The proposed technique has been implemented and its performance measure is briefly addressed.
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44

Sinha, Bhargab, Sourav Nath, and Krishna Lal Baishnab. "A hybrid RFD-ACO approach for routing optimization in VLSI physical design." Journal of Information and Optimization Sciences 39, no. 1 (November 15, 2017): 53–66. http://dx.doi.org/10.1080/02522667.2017.1372910.

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45

Mary Reena, Kottarathil Eashy, Abraham Theckethil Mathew, and Lillykutty Jacob. "An Occupancy Based Cyber-Physical System Design for Intelligent Building Automation." Mathematical Problems in Engineering 2015 (2015): 1–15. http://dx.doi.org/10.1155/2015/132182.

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Cyber-physical system (CPS) includes the class of Intelligent Building Automation System (IBAS) which increasingly utilizes advanced technologies for long term stability, economy, longevity, and user comfort. However, there are diverse issues associated with wireless interconnection of the sensors, controllers, and power consuming physical end devices. In this paper, a novel architecture of CPS for wireless networked IBAS with priority-based access mechanism is proposed for zones in a large building with dynamically varying occupancy. Priority status of zones based on occupancy is determined using fuzzy inference engine. Nondominated Sorting Genetic Algorithm-II (NSGA-II) is used to solve the optimization problem involving conflicting demands of minimizing total energy consumption and maximizing occupant comfort levels in building. An algorithm is proposed for power scheduling in sensor nodes to reduce their energy consumption. Wi-Fi with Elimination-Yield Nonpreemptive Multiple Access (EY-NPMA) scheme is used for assigning priority among nodes for wireless channel access. Controller design techniques are also proposed for ensuring the stability of the closed loop control of IBAS in the presence of packet dropouts due to unreliable network links.
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Chen, Xiaodao, Dongmei Zhang, Lizhe Wang, Ning Jia, Zhijiang Kang, Yun Zhang, and Shiyan Hu. "Design Automation for Interwell Connectivity Estimation in Petroleum Cyber-Physical Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 2 (February 2017): 255–64. http://dx.doi.org/10.1109/tcad.2016.2584065.

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Mongush, Amyrtaa K., and Igor N. Karmanov. "AUTOMATION OF COMPLEX INFORMATION SECURITY SYSTEMS DESIGN." Interexpo GEO-Siberia 6, no. 2 (July 8, 2020): 31–35. http://dx.doi.org/10.33764/2618-981x-2020-6-2-31-35.

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Entry of modern society into the information stage of development wake, information security one of the most important problems of our time. The article discusses the possibility of automating the design of an integrated information security system. One of the key stages in the design of an information security system is the assessment of the current state of the information security system through audit. An information security audit allows identifying all vulnerabilities in the system. To automate the detection of vulnerabilities of the investigated object, network scanners are considered. The use of scanners allows solving the problems of identification and analysis of vulnerabilities. A scheme for automating the design of physical protection systems is also considered. In conclusion, the advantages of automating the design of an information protection system are noted, frequently used software tools and utilities for automating individual stages of the design of information protection systems are presented.
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Palchaudhuri, Ayan, and Anindya Sundar Dhar. "Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies." Journal of Parallel and Distributed Computing 130 (August 2019): 110–25. http://dx.doi.org/10.1016/j.jpdc.2019.03.021.

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Ravikumar, D., Arun Raaza, V. Devi, and E. Gopinathan. "A genetic algorithm approach for global routing of VLSI circuits." International Journal of Engineering & Technology 7, no. 2.21 (April 20, 2018): 394. http://dx.doi.org/10.14419/ijet.v7i2.21.12450.

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Very Large Scale Integrating (VLSI) design has the objectives of producing the layout for integrating circuits. The currently prevalent submicron regions require innovative, new physical design algorithms. Performance requirements have not seen before, become the significant features of such regions. The last ten years have been witnessing the feature of swelling success of Genetic Algorithms in their application to VLSI physical design. These algorithms are in spot light and the subject matter of study and examination. Routing problem is posed to a cost function which takes care of the total net length, the channel capacity exceedance and crosstalk. The Genetic algorithm is used for optimizing the cost function.
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Teodorov, Ciprian, and Loïc Lagadec. "Model-driven physical-design automation for FPGAs: fast prototyping and legacy reuse." Software: Practice and Experience 44, no. 4 (March 6, 2013): 455–82. http://dx.doi.org/10.1002/spe.2190.

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