Relevant bibliographies by topics / VLSI Testing

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'VLSI Testing'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "VLSI Testing"

1

Karri, R., and M. Nicolaidis. "Online VLSI Testing." IEEE Design & Test of Computers 15, no. 4 (1998): 12–16. http://dx.doi.org/10.1109/mdt.1998.735922.

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Marnane, W. P., and W. R. Moore. "Testing VLSI regular arrays." Journal of Electronic Testing 6, no. 2 (1995): 153–77. http://dx.doi.org/10.1007/bf00993084.

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Birolini, A. "VLSI Testing And Screening." Journal of the IEST 32, no. 3 (1989): 42–48. http://dx.doi.org/10.17764/jiet.1.32.3.q4v5876615336jv8.

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Testing is necessary to verify that very large scale integration ICs (VLSI-ICs) conform to their specifications. This can grow from a more or less reduced incoming inspection test to a full qualification test consisting of a characterization, environmental tests, reliability tests, and failure analysis. The aim of a screening is to eliminate weak ICs that would cause early failures. This article presents the possibilities and limits of testing and screening very large scale integration ICs (VLSI-ICs). Practical results are given, and the procedures for the qualification of these ICs are discus
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Erényi, István. "VLSI testing and testability." Microprocessing and Microprogramming 38, no. 1-5 (1993): 221. http://dx.doi.org/10.1016/0165-6074(93)90147-d.

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Selvarasan R and Dr G. Sudhagar. "An Overview on Strategies to Perform VLSI Testing Productively Utilizing BIST." International Journal of Advanced Networking and Applications 16, no. 02 (2024): 6342–48. http://dx.doi.org/10.35444/ijana.2024.16205.

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A survey on techniques to perform VLSI Testing efficiently using BIST explores various methodologies to enhance Very Large-Scale Integration (VLSI) testing through Built-In-Self-Test (BIST) mechanism. The research delves into the significance of BIST controllers, such as the utilization of Low-Feedback Shift Registers (LFSR) for efficient testing. It also addresses the critical challenge of reducing test power in low-power VLSI circuits, emphasizing the need for innovative techniques to mitigate excessive power consumption during testing processes. Furthermore, the paper highlights the evoluti
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Rajsuman, R. "Iddq testing for CMOS VLSI." Proceedings of the IEEE 88, no. 4 (2000): 544–68. http://dx.doi.org/10.1109/5.843000.

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Atre, M. V., and D. Krishna Kumar. "Fuzzy Logic and VLSI Testing ." Defence Science Journal 45, no. 4 (1995): 325–32. http://dx.doi.org/10.14429/dsj.45.4140.

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Patnaik, L. M., H. S. Jamadagni, V. K. Agrawal, and B. K. S. V. L. Varaprasad. "The state of VLSI testing." IEEE Potentials 21, no. 3 (2002): 12–16. http://dx.doi.org/10.1109/mp.2002.1033655.

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Hurst, S. L. "IDDQ testing of VLSI circuits." Microelectronics Journal 25, no. 2 (1994): 139. http://dx.doi.org/10.1016/0026-2692(94)90112-0.

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Milovanović, Draeiša P. "Iddq Testing for CMOS VLSI." Microelectronics Journal 26, no. 4 (1995): xxiii. http://dx.doi.org/10.1016/0026-2692(95)90074-8.

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Dissertations / Theses on the topic "VLSI Testing"

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Hwang, Suntae. "VLSI testing for high reliability: Mixing IDDQ and logic testing." Case Western Reserve University School of Graduate Studies / OhioLINK, 1993. http://rave.ohiolink.edu/etdc/view?acc_num=case1056994488.

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Corliss, Walter F. "An engineering methodology for implementing and testing VLSI circuits." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/27024.

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The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested
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Nicolici, N. "Power minimisation techniques for testing low power VLSI circuits." Thesis, University of Southampton, 2000. https://eprints.soton.ac.uk/254107/.

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Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. The first part of this dissertation addresses power minimisation techniques in scan sequential circuits at the logic level of abstraction. A new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation
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Tung, Kenny W. L. Carleton University Dissertation Engineering Electronics. "A technique for on-chip analog VLSI circuit testing." Ottawa, 1993.

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Goel, Nita. "Syndrome signature in built-in self-testing of VLSI circuits." Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/9581.

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Testing has become very important in the context of modern VLSI and is a severe challenge for testing engineers. A number of basic analytic and heuristic methods exists for the solution of the fault detection and location problem in combinational circuits. Classical testing of combinational circuits requires a list of fault-free responses of the circuit to the test set. For most practical circuits implemented today, the large storage requirement makes the test procedure very expensive. In this thesis, a syndrome signature is proposed that is particularly well suited for exhaustive testing of V
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Besnard, Stéphane Claude Louis. "Optimising fault modelling and test development for VLSI analogue circuits." Thesis, University of Huddersfield, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503.

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Prasad, Abhijit. "Power supply partitioning for placement of built-in current sensors for IDDQ testing." Texas A&M University, 2003. http://hdl.handle.net/1969.1/103.

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IDDQ testing has been a very useful test screen for CMOS circuits. However, with each technology node the background leakage of chips is rapidly increasing. As a result it is becoming more difficult to distinguish between faulty and fault-free chips using IDDQ testing. Power supply partitioning has been proposed to increase test resolution by partitioning the power supply network, such that each partition has a relatively small defect-free IDDQ level. However, at present no practical partitioning strategy is available. The contribution of this thesis is to present a practical power supply part
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Botzas, Anthony. "Fabricating and testing a VLSI systolic convolution cell for image processing." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=26374.

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The two-dimensional discrete convolution operator is targeted for performance improvement in order to speed up image processing work loads. Since the large computation requirements for this operation are especially taxing to single processor computers, the approach is to consider parallel processing alternatives. Of the parallel processor classes considered, systolic arrays are singled out as the preferred parallel processing solution for the convolution problem.<br>Therefore, the design of a pipelined double precision floating point VLSI systolic cell for convolution is described. The arithme
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Poulos, Konstantinos. "NEW TECHNIQUES ON VLSI CIRCUIT TESTING & EFFICIENT IMPLEMENTATIONS OF ARITHMETIC OPERATIONS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1872.

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Testing is necessary factor to guarantee that ICs operate according to specifications before being delivered to customers. Testing is a process used to identify ICs containing imperfections or manufacturing defects that may cause failures. Inaccuracy and imperfections can be introduced during the fabrication of the chips due to the complex mechanical and chemical steps required during the manufacturing processes. The testing process step applies test patterns to circuits and analyzes their responses. This work focuses on VLSI circuit testing with two implementations for DFT (Design for testabi
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Eriksson, Jens. "Evaluation of Hardware Test Methods for VLSI Systems." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-239.

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<p>The increasing complexity and decreasing technology feature sizes of electronic designs has caused the challenge of testing to grow over the last decades. The purpose of this thesis was to evaluate different hardware test methods/approaches based on their applicability in a complex SoC design. Among the aspects that were investigated are test implementation effort, test efficiency and the performance penalties implicated by the test.</p><p>This report starts out by presenting a general introduction to the basics of hardware testing. It then moves on to review available standards and methodo
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Books on the topic "VLSI Testing"

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1958-, McIntyre Steven M., ed. Introduction to VLSI testing. Prentice Hall, 1988.

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V, Kachan I., ed. Self-testing VLSI design. Elsevier, 1993.

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Gulati, Ravi K. IDDQ Testing of VLSI Circuits. Springer US, 1993.

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Nicolaidis, Michael, Yervan Zorian, and Dhiraj K. Pradan, eds. On-Line Testing for VLSI. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-6069-9.

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Gulati, Ravi K., and Charles F. Hawkins, eds. IDDQ Testing of VLSI Circuits. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3146-3.

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Nicolaidis, Michael. On-Line Testing for VLSI. Springer US, 1998.

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1949-, Reghbati Hassan K., ed. Tutorial--VLSI testing & validation techniques. IEEE Computer Society Press, 1985.

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K, Gulati Ravi, and Hawkins Charles F, eds. IDDQ testing of VLSI circuits. Kluwer Academic Publishers, 1993.

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Reghbati, Hassan K. VLSI: Testing and validation techniques. IEEE Computer Society Press, 1985.

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Bhattacharya, Debashis. Hierarchical Modeling for VLSI Circuit Testing. Springer US, 1990.

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Book chapters on the topic "VLSI Testing"

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Chattopadhyay, Santanu. "VLSI Testing." In Thermal-Aware Testing of Digital VLSI Circuits and Systems. CRC Press, 2018. http://dx.doi.org/10.1201/9781351227780-1.

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Bhargava, Cherry, and Gaurav Mani Khanal. "Testing of VLSI Circuits." In Advanced VLSI Technology. River Publishers, 2022. http://dx.doi.org/10.1201/9781003337065-4.

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Wang, Laung-Terng, and Charles E. Stroud. "Fundamentals of VLSI Testing." In Power-Aware Testing and Test Strategies for Low Power Devices. Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_1.

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Dorey, A. P., B. K. Jones, A. M. D. Richardson, and Y. Z. Xu. "Introduction to VLSI Testing." In Rapid Reliability Assessment of VLSICs. Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-0587-3_1.

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Ma, Junxia, and Mohammad Tehranipoor. "Background on VLSI Testing." In Introduction to Hardware Security and Trust. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8080-9_1.

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Tehranipoor, Mohammad, Ke Peng, and Krishnendu Chakrabarty. "Introduction to VLSI Testing." In Test and Diagnosis for Small-Delay Defects. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8297-1_1.

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Sayil, Selahattin. "Contactless Testing." In Contactless VLSI Measurement and Testing Techniques. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69673-7_4.

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Saucier, G., C. Bellon, and M. Crastes De Paulet. "New Trends in VLSI Testing." In The Kluwer International Series in Engineering and Computer Science. Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-1985-6_18.

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Aharoni, Merav, Odellia Boni, Ari Freund, Lidor Goren, Wesam Ibraheem, and Tamir Segev. "Rectangle Placement for VLSI Testing." In Integration of AI and OR Techniques in Constraint Programming. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-18008-3_2.

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Collin, J. P., and B. Courtois. "Device Testing and Sem Testing Tools." In Testing and Diagnosis of VLSI and ULSI. Springer Netherlands, 1988. http://dx.doi.org/10.1007/978-94-009-1417-9_18.

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Conference papers on the topic "VLSI Testing"

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Aftabjahani, Sohrab, and Wilson Pradeep. "Security Verification and Secure Testing Solutions." In 2025 IEEE 43rd VLSI Test Symposium (VTS). IEEE, 2025. https://doi.org/10.1109/vts65138.2025.11022775.

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Rinitha, R., and R. Ponni. "Testing in VLSI: A survey." In 2016 International Conference on Emerging Trends in Engineering, Technology and Science (ICETETS). IEEE, 2016. http://dx.doi.org/10.1109/icetets.2016.7603068.

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Wen, Xiaoqing. "VLSI testing and test power." In 2011 International Green Computing Conference (IGCC). IEEE, 2011. http://dx.doi.org/10.1109/igcc.2011.6008607.

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Singh, Adit D. "Scan Delay Testing of Nanometer SoCs." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.134.

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Alluri, Lakshmaiah, and Hemant Jeevan Magadum. "Small Delay Tracing Defect Testing." In 7th International Conference on VLSI and Applications (VLSIA 2021). Academy and Industry Research Collaboration Center (AIRCC), 2021. http://dx.doi.org/10.5121/csit.2021.112101.

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This Small Delay Tracing Defect Testing detect small delay defects by creating internal signal races. The races are created by launching transitions along simultaneous two paths, a reference path and a test path. The arrival times of the transitions on a ‘convergence’ or common gate determine the result of the race. On the output of the convergence gate, a static hazard created by a small delay defect presence on the test path which is directed to the input of a scan-latch. A glitch detector is added to the scan latch which records the presence or absence of the glitch.
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Mohammad, Mohammad Gh, and Kewal K. Saluja. "Testing Flash Memories for Tunnel Oxide Defects." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.41.

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Goutzoulis, A. P., and P. J. Chantry. "Optical Techniques For Aiding VLSI Testing." In 30th Annual Technical Symposium, edited by William J. Miceli. SPIE, 1986. http://dx.doi.org/10.1117/12.976265.

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Maly, W. "Realistic fault modeling for VLSI testing." In 24th ACM/IEEE conference proceedings. ACM Press, 1987. http://dx.doi.org/10.1145/37888.37914.

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Akter, Naznin, Mustafa Karabiyik, Michael Shur, John Suarez, and Nezih Pala. "AI Powered THz VLSI Testing Technology." In 2020 IEEE 29th North Atlantic Test Workshop (NATW). IEEE, 2020. http://dx.doi.org/10.1109/natw49237.2020.9153077.

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Li, Chien-Mo. "Apply Machine Learning to IC Testing." In 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2021. http://dx.doi.org/10.1109/vlsi-dat52063.2021.9427351.

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Reports on the topic "VLSI Testing"

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Nguyen, Lau T., Linda G. Bushnell, and Vason P. Srini. The VLSI-PLM Board: Design, Construction, and Testing. Defense Technical Information Center, 1989. http://dx.doi.org/10.21236/ada631676.

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Valdmanis, Janis A. High Sensitivity Probes for Silicon VLSI Internal Node Testing. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada253924.

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