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Journal articles on the topic 'VLSI Testing'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Karri, R., and M. Nicolaidis. "Online VLSI Testing." IEEE Design & Test of Computers 15, no. 4 (1998): 12–16. http://dx.doi.org/10.1109/mdt.1998.735922.

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2

Marnane, W. P., and W. R. Moore. "Testing VLSI regular arrays." Journal of Electronic Testing 6, no. 2 (1995): 153–77. http://dx.doi.org/10.1007/bf00993084.

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3

Birolini, A. "VLSI Testing And Screening." Journal of the IEST 32, no. 3 (1989): 42–48. http://dx.doi.org/10.17764/jiet.1.32.3.q4v5876615336jv8.

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Testing is necessary to verify that very large scale integration ICs (VLSI-ICs) conform to their specifications. This can grow from a more or less reduced incoming inspection test to a full qualification test consisting of a characterization, environmental tests, reliability tests, and failure analysis. The aim of a screening is to eliminate weak ICs that would cause early failures. This article presents the possibilities and limits of testing and screening very large scale integration ICs (VLSI-ICs). Practical results are given, and the procedures for the qualification of these ICs are discus

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4

Erényi, István. "VLSI testing and testability." Microprocessing and Microprogramming 38, no. 1-5 (1993): 221. http://dx.doi.org/10.1016/0165-6074(93)90147-d.

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5

Selvarasan R and Dr G. Sudhagar. "An Overview on Strategies to Perform VLSI Testing Productively Utilizing BIST." International Journal of Advanced Networking and Applications 16, no. 02 (2024): 6342–48. http://dx.doi.org/10.35444/ijana.2024.16205.

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A survey on techniques to perform VLSI Testing efficiently using BIST explores various methodologies to enhance Very Large-Scale Integration (VLSI) testing through Built-In-Self-Test (BIST) mechanism. The research delves into the significance of BIST controllers, such as the utilization of Low-Feedback Shift Registers (LFSR) for efficient testing. It also addresses the critical challenge of reducing test power in low-power VLSI circuits, emphasizing the need for innovative techniques to mitigate excessive power consumption during testing processes. Furthermore, the paper highlights the evoluti

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6

Rajsuman, R. "Iddq testing for CMOS VLSI." Proceedings of the IEEE 88, no. 4 (2000): 544–68. http://dx.doi.org/10.1109/5.843000.

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7

Atre, M. V., and D. Krishna Kumar. "Fuzzy Logic and VLSI Testing ." Defence Science Journal 45, no. 4 (1995): 325–32. http://dx.doi.org/10.14429/dsj.45.4140.

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8

Patnaik, L. M., H. S. Jamadagni, V. K. Agrawal, and B. K. S. V. L. Varaprasad. "The state of VLSI testing." IEEE Potentials 21, no. 3 (2002): 12–16. http://dx.doi.org/10.1109/mp.2002.1033655.

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9

Hurst, S. L. "IDDQ testing of VLSI circuits." Microelectronics Journal 25, no. 2 (1994): 139. http://dx.doi.org/10.1016/0026-2692(94)90112-0.

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10

Milovanović, Draeiša P. "Iddq Testing for CMOS VLSI." Microelectronics Journal 26, no. 4 (1995): xxiii. http://dx.doi.org/10.1016/0026-2692(95)90074-8.

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11

Kulibaba, Andrey Ya, and Aleksey S. Silin. "Evaluating the Reliability Testing Acceleration Factor Based on VLSI Chip Infrared Image Analysis." Vestnik MEI, no. 6 (2021): 108–14. http://dx.doi.org/10.24160/1993-6982-2021-6-108-114.

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A new approach for evaluating the acceleration factor of forced reliability tests of very large scale integrated circuits (VLSI) is presented. The approach is based on subjecting the VLSI chip to an infrared image analysis. Currently, the VLSI reliability testing acceleration factor is evaluated based on the Arrhenius law, according to which this factor depends on the chip temperature. The chip temperature, in turn, is represented by the sum of the chip package temperature and the product of the maximum dissipated power and the chip-to-package thermal resistance. The drawback of the existing m

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12

Welch, E. F. "Book Review: Introduction to VLSI Testing." International Journal of Electrical Engineering & Education 26, no. 1-2 (1989): 190–91. http://dx.doi.org/10.1177/002072098902600138.

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13

Chieh-Yuan Chao, Hung-Jen Lin, and L. Miler. "Optimal testing of VLSI analog circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 1 (1997): 58–77. http://dx.doi.org/10.1109/43.559332.

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14

Torku, Kofi E., and Dave A. Kiesling. "Noise Problems in Testing VLSI Hardware." IEEE Design & Test of Computers 2, no. 6 (1985): 36–43. http://dx.doi.org/10.1109/mdt.1985.294795.

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15

Maurer, P. M. "Dynamic functional testing for VLSI circuits." IEEE Design & Test of Computers 7, no. 6 (1990): 42–49. http://dx.doi.org/10.1109/54.64956.

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16

Huang, W.-K., and F. Lombardi. "Self-testing approaches for VLSI arrays." IEE Proceedings E (Computers and Digital Techniques) 140, no. 3 (1993): 175–84. http://dx.doi.org/10.1049/ip-e.1993.0025.

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17

Hwang, S., and R. Rajsuman. "VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing." VLSI Design 5, no. 3 (1997): 299–311. http://dx.doi.org/10.1155/1997/59329.

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In this paper, we examine the effectiveness of combined logic and IDDQ testing to detect stuck-at and bridging faults. The stuck-at faults are detected by the logic test and IDDQ testing detects bridging faults.Near minimal stuck-at test sets are used for this combined logic and IDQQ test environment. These near minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits under this combined test environment. A comparison is given for the fault coverage obtained under this combined test environm

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18

Arya, Namita, and Amit Prakash Singh. "Comparative Analysis of Time and Physical Redundancy Techniques for Fault Detection." Indonesian Journal of Electrical Engineering and Computer Science 6, no. 1 (2017): 66. http://dx.doi.org/10.11591/ijeecs.v6.i1.pp66-71.

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<p>The integration level in today’s world is continuously increasing in VLSI chips. VLSI circuit verification is a major challenge in these days. Integration capacity of VLSI circuits mimics the testing complexity of circuits. There is a significant chunk of the testing cost with respect to the whole fabrication prices. Hence it is important to cut down the verification cost. Time required during testing is a main factor for the cost of a chip. This time is directly proportional to the number of testing in the circuitry. So the test set should be very small. There is one way to generate

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19

Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.

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Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.

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20

Dharanika, T., J. Jaya, and E. Nandakumar. "Design of Fostered Power Terahertz VLSI Testing Using Deep Neural Network and Embrace User Intent Optimization." Journal of Nanoelectronics and Optoelectronics 19, no. 7 (2024): 724–36. http://dx.doi.org/10.1166/jno.2024.3619.

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VLSI (Very Large-Scale Integration) testing is a crucial step in ensuring the reliability and functionality of integrated circuits. However, conventional testing methods often lack the ability to address user-specific requirements, resulting in suboptimal outcomes. Terahertz technology offers unique capabilities for non-destructive testing, yet its integration with VLSI testing methodologies remains limited. Additionally, the neglect of user preferences in testing processes poses a challenge to tailoring testing procedures to specific user needs. This research presents a novel approach for fos

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21

Esch, J. "Prolog to IDDQ testing for CMOS VLSI." Proceedings of the IEEE 88, no. 4 (2000): 542–43. http://dx.doi.org/10.1109/jproc.2000.842999.

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22

Jiang, Zhigang, and Sandeep K. Gupta. "Threshold Testing: Improving Yield for Nanoscale VLSI." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, no. 12 (2009): 1883–95. http://dx.doi.org/10.1109/tcad.2009.2032375.

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23

You, Y., and J. P. Hayes. "Implementation of VLSI self-testing by regularization." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 12 (1988): 1261–71. http://dx.doi.org/10.1109/43.16804.

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24

Akers, S. B., and B. Krishnamurthy. "Test counting: a tool for VLSI testing." IEEE Design & Test of Computers 6, no. 5 (1989): 58–77. http://dx.doi.org/10.1109/54.43080.

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25

Frisco, Roberta De, Angelo Monti, and Linda Pagli. "Testing and reconfiguration of VLSI linear arrays." Theoretical Computer Science 197, no. 1-2 (1998): 171–88. http://dx.doi.org/10.1016/s0304-3975(97)00238-7.

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26

Hurst, S. L. "VLSI testing and testability considerations: an overview." Microelectronics Journal 19, no. 4 (1988): 57–69. http://dx.doi.org/10.1016/s0026-2692(88)80045-4.

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27

Yoon-Hwa, Choi. "Testing of data paths in VLSI arrays." IEE Proceedings E Computers and Digital Techniques 137, no. 2 (1990): 154. http://dx.doi.org/10.1049/ip-e.1990.0018.

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28

Painke, Helmut. "Session G4: VLSI testing and modelling I." Microprocessing and Microprogramming 32, no. 1-5 (1991): 773. http://dx.doi.org/10.1016/0165-6074(91)90435-v.

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29

Choi, Yoon-Hwa. "Exploitation of parallelism in VLSI array testing." Computers & Electrical Engineering 15, no. 1 (1989): 33–41. http://dx.doi.org/10.1016/0045-7906(89)90006-2.

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30

Naidu Rayapati, Venkatapathi. "VLSI semiconductor random access memory functional testing." Microelectronics Reliability 30, no. 5 (1990): 877–89. http://dx.doi.org/10.1016/0026-2714(90)90556-3.

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31

Hnatek, Eugene R. "Factors involved in electrically testing vlsi circuits." Quality and Reliability Engineering International 2, no. 2 (1986): 81–100. http://dx.doi.org/10.1002/qre.4680020204.

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32

Gonsai, Sima K., Kinjal Ravi Sheth, Dhavalkumar N. Patel, et al. "Exploring the synergy: AI and ML in very large scale integration design and manufacturing." Bulletin of Electrical Engineering and Informatics 13, no. 6 (2024): 3993–4001. http://dx.doi.org/10.11591/eei.v13i6.8594.

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With the rapid advancements in very large scale integration (VLSI) and integrated circuit (IC) technology, the complexity of devices has escalated significantly. Designing a VLSI chip is essential for scaling up the capabilities of chips to meet the growing demands of modern applications, like artificial intelligence (AI), IoT, and high-performance computing. Chip testing and verification also emerges as crucial tasks to ensure optimal device functionality. Testing verifies the integrity of a circuit’s gates and connections, ensuring accurate operation. Throughout the chip’s design and develop

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33

Bulaev, I. Yu, A. Ya Koulibaba, and A. S. Silin. "DETECTION OF POTENTIALLY UNRELIABLE VLSI BASED ON THE ANALYSIS OF TEMPERATURE-SENSITIVE PARAMETERS." Kontrol'. Diagnostika, no. 278 (August 2021): 44–50. http://dx.doi.org/10.14489/td.2021.08.pp.044-050.

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The paper discusses methods for non-destructive diagnostic testing of very large scale integration circuits (VLSI) based on the “junction-case” thermal resistance parameter. This parameter is important because VLSI’s failure rate depends on junction temperature, which in turn depends on thermal resistance “junction-case”. There are three known methods for detecting potentially unreliable VLSIs with increased thermal resistance value: 1) non-destructive measurement of thermal resistance; 2) scanning acoustic microscopy; 3) an approach based on the statistical analysis of temperature-sensitive e

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34

Varaprasad, B. K. S. V. L., L. M. Patnaik, H. S. Jamadagni, and V. K. Agrawal. "An Efficient Test Pattern Generation Scheme for an On Chip BIST." VLSI Design 12, no. 4 (2001): 551–62. http://dx.doi.org/10.1155/2001/45324.

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Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (

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35

Mubarak, Ali Meerasha, S.Radhakrishnan, T.Nirmalraj, and S.Saravanan. "Code Multiplexed VLSI Test Architecture for SOC Testing." Spectrum International Journal of Multidisciplinary Research 1, no. 2 (2023): 9–13. https://doi.org/10.5281/zenodo.8382605.

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This work presents a code multiplexed test architecture for system-on-a-chip (SOC) testing utilizing simultaneous test data from test generators (TGs) transaction on common bus to the embedded core in the SOC. To improve the SOC testing performance without increasing the testing channel resources and complexity, this work presents an efficient test architecture that exploits parallelism in core-level testing, resulting in shorter testing time and higher concurrency on a shared test bus. The proposed code division multiple access (CDMA) enables multiple concurrent transactions on a shared bus.

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36

Mirabella, Nunzio, Maurizio Ricci, Ignazio Calà, Roberto Lanza, and Michelangelo Grosso. "Testing single via related defectsin digital VLSI designs." Microelectronics Reliability 120 (May 2021): 114100. http://dx.doi.org/10.1016/j.microrel.2021.114100.

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37

Shih-Chieh Chang and Jiann-Chyi Rau. "A timing-driven pseudoexhaustive testing for VLSI circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 1 (2001): 147–58. http://dx.doi.org/10.1109/43.905682.

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38

Basker, P. "Survey of Low Power Testing of VLSI Circuits." Science Journal of Circuits, Systems and Signal Processing 2, no. 2 (2013): 67. http://dx.doi.org/10.11648/j.cssp.20130202.15.

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39

Girard, P. "Survey of low-power testing of VLSI circuits." IEEE Design & Test of Computers 19, no. 3 (2002): 82–92. http://dx.doi.org/10.1109/mdt.2002.1003802.

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40

Nourani, Mehrdad, and Arun Radhakrishnan. "Testing On-Die Process Variation in Nanometer VLSI." IEEE Design and Test of Computers 23, no. 6 (2006): 438–51. http://dx.doi.org/10.1109/mdt.2006.157.

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41

Zhang, J. F. "VLSI Testing: Digital and Mixed Analogue/Digital Techniques." Measurement Science and Technology 10, no. 12 (1999): 1357. http://dx.doi.org/10.1088/0957-0233/10/12/502.

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42

Hosseinabady, Mohammad, Shervin Sharifi, Fabrizio Lombardi, and Zainalabedin Navabi. "A Selective Trigger Scan Architecture for VLSI Testing." IEEE Transactions on Computers 57, no. 3 (2008): 316–28. http://dx.doi.org/10.1109/tc.2007.70806.

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43

Seth, S. C., and V. D. Agrawal. "A Review of Testing of Digital VLSI Devices." IETE Technical Review 2, no. 11 (1985): 363–74. http://dx.doi.org/10.1080/02564602.1985.11437848.

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44

Hashempour, H., F. J. Meyer, and F. Lombardi. "Analysis and Evaluation of Multisite Testing for VLSI." IEEE Transactions on Instrumentation and Measurement 54, no. 5 (2005): 1770–78. http://dx.doi.org/10.1109/tim.2005.855099.

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45

Lala, P. K., and N. Berenjian. "Functional testing of LSI/VLSI chips—A survey." Journal of the Institution of Electronic and Radio Engineers 57, no. 6 (1987): 255. http://dx.doi.org/10.1049/jiere.1987.0093.

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46

Fazil, M. M., A. K. Sood, and R. P. Bajpai. "Strategies and Requisites of Testing LSI/VLSI Devices." IETE Technical Review 15, no. 1-2 (1998): 119–21. http://dx.doi.org/10.1080/02564602.1998.11416738.

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47

Williams, T. W., R. G. Walther, P. S. Bottorff, and S. Das Gupta. "Experiment to investigate self-testing techniques in VLSI." IEE Proceedings G (Electronic Circuits and Systems) 132, no. 3 (1985): 105. http://dx.doi.org/10.1049/ip-g-1.1985.0022.

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48

Lee, Y. H., and C. M. Krishna. "Optimal scheduling of signature analysis for VLSI testing." IEEE Transactions on Computers 40, no. 3 (1991): 336–41. http://dx.doi.org/10.1109/12.76412.

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49

Helmut Painke. "Session H4: VLSI testing and fault modelling II." Microprocessing and Microprogramming 32, no. 1-5 (1991): 851. http://dx.doi.org/10.1016/0165-6074(91)90448-3.

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50

Saradhi, M. Pardha, M. Tiny Serina, K. Sai Sravya, M. Pavithra, and P. Ankitha. "Enhanced Self-Test and Fault Localization in VLSI Circuit Using a 32-bit LFSR." International Scientific Journal of Engineering and Management 04, no. 04 (2025): 1–9. https://doi.org/10.55041/isjem02744.

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An Enhanced Self-Test and Fault Localization System (STFLS) improves fault detection accuracy in digital circuits. A 32-bit LFSR-based Pseudo-Random Pattern Generator generated test patterns, establishing a fault-free reference for precise comparison. Faults were identified by detecting deviations from the stored baseline outputs to ensure accurate localization. The system was implemented in Verilog HDL and simulated using Xilinx Vivado, thereby enhancing traditional self-test techniques. This approach is highly effective for VLSI testing, hardware verification, and fault analysis, and ensures

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