Relevant bibliographies by topics / Voltage multiplier circuit

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Voltage multiplier circuit'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Voltage multiplier circuit"

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SAKUL, CHAIWAT, and KOBCHAI DEJHAN. "FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS." Journal of Circuits, Systems and Computers 21, no. 03 (May 2012): 1250024. http://dx.doi.org/10.1142/s0218126612500247.

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This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.
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Reaungepattanawiwat, Chalermpol, and Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter." Applied Mechanics and Materials 781 (August 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.

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This paper presents a high voltage gain of a DC-DC converter. The proposed system consists of voltage multiplier circuits and a coupled inductor of a boost DC-DC converter. The input voltage of the voltage multiplier circuit is the induced voltage of inductor at a boost DC-DC converter. The field programmable gate array (FGPA) is used for generating the control signal of the proposed system. To verify the proposed circuit, an experiment was conducted from the prototype circuit. The proposed circuit can step-up the voltage with high voltage gain. Moreover, the voltage across the switch is very low.
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Suvarna, S., K. Rajesh, and T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic." International Journal of Students' Research in Technology & Management 4, no. 1 (March 10, 2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.

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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.
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Zhu, Binxin, Zihao Wei, Yao Chen, Han Wang, and D. Mahinda Vilathgamuwa. "Multiple Input-Terminal Voltage Multiplier Circuit." IEEE Transactions on Industry Applications 56, no. 5 (September 2020): 5075–82. http://dx.doi.org/10.1109/tia.2020.2998670.

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Semenov, V. K., and Yu A. Polyakov. "Circuit improvements for a voltage multiplier." IEEE Transactions on Appiled Superconductivity 11, no. 1 (March 2001): 550–53. http://dx.doi.org/10.1109/77.919404.

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Chen, Wei Ping, Tian Yang Wang, Hong Lei Xu, and Xiao Wei Liu. "A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair." Key Engineering Materials 483 (June 2011): 487–91. http://dx.doi.org/10.4028/www.scientific.net/kem.483.487.

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A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.
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Lin, Jin-Fa, Cheng-Yu Chan, and Shao-Wei Yu. "Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications." Electronics 8, no. 12 (November 30, 2019): 1429. http://dx.doi.org/10.3390/electronics8121429.

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In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.
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Ali, Esraa Mousa, Nor Zaihar Yahaya, Omar Aqeel Saraereh, Anwar Hamdan Al Assaf, Bilal Hasan Alqasem, Shahid Iqbal, Oladimeji Ibrahim, and Amit V. Patel. "Power Conversion Using Analytical Model of Cockcroft–Walton Voltage Multiplier Rectenna." Electronics 10, no. 8 (April 7, 2021): 881. http://dx.doi.org/10.3390/electronics10080881.

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A voltage multiplier rectenna is a combination of a voltage multiplier rectifier and an antenna used for the conversion of AC to DC. It is an essential part of the system of RF energy harvesting. Conventional rectennas are characterized by low conversion efficiency. This study presents an analytical novel mode designed for RF energy harvesting systems to study the voltage and current output of rectifier stages for efficiency optimization. The design contains a voltage multiplier rectification circuit with seven stages. The Schottky diode HSMS 285-C was selected for the circuit modeling voltage multiplier circuit. Advanced Design System (ADS) simulation was used to validate the equations of the theoretical model solved with MATLAB code. The fabricated system was tested for an input power range of 10 μW to 100 mW; the maximum output power is 0.2577 mW with maximum efficiency of 29.85%.
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Azmi, Nor A., Sohiful A. Z. Murad, Azizi Harun, and Rizalafande C. Ismail. "5V to 6kV DC-DC Converter Using Switching Regulator with Cockcroft-Walton Voltage Multiplier for High Voltage Power Supply Module." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 12, no. 2 (February 28, 2019): 162–71. http://dx.doi.org/10.2174/2352096511666180605094827.

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Background: This paper describes the design of 5 V to 6 kV DC-DC converter by using a switching regulator with Cockroft-Walton (C-W) voltage multiplier for a high voltage power supply module. Methods: The proposed design consists of Pulse Width Modulation (PWM) controller circuit, voltage multiplier, and feedback signal. A single unit of 5 V input triggers LT1618 controller circuit to generate 20 V which then produces 300 V from LT8331 output that is connected to diode-capacitor multiplier circuit to achieve final 6 kV. A negative feedback signal is required to stabilize an output voltage. With the implementation of C-W voltage multiplier technique, the output is boosted up as required from the input signal voltage 5 V DC. Results: The LTspice simulation results indicate that the proposed DC converter can generate 6.20 kV. Line regulation of 17 % and the load regulation of 14 % are obtained based on the proposed design. Conclusion: The proposed design is suitable for high voltage power supply module.
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Satansup, Jetsdaporn, and Worapong Tangsrirat. "1.5-V CMOS Current Multiplier/Divider." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 3 (June 1, 2018): 1478. http://dx.doi.org/10.11591/ijece.v8i3.pp1478-1487.

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A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.
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Dissertations / Theses on the topic "Voltage multiplier circuit"

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Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.

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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.
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Chaour, Issam, Ahmed Fakhfakh, and Olfa Kanoun. "Enhanced Passive RF-DC Converter Circuit Efficiency for Low RF Energy Harvesting." Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-224264.

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For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting energy at even a low input power from −40 dBm for a resistive load of 50 kΩ. It realizes a significant improvement in comparison with state of the art solutions
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Chvátlina, Pavel. "Laboratorní přípravek pro testování tranzistorů IGBT." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217920.

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This master’s thesis describes the function and realization of the laboratory test equipment designed for measuring and analysing of collector current iC and voltage uCE courses during the opening and closing process of a power IGBT transistor. The opening and closing times toff and ton of the new power transistor IGBT are changing in the range from tenths to the ones s, so the reading of current iC and voltage uCE proceeds in a very short time. The measuring circuit of this test equipment is based on a short-time discharging of a condenser battery to the inductive load over the measured transistor. Consequently it is possible to replace the power supply whose maximum output power would otherwise have to be in the range of ones MW. In the final part of this thesis there are described properties and design of a high-frequency sensor with the Rogowski coil, which can be used for reading collector current course during opening and closing time of the measured transistor IGBT. Collector current iC and voltage uCE courses can be analysed with a storage oscilloscope.
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Najafi, Syed Ahmed Ali. "Energy Harvesting From Overhead Transmission Line Magnetic Fields." University of Akron / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=akron1548448189459464.

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Dhillon, Yuvraj Singh. "Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6935.

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Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables. A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption. To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed.
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Llanos, Roger Vicente Caputo. "Voltage scaling interfaces for multi-voltage digital systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/159617.

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Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação.
Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
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Jahagirdar, Anant. "SOLAR DRIVEN PHOTOELECTROCHEMICAL WATER SPLITTING FOR HYDROGEN GENERATION USING MULTIPLE BANDGAP TANDEM OF CIGS2 PV CELLS AND TH." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3505.

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The main objective of this research was to develop efficient CuIn1-xGaxS2 (CIGS2)/CdS thin film solar cells for photoelectrochemical (PEC) water splitting to produce very pure hydrogen and oxygen. Efficiencies obtained using CIGS2 have been lower than those achieved using CuInSe2 and CuIn1-xGaxSe2. The basic limitation in the efficiencies is attributed to lower open circuit voltages with respect to the bandgap of the material. Presently, the main mechanism used to increase the open circuit voltage of these copper chalcopyrites (CuInSe2 and CuInS2) is the addition of gallium. However, addition of gallium has its own challenges. This research was intended to (i) elucidate the advantages and disadvantages of gallium addition, (ii) provide an alternative technique to the photovoltaic (PV) community to increase the open circuit voltage which is independent of gallium additions, (iii) develop highly efficient CIGS2/CdS thin film solar cells and (iv) provide an alternative material in the form of CIGS2/CdS thin film solar cells and an advanced technology in the form of a multiple bandgap tandem for PEC water splitting. High gallium content was achieved by the incorporation of a highly excess copper composition. Attempts to achieve high gallium content produced reasonable but not the best solar cell performance. Few solar cells developed on a molybdenum back contact and an ITO/MoS2 transparent conducting back contact showed a PV conversion efficiency of 7.93% and 5.97%, respectively. The solar cells developed on the ITO/MoS2 back contact form the first generation CIGS2/CdS thin film solar cells and 5.97% is the first ever reported efficiency on an ITO/MoS2 transparent back contact. Reasons for the moderate performance of these solar cells were attributed to significant porosity and remnants of unsulfurized CuGa alloy in the bulk of CIGS2. This was the first attempt to a detailed study of materials and device characteristics of CIGS2/CdS thin film solar cells prepared starting with a highly excess copper content CIGS2 layer. Next, excess copper composition of 1.4 (equivalent to gallium content, x = 0.3) was chosen with the aim to achieve the best efficiency. The open circuit voltage was enhanced by depositing an intermediate layer of intrinsic ZnO between CdS and ZnO:Al layers. The systematic study of requirements for such a layer and further optimization of its thickness to achieve a higher open circuit voltage (which is the greatest challenge of the scientific community) forms an important scientific contribution of this research. The PV parameters for CIGS2/CdS thin film solar cell as measured officially at the National Renewable Energy Laboratory were: open circuit voltage of 830.5 mV, short circuit current density of 21.88 mA/cm2, fill factor of 69.13% and photovoltaic conversion efficiency of 11.99% which sets a new world record for CIGS2 cells developed using sulfurization and the open circuit voltage of 830.5 mV has become the "Voc champion value". New PEC setups with the RuS2 and Ru0.99Fe0.01S2 photoanodes were developed. RuS2 and Ru0.99Fe0.01S2 photoanodes were more stable in the electrolyte and showed better I-V characteristics than the RuO2 anode earlier used. Using two CIGS2/CdS thin film solar cells, a PEC efficiency of 8.78% was achieved with a RuS2 anode and a platinum cathode. Results of this research constitute a significant advance towards achieving practical feasibility and industrially viability of the technology of PEC hydrogen generation by water splitting.
Ph.D.
Department of Mechanical, Materials and Aerospace Engineering;
Engineering and Computer Science
Materials Science and Engineering
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Velaga, Srikirti. "Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368026670.

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Terres, Marco Antonio de Souza Madeira. "Arquiteturas de conversores de tensão para circuitos com múltiplas tensões de alimentação ajustadas de forma dinâmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/141259.

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Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%.
Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.
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Luo, Feng. "Integrated Switching DC-DC Converters with Hybrid Control Schemes." Diss., The University of Arizona, 2009. http://hdl.handle.net/10150/193904.

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In the modern world of technology, highly sophisticated electronic systems pave the way for future's information technology breakthroughs. However, rapid growth on complexity and functions in such systems has also been a harbinger for the power increase. Power management techniques have thus been introduced to mitigate this urgent power crisis. Switching power converters are considered to be the best candidate due to their high efficiency and voltage conversion flexibility. Moreover, switching power converter systems are highly nonlinear, discontinuous in time, and variable. This makes it viable over a wide operating range, under various load and line disturbances. However, only one control scheme cannot optimize the whole system in different scenarios. Hybrid control schemes are thus employed in the power converters to operate jointly and seamlessly for performance optimization during start-up, steady state and dynamic voltage/load transient state.In this dissertation, three switching power converter topologies, along with different hybrid control schemes are studied. First, an integrated switching buck converter with a dual-mode control scheme is proposed. A pulse-train (PT) control, employing a combination of four pulse control patterns, is proposed to achieve optimal regulation performance. Meanwhile, a high-frequency pulse-width modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling. Second, an integrated buck-boost converter with a tri-mode digital control is presented. It employs adaptive step-up/down voltage conversion to enable a wide range of output voltage. This is beneficial to ever-increasing dynamic voltage scaling (DVS) enabled, modern power-efficient VLSI systems. DVS adaptively adjusts the supply voltage and operation frequency according to instantaneous power and performance demand, such that a system is constantly operated at the lowest possible power level without compromising its performance. Third, a digital integrated single-inductor multiple-output (SIMO) converter, tailored for DVS-enabled multicore systems is addressed. With a multi-mode control algorithm, DVS tracking speed and line/load regulation are significantly improved, while the converter still retains low cross regulation.All three integrated CMOS DC-DC converters have been designed and fabricated successfully, demonstrating the techniques proposed in this research. The measurements results illustrate superior line and load regulation performances and dynamic response in all these designs.
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Books on the topic "Voltage multiplier circuit"

1

Kursun, Volkan. Multiple-voltage CMOS circuit design. Chichester, UK: John Wiley, 2006.

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Kursun, Volkan. Multiple supply and threshold voltage CMOS circuits. Chichester, England: John Wiley, 2006.

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1945-, Brodersen Robert W., ed. Low-power CMOS wireless communications: A wideband CDMA system design. Boston: Kluwer Academic Publishers, 1998.

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Wright, A. G. Voltage dividers. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780199565092.003.0013.

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Voltage dividers provide accelerating voltages to generate multiplier gain. Dynode voltages must remain constant and independent of the light input to maintain stable gain. The standard resistive divider never quite satisfies this requirement, although acceptable performance can be achieved by careful design. The inclusion of zener diodes improves performance but field-effect transistor (FET) circuits can provide gain stability at high mean anode currents, regardless of whether the application is pulsed or analogue. Design procedures for active and semi-active voltage dividers are presented. Dividers based on the Cockcroft–Walton (CW) principle are particularly suited to portable instrumentation because of their low standing current. Consideration is given to pulsed operation, decoupling, switch-on transients, ripple, dynode signals, single cable dividers, and equivalent circuits at high frequencies. Gating is used to protect a photomultiplier, in the presence of high light levels, by reducing the gain electronically. Various methods for gating a voltage divider are presented.
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Akashe, Shyam, and Khusbou Mishra. Low Power High Speed CMOS Multiplexer Design. Nova Science Publishers, Incorporated, 2015.

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Wright, A. G. The Photomultiplier Handbook. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780199565092.001.0001.

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This handbook is aimed at helping users of PMTs who are faced with the challenge of designing sensitive light detectors for scientific and industrial purposes. The raison d’être for photomultipliers (PMTs) stems from four intrinsic attributes: large detection area, high, and noiseless gain, and wide bandwidth. Detection involves a conversion process from photons to photoelectrons at the photocathode. Photoelectrons are subsequently collected and increased in number by the action of an incorporated electron multiplier. Photon detection, charge multiplication, and many PMT applications are statistical in nature. For this reason appropriate statistical treatments are provided and derived from first principles. PMTs are characterized by a range of photocathodes offering detection over UV to infra-red wavelengths, the sensitivities of which can be calibrated by National Laboratories. The optical interface between light sources and PMTs, particularly for diffuse or uncollimated light, is sparsely covered in the scientific literature. The theory of light guides, Winston cones, and other light concentrators points to means for optimizing light collection subject to the constraints of Liouville’s theorem (étandue). Certain PMTs can detect single photons but are restricted by the limitations of unwanted background ranging in magnitude from a fraction of a photoelectron equivalent to hundreds of photoelectrons. These sources, together with their correlated nature, are examined in detail. Photomultiplier biasing requires a voltage divider comprising a series of resistors or active components, such as FETs. Correct biasing provides the key to linear operation and so considerable attention is given to the treatment of this topic. Electronic circuits and modules that perform the functions of charge to voltage conversion, pulse shaping, and impedance matching are analysed in detail.
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Brodersen, Robert W., and Samuel Sheng. Low-Power CMOS Wireless Communications A Wideband CDMA System Design. Springer, 1997.

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Book chapters on the topic "Voltage multiplier circuit"

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Rajawat, Asmita, and P. K. Singhal. "Design of Energy Efficient Voltage Multiplier Circuit for RF Energy Harvesting." In Lecture Notes in Electrical Engineering, 583–92. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4286-7_58.

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Rajawat, Asmita, Karush Suri, and Mohit Mohta. "Design of an Efficient Rectifier Circuit Based on Karthaus-Fischer Voltage Multiplier for Energy Harvesting." In Advances in Intelligent Systems and Computing, 913–22. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_96.

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Islam, Mahfuzul, and Hidetoshi Onodera. "Monitor Circuits for Cross-Layer Resiliency." In Dependable Embedded Systems, 385–407. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_16.

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AbstractCross-layer resiliency has become a critical deciding factor for any successful product. This chapter focuses on monitor circuits that are essential in realizing the cross-layer resiliency. The role of monitor circuits is to establish a bridge between the hardware and other layers by providing information about the devices and the operating environment in run-time. This chapter explores delay-based monitor circuits for design automation with the existing cell-based design methodology. The chapter discusses several design techniques to monitor parameters of threshold voltage, temperature, leakage current, critical delay, and aging. The chapter then demonstrates a reconfigurable architecture to monitor multiple parameters with small area footprint. Finally, an extraction methodology of physical parameters is discussed for model-hardware correlation. Utilizing the cell-based design flow, delay-based monitors can be placed inside the target digital circuit and thus a better correlation between monitor and target circuit behavior can be realized.
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Popa, Cosmin Radu. "Voltage and Current Multiplier Circuits." In Synthesis of Computational Structures for Analog Signal Processing, 89–184. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0403-3_2.

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Haugen, Greg, Sara Barta, Mike Emery, Steven Hamrock, and Mike Yandrasits. "Open Circuit Voltage Fuel Cell Durability Testing Using Multiple PEM MEAs." In ACS Symposium Series, 137–51. Washington, DC: American Chemical Society, 2010. http://dx.doi.org/10.1021/bk-2010-1040.ch010.

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Kim, Seokjoong, and Matthew R. Guthaus. "SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture." In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 181–95. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0_10.

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Taybi, Abdellah, Abdelali Tajmouati, Jamal Zbitou, and Mohamed Latrach. "Study and Design of New Rectenna Structures for Wireless Power Transmission Applications." In Advances in Computer and Electrical Engineering, 123–55. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-0117-7.ch004.

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This chapter presents many research works that have been carried out to deal with the problem of power supply to remote sensors. A 2.45 GHz voltage multiplier rectifier was validated to deliver 18V of output voltage with a conversion efficiency of 69%. Another rectenna was fabricated at 5.8 GHz of the Industrial Scientific Medical band and reach a measured voltage of 7.4V at 18 dBm. The third structure is about a series rectifier working at 2.45 GHz associated with a microstrip low pass filter which produces a supplying voltage of 11.23V. Added to the aforementioned results, the objective in this work is to design, optimize and realize two structures: A dual band patch antenna working at 2.45 GHz and 5.8 GHz, and a compact rectifier circuit at 2.45 GHz for the power supply of low-consumption devices. This rectifier has been designed using Advanced Design System. The bridge topology was employed on an FR4 substrate. A good matching input impedance was observed and high conversion efficiency was obtained. Simulation results have been validated through realization and measurements.
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Brindley, Keith. "Voltage multiplier circuits." In Newnes Radio and Electronics Engineer's Pocket Book, 260. Elsevier, 1989. http://dx.doi.org/10.1016/b978-0-434-90187-6.50109-3.

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Brindley, Keith. "Voltage multiplier circuits." In Newnes Radio and Electronics Engineer's Pocket Book, 167–68. Elsevier, 1987. http://dx.doi.org/10.1016/b978-0-434-90183-8.50101-0.

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"Signal Transfer in ICs with Multiple Supply Voltages." In Multi-Voltage CMOS Circuit Design, 139–46. Chichester, UK: John Wiley & Sons, Ltd, 2006. http://dx.doi.org/10.1002/0470033371.ch8.

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Conference papers on the topic "Voltage multiplier circuit"

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Zhu, Binxin, Yao Chen, Han Wang, and Mahinda Vilathgamuwa. "Multiple Input-Terminal Voltage Multiplier Circuit." In 2019 4th International Conference on Intelligent Green Building and Smart Grid (IGBSG). IEEE, 2019. http://dx.doi.org/10.1109/igbsg.2019.8886172.

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Emmanuel, Bergeret, Jean Gaubert, Philippe Pannier, and Jean-marie Gaultier. "Conception of UHF voltage multiplier for RFID circuit." In The 4th International IEEE-NEWCAS Conference. IEEE, 2006. http://dx.doi.org/10.1109/newcas.2006.250961.

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Feldengut, Tobias, Rainer Kokozinski, and Stephan Kolnsberg. "A UHF voltage multiplier circuit using a threshold-voltage cancellation technique." In 2009 Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2009. http://dx.doi.org/10.1109/rme.2009.5201303.

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Ettaghzouti, Thouraya, Nejib Hassen, and Kamel Besbes. "High performance low voltage low power voltage mode analog multiplier circuit." In 2017 International Conference on Information and Digital Technologies (IDT). IEEE, 2017. http://dx.doi.org/10.1109/dt.2017.8012160.

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Ettaghzouti, Thouraya, Nejib Hassen, and Kamel Besbes. "High performance low voltage low power voltage mode analog multiplier circuit." In 2016 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT). IEEE, 2016. http://dx.doi.org/10.1109/setit.2016.7939926.

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Amiri, Abolfazl, and Ali Naderi Saatlo. "Voltage mode implementation of highly accurate analog multiplier circuit." In 2015 23rd Iranian Conference on Electrical Engineering (ICEE). IEEE, 2015. http://dx.doi.org/10.1109/iraniancee.2015.7146368.

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Sakul, Chaiwat. "A low voltage supply four-quadrant analog multiplier circuit." In 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication (2009 ASID). IEEE, 2009. http://dx.doi.org/10.1109/icasid.2009.5276907.

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Sakul, Chaiwat, and Kajornsak Pongthana. "A low voltage supply four-quadrant analog multiplier circuit." In 2009 International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS 2009). IEEE, 2009. http://dx.doi.org/10.1109/ispacs.2009.5383843.

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Sreeram, K. "An Improvised Voltage Multiplier Circuit for Industrial Applications and Grids." In 2018 International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET). IEEE, 2018. http://dx.doi.org/10.1109/iccsdet.2018.8821154.

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Kumar, Vikash, and Aminul Islam. "CNFET Based Voltage Multiplier Circuit for RF Energy Harvesting Applications." In 2015 Fifth International Conference on Communication Systems and Network Technologies (CSNT). IEEE, 2015. http://dx.doi.org/10.1109/csnt.2015.59.

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