Dissertations / Theses on the topic 'Voltage multiplier circuit'

With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.

For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting energy at even a low input power from −40 dBm for a resistive load of 50 kΩ. It realizes a significant improvement in comparison with state of the art solutions

This master’s thesis describes the function and realization of the laboratory test equipment designed for measuring and analysing of collector current iC and voltage uCE courses during the opening and closing process of a power IGBT transistor. The opening and closing times toff and ton of the new power transistor IGBT are changing in the range from tenths to the ones s, so the reading of current iC and voltage uCE proceeds in a very short time. The measuring circuit of this test equipment is based on a short-time discharging of a condenser battery to the inductive load over the measured transistor. Consequently it is possible to replace the power supply whose maximum output power would otherwise have to be in the range of ones MW. In the final part of this thesis there are described properties and design of a high-frequency sensor with the Rogowski coil, which can be used for reading collector current course during opening and closing time of the measured transistor IGBT. Collector current iC and voltage uCE courses can be analysed with a storage oscilloscope.

Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables. A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption. To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed.

Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação.
Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.

The main objective of this research was to develop efficient CuIn1-xGaxS2 (CIGS2)/CdS thin film solar cells for photoelectrochemical (PEC) water splitting to produce very pure hydrogen and oxygen. Efficiencies obtained using CIGS2 have been lower than those achieved using CuInSe2 and CuIn1-xGaxSe2. The basic limitation in the efficiencies is attributed to lower open circuit voltages with respect to the bandgap of the material. Presently, the main mechanism used to increase the open circuit voltage of these copper chalcopyrites (CuInSe2 and CuInS2) is the addition of gallium. However, addition of gallium has its own challenges. This research was intended to (i) elucidate the advantages and disadvantages of gallium addition, (ii) provide an alternative technique to the photovoltaic (PV) community to increase the open circuit voltage which is independent of gallium additions, (iii) develop highly efficient CIGS2/CdS thin film solar cells and (iv) provide an alternative material in the form of CIGS2/CdS thin film solar cells and an advanced technology in the form of a multiple bandgap tandem for PEC water splitting. High gallium content was achieved by the incorporation of a highly excess copper composition. Attempts to achieve high gallium content produced reasonable but not the best solar cell performance. Few solar cells developed on a molybdenum back contact and an ITO/MoS2 transparent conducting back contact showed a PV conversion efficiency of 7.93% and 5.97%, respectively. The solar cells developed on the ITO/MoS2 back contact form the first generation CIGS2/CdS thin film solar cells and 5.97% is the first ever reported efficiency on an ITO/MoS2 transparent back contact. Reasons for the moderate performance of these solar cells were attributed to significant porosity and remnants of unsulfurized CuGa alloy in the bulk of CIGS2. This was the first attempt to a detailed study of materials and device characteristics of CIGS2/CdS thin film solar cells prepared starting with a highly excess copper content CIGS2 layer. Next, excess copper composition of 1.4 (equivalent to gallium content, x = 0.3) was chosen with the aim to achieve the best efficiency. The open circuit voltage was enhanced by depositing an intermediate layer of intrinsic ZnO between CdS and ZnO:Al layers. The systematic study of requirements for such a layer and further optimization of its thickness to achieve a higher open circuit voltage (which is the greatest challenge of the scientific community) forms an important scientific contribution of this research. The PV parameters for CIGS2/CdS thin film solar cell as measured officially at the National Renewable Energy Laboratory were: open circuit voltage of 830.5 mV, short circuit current density of 21.88 mA/cm2, fill factor of 69.13% and photovoltaic conversion efficiency of 11.99% which sets a new world record for CIGS2 cells developed using sulfurization and the open circuit voltage of 830.5 mV has become the "Voc champion value". New PEC setups with the RuS2 and Ru0.99Fe0.01S2 photoanodes were developed. RuS2 and Ru0.99Fe0.01S2 photoanodes were more stable in the electrolyte and showed better I-V characteristics than the RuO2 anode earlier used. Using two CIGS2/CdS thin film solar cells, a PEC efficiency of 8.78% was achieved with a RuS2 anode and a platinum cathode. Results of this research constitute a significant advance towards achieving practical feasibility and industrially viability of the technology of PEC hydrogen generation by water splitting.
Ph.D.
Department of Mechanical, Materials and Aerospace Engineering;
Engineering and Computer Science
Materials Science and Engineering

Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%.
Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.

In the modern world of technology, highly sophisticated electronic systems pave the way for future's information technology breakthroughs. However, rapid growth on complexity and functions in such systems has also been a harbinger for the power increase. Power management techniques have thus been introduced to mitigate this urgent power crisis. Switching power converters are considered to be the best candidate due to their high efficiency and voltage conversion flexibility. Moreover, switching power converter systems are highly nonlinear, discontinuous in time, and variable. This makes it viable over a wide operating range, under various load and line disturbances. However, only one control scheme cannot optimize the whole system in different scenarios. Hybrid control schemes are thus employed in the power converters to operate jointly and seamlessly for performance optimization during start-up, steady state and dynamic voltage/load transient state.In this dissertation, three switching power converter topologies, along with different hybrid control schemes are studied. First, an integrated switching buck converter with a dual-mode control scheme is proposed. A pulse-train (PT) control, employing a combination of four pulse control patterns, is proposed to achieve optimal regulation performance. Meanwhile, a high-frequency pulse-width modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling. Second, an integrated buck-boost converter with a tri-mode digital control is presented. It employs adaptive step-up/down voltage conversion to enable a wide range of output voltage. This is beneficial to ever-increasing dynamic voltage scaling (DVS) enabled, modern power-efficient VLSI systems. DVS adaptively adjusts the supply voltage and operation frequency according to instantaneous power and performance demand, such that a system is constantly operated at the lowest possible power level without compromising its performance. Third, a digital integrated single-inductor multiple-output (SIMO) converter, tailored for DVS-enabled multicore systems is addressed. With a multi-mode control algorithm, DVS tracking speed and line/load regulation are significantly improved, while the converter still retains low cross regulation.All three integrated CMOS DC-DC converters have been designed and fabricated successfully, demonstrating the techniques proposed in this research. The measurements results illustrate superior line and load regulation performances and dynamic response in all these designs.

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.

L'efficacité énergétique est devenue une métrique clé de la performance des systèmes sur puce numériques, en particulier pour les applications tirant leur énergie de batteries ou de l'environnement. La miniaturisation technologique n'est plus suffisante pour atteindre les niveaux de consommation requis. Ce travail de recherche propose ainsi de nouvelles conceptions de circuits pour la génération d'horloge flexible, la mesure de puissance et de température ainsi que l'intégration de ces blocs au sein de systèmes sur puce complets.Le multiplieur de fréquence innovant en boucle ouverte proposé permet l'adaptation rapide de la fréquence générée (53MHz 0.5V - 889MHz 0.9 V). Sa surface réduite (981µm2) et faible consommation (0.45pJ/cycle à 0.5 V) facilitent son intégration dans des systèmes à basse consommation. Le capteur de puissance instrumente un convertisseur de tension switched-capacitor; validé sur deux architectures différentes, il permet une mesure de la puissance d'entrée et de sortie avec une précision de 2.5% à 6%. Enfin, un nouveau principe de capteur de température est proposé. Il exploite une méthode de calibration par body-biasing sur caisson n et un système numérique intégré pour la compensation de non-linéarité. Enfin, cette thèse illustre la manière dont ces circuits peuvent être intégrés pour assurer la gestion de consommation de systèmes complexes. Un travail de modélisation du body-biasing est proposé, illustrant sa complémentarité avec la gestion de tension d'alimentation. Puis trois exemples de stratégies de gestion de la consommation sont proposées au sein de systèmes complets
Energy efficiency has become a key metric for digital SoC, especially for applications relying on batteries or energy harvesting. Hence, this work proposes new designs for on-chip flexible clock generator, power monitor and temperature sensor as well as the integration of those blocks within complete SoC.The novel open-loop clock multiplier architecture enables fast frequency scaling and is implemented to operate on the same voltage-frequency range as a digital core ((53MHz 0.5V - 889MHz 0.9 V). The achieved extremely low area (981µm2) and power consumption 0.45pJ/cycle 0.5 V) also ease its integration within low power SoC. The proposed power monitor instruments switched capacitor DC-DC converters, which are standard components of low voltage SoCs. The monitor has been demonstrated over two different converters topologies and provides a measurement of both the converter input and output power within 2.5% to 6% accuracy. Last, a new principle of temperature sensor is proposed. It leverages single n well body-biasing for calibration and integrated digital logic for large non-linearity correction. It is expected to achieve within 1C accuracy 0.1nJ / sample and 225 µm2 probe area. Then, this work illustrates how those circuits can be integrated within complex SoCs power management strategies. First, a modeling study of body biasing highlights the benefits it can provide in complement to voltage scaling, accounting for a wide temperature range. Last, three example of power management are proposed at SoC level

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
This thesis aims to present the design and development of an Energy Harvesting (EH) circuit applied to wireless sensor networks (WSN), especially those that perform functions in lighting systems, such as monitoring or control. The primary function of an Energy Harvesting system is to convert, condition and manage energy from an available source in the environment, in order to power low power consumption devices, which usually would be fed by batteries. The most used energy sources in EH systems are solar, wind, electromagnetic waves, mechanical vibration and thermal differences. Thus Energy Harvesting is an alternative to increase the autonomy or even eliminate the use of batteries for portable, implanted or remote located devices. Initially, an analysis of the most appropriate energy sources to power wireless sensors networks is performed, taking into aspects such as energy density, advantages and disadvantages. Subsequently, the proposed EH circuit is developed and tested. One of the specific objectives is that the EH proposed circuit is capable to being adapted for different energy sources. The proposed circuit consists of two stages, the first is a pre-amplifier and rectifier based on Villard multiplier. The second stage consists of a low-power boost converter with a synthesized inductor. The circuit is able to operate with minimum input voltages about 0.3 V, reaching maximum output of 5 V and 100mW of power.
A presente dissertação tem por objetivo apresentar a concepção e o desenvolvimento de um circuito Energy Harvesting (EH) aplicado a redes de sensores sem fio, notadamente aquelas que desempenham funções relacionadas a sistemas de iluminação, como por exemplo, monitoramento ou controle. A função primordial de um sistema EH é obter, converter, condicionar e gerenciar energia proveniente de uma fonte disponível no meio ambiente, de modo que esta alimente dispositivos de baixo consumo que usualmente seriam alimentados através de pilhas ou baterias. As fontes de energia mais empregadas para sistemas EH são solar, eólica, ondas eletromagnéticas, diferenças térmicas e vibrações mecânicas. Desse modo, Energy Harvesting é uma alternativa para o aumento da autonomia ou mesmo da eliminação do uso de baterias para dispositivos portáteis, implantados, ou dispositvos que se encontram locais remotos. Inicialmente, uma análise das fontes de energia mais propícias para a alimentação de uma rede de sensores sem fio é realizada, tendo em vista aspectos como densidade de energia, vantagens e desvantagens. Posteriormente, a topologia de circuito EH proposta é desenvolvida e testada. Um dos objetivos específicos é que o circuito EH proposto possa ser adaptado para diferentes fontes de energia. O circuito proposto é composto por dois estágios, o primeiro, é um pré-amplificador e retificador, baseado no multiplicador de Villard. O segundo estágio é composto por um conversor Boost de baixa potência, cuja indutância é sintetizada por meio de um circuito do tipo Gyrator. O circuito é capaz de operar com tensões de entrada mínima de 0,3 V, atingindo saída máxima de 5 V e 100 mW de potência.

Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode.
Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.

碩士
國立臺灣大學
機械工程學研究所
101
A ion fan is consisted of a pair of electrodes between which generated ions with applied high voltages can drive the air flow. Most study use pin-to-plate or pin-to-ring as its electrodes to generate ion wind, which the pin is at high potential. However, it has been studied that if one put a ring near the high potential pin can increase the velocity of ion wind. This study investigate the high potential electrode’s shape by using multi-pin circle arrangement instead of single pin in the middle. Additionally, a high voltage power supply (HVPS) is necessary of the ion fan, this study use voltage multiplier circuit as the HVPS which consist of 50 electrolytic capacitors and diodes. The experiment showing that using different capacitance of electrolytic capacitors can decrease the voltage drop which appears in using single capacitance of electrolytic capacitors. Finally, the multi-pin circle arrangement using 3 pins has a velocity of 1.21 m/s which is larger than 0.85 m/s when using 6 pins and is slightly smaller than single pin in the middle which is 1.23 m/s while the supplying voltage was in 10.5kV.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails.
Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

碩士
中原大學
電子工程研究所
102
ABSTRACT As the complexity of integrated circuit design and the demand of portable products continue to increase, the reduction of power consumption has become an important design challenge. In the modern integrated circuit design, the use of multiple voltages is recognized an effective approaqch to reduce power consumption without sacrificing circuit speed. However, the synthesis of multi-voltage three-dimensional integrated circuit designs has not been well studied. In this thesis, we study the layer assignment problem for multi-voltage three-dimensional integrated circuit designs. We present an integer linear programming approach to minimize the footprint area. Different from previous layer assignment approach, we not only consider the area of cells but also consider the area of power networks. Experimental results consistently show that our approach can save both power consumption and footprint area.

Mak Wing-sum.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.
Includes bibliographical references (leaf [68]).
Abstracts in English and Chinese.
List of Figures --- p.I
List of Tables --- p.III
ACKNOWLEDGMENTS
ABSTRACT
Chapter Chapter I --- Introduction
Chapter 1.1 --- Introduction - Low Power --- p.I-1
Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1
Chapter 1.2.1 --- Static Power Dissipation --- p.I-2
Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5
Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8
Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10
Chapter 1.4 --- Objective of the Project --- p.I-10
Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic
Chapter 2.1 --- Low Power Design --- p.II-12
Chapter 2.2 --- Adiabatic Switching --- p.II-12
Chapter 2.3 --- Adiabatic Logic --- p.II-14
Chapter 2.4 --- History of Adiabatic Logic --- p.II-17
Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter
Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18
Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20
Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22
Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23
Chapter Chapter IV --- Power Clock Generator
Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24
Chapter 4.2 --- Power Clock Generator
Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV
Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27
Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier
Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32
Chapter 5.2 --- Structure of Multiplier --- p.V-34
Chapter Chapter VI --- Simulations
Chapter 6.1 --- AqsCMOS Inverter
Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38
Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39
Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI
Chapter 6.2 --- Power Clock Generator --- p.VI -42
Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45
Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46
Chapter ChapterVII --- evaluations
Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51
Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus
Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54
Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55
Chapter 7.2.3 --- Input Current Measurement --- p.VII -58
Chapter 7.3 --- Power Measurement --- p.VII -63
Chapter Chapter VIII --- Conclusions and Fiirthfr Developments
Chapter 8.1 --- Conclusions --- p.VIII -65
Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65
Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65
Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66
Chapter 8.2 --- Further Development --- p.VIII -66
Appendix I micro-photography of aqscmos multiplier
Appendix II micro-Photography of CMOS multiplier
Appendix III micro-photography of AqsCMOS inverter chain testing modules
Appendix IV power - meter simulation approach
Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers
Reference

碩士
中華大學
資訊工程學系碩士班
94
As semiconductor process keeps migrating, total power consumption of digital circuits will significantly impact the future development of the chip design. Therefore, the most important issue in modern chip designs is how to reduce the power consumption. One of the methods to achieve the low-power goal is to reduce the supply voltage, which has been confirmed to be the most effective way to achieve low-power optimization. However, most of the methods are requested to pre-assign the number of voltages in the early physical design. The proposed methods don’t really support the optimization analysis for given circuits, and the final result will not obtain low-power optimization for given circuits. In this thesis, an efficent approach is proposed to analyze a circuit netlist which came from the result in logic synthesis. Based on the characteristic of the connection structure in a circuit netlist, and the distribution of the slack, the optimized number of voltages can be defined dynamically to achieve low-power optimization. In addition, the delay and power penalty in the level converters can be further considered, and there’s no need to violate the primary system productivity for the low-power goal. By puting these optimized voltages into the consideration of power supply design, a quadratic programming approach is used to minimize total power consumption based on all the voltage constraints. In the experiement, 9 MCNC benchmarks are used to test the performance of the proposed approach. The experimental results show that the power consumption of the whole circuit improves 30% to 40%, compared to single power supply environment. For dual-voltage supply enviroment, there will be 30% improvement on total power consumption. Therefore, the best effectivity of low-power optimization can be achieved via the method we propose here.

Indiana University-Purdue University Indianapolis (IUPUI)
A novel method of power management and sequential monitoring of several sensors is proposed in this work. Application specific integrated circuits (ASICs) consisting of analog and digital sub-systems forming a system on chip (SoC) has been designed using complementary metal-oxide-semiconductor (CMOS) technology. The analog sub-system comprises the sensor-drivers that convert the input voltage variations to output pulse-frequency. The digital sub-system includes the system management unit (SMU), counter, and shift register modules. This performs the power-usagemanagement, sensor-sequence-control, and output-data-frame-generation functions. The SMU is the key unit within the digital sub-system is that enables or disables a sensor. It captures the pulse waves from a sensor for 3 clocks out of a 16-clock cycle, and transmits the signal to the counter modules. As a result, the analog sub-system is at on-state for only 3/16th fraction (18 %) of the time, leading to reduced power consumption. Three cycles is an optimal number selected for the presented design as the system is unstable with less than 3 cycles and higher clock cycles results in increased power consumption. However, the system can achieve both higher sensitivity and better stability with increased on-state clock cycles. A current-starved-ring-oscillator generates pulse waves that depend on the sensor input parameter. By counting the number of pulses of a sensor-driver in one clock cycle, a sensor input parameter is converted to digital. The digital sub-system constructs a 16-bit frame consisting of 8-bit sensor data, start and stop bits, and a parity bit. Ring oscillators that drive capacitance and resistance-based sensors use an arrangement of delay elements with two levels of control voltages. A bias unit which provides these two levels of control voltages consists of CMOS cascade current mirror to maximize voltage swing for control voltage level swings which give the oscillator wider tuning range and lower temperature induced variations. The ring oscillator was simulated separately for 250 nm and 180 nm CMOS technologies. The simulation results show that when the input voltage of the oscillator is changed by 1 V, the output frequency changes linearly by 440 MHz for 180 nm technology and 206 MHz for 250 nm technology. In a separate design, a temperature sensitive ring oscillator with symmetrical load and temperature dependent input voltage was implemented. When the temperature in the simulation model was varied from -50C to 100C the oscillator output frequency reduced by 510 MHz for the 250 nm and by 810 MHz for 180 nm CMOS technologies, respectively. The presented system does not include memory unit, thus, the captured sensor data has to be instantaneously transmitted to a remote station, e.g. end user interface. This may result in a loss of sensor data in an event of loss of communication link with the remote station. In addition, the presented design does not include transmitter and receiver modules, and thus necessitates the use of separate modules for the transfer of the data.

碩士
國立臺灣科技大學
電機工程系
106
A power-efficient boost converter for a thermoelectric energy harvesting system (EHS) is proposed in this thesis. To improve overall system power efficiency, a multiple output architecture is adopted. To provide suitable cut-off voltage to power transistors in different conditions of output voltage levels, a novel high-voltage-selector based on a winner-take-all circuit is proposed. Besides, power transistor dimensions are optimized to balance the conduction and the switching losses for minimizing the loss of the power stage. Floatinggate technologies are employed in voltage comparators and voltage detectors to avoid the power consumption of a conventional bandgap reference circuit and to provide reconfigurability for output voltage levels. Floating-gate transistors are also employed in a novel cold-start-up circuit to reduce the threshold voltage of transistors in a charge pump circuit so that the start-up voltage can be as low as 380 mV. The cold-start-up circuit exploits the same inductor as the main boost converter without extra external component. To maximize the energy harvesting efficiency, the boost converter adopts an adaptive on-time and peak current control scheme and a fractional open-circuit voltage approach to achieve maximum power point tracking. To reduce the tracking time, a binary and incremental search algorithm is exploited with small input voltage ripples. A prototyped chip is designed and fabricated in a 0:35um CMOS process. The measurement results show that the cold-start-up circuit can start-up the system when input voltage equals to 380 mV and the start-up time is about 1:4 seconds. Furthermore, the simulation result shows the peak efficiency is 95:85% when the input power equals to 988 W.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.
Graduation date: 2013
Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014

Οι εφαρμογές της σύγχρονης τεχνολογίας επιτάσσουν τη χρήση συσκευών με όσο το δυνατόν μικρότερες διαστάσεις, χαμηλή τάση τροφοδοσίας, χαμηλή κατανάλωση ισχύος και ταυτόχρονα υψηλές επιδόσεις. Το αντικείμενο της εργασίας αυτής, αφορά στη σχεδίαση αναλογικών ολοκληρωμένων φίλτρων, χαμηλής τάσης τροφοδοσίας, για υλοποίηση μεγάλων σταθερών χρόνου, στο πεδίο του λογαρίθμου. Προς αυτή την κατεύθυνση, μελετώντας και σχεδιάζοντας δομές αναλογικών φίλτρων στο πεδίο του λογαρίθμου, επιτεύχθηκε η σχεδίαση φίλτρων δεύτερης τάξης με μεγάλες σταθερές χρόνου, διατηρώντας τις φυσικές διαστάσεις των κυκλωμάτων σε εξαιρετικά χαμηλά επίπεδα. Αρχικά, παρουσιάζονται κάποια εισαγωγικά στοιχεία για την σχεδίαση ολοκληρωμένων κυκλωμάτων σε περιβάλλον χαμηλής τάσης τροφοδοσίας. Γίνεται εισαγωγή στην ιδέα των λογαριθμικών φίλτρων και αναλύονται οι βασικές αρχές σχεδίασης. Παρουσιάζονται βασικά χαρακτηριστικά των κυκλωμάτων στο πεδίο του λογαρίθμου, καθώς και ανάλυση των τελεστών και των διαγωγών που αποτελούν τη βάση της σχεδίασης στο λογαριθμικό πεδίο. Επιπλέον, παρουσιάζονται οι υλοποιήσεις των ολοκληρωτών των φίλτρων στο πεδίο του λογαρίθμου. Στη συνέχεια, γίνεται τοπολογική εξομοίωση 2ης τάξης βαθυπερατών φίλτρων στο πεδίο του λογαρίθμου. Σχεδιάζονται φίλτρα με την κλασική μέθοδο υλοποίησης, κάνοντας χρήση ισοδύναμων των παθητικών στοιχείων στο λογαριθμικό πεδίο, αλλά και φίλτρα υλοποιημένα με διάγραμμα ροής (SFG). Παρουσιάζονται τα πρώτα αποτελέσματα των εξομοιώσεων που πραγματοποιήθηκαν με το λογισμικό Cadence και το γραφικό περιβάλλον που διαθέτει για την σχεδίαση αναλογικών ηλεκτρονικών κυκλωμάτων (Virtuoso Analog Environment). Προτείνονται, δύο κυκλώματα τα οποία πραγματοποιούν πολλαπλασιασμό της χωρητικότητας των πυκνωτών, επιτυγχάνοντας έτσι μεγάλες σταθερές χρόνου, και η υλοποίηση νέων ολοκληρωτών που κάνουν χρήση των πολλαπλασιαστών. Δημιουργούνται έτσι οι βάσεις για την υλοποίηση φίλτρων με εξαιρετικά μικρές διαστάσεις, των οποίων η σχεδίαση, η εξομοίωση και η φυσική σχεδίαση (layout design) παρουσιάζονται, αναλύονται και συγκρίνονται.
The technological evolution and market requirements have led to an increasing demand of low - power portable devices, featuring the reduced size of the devises and high efficiency. This M.Sc project deals with the design of analog integrated, Log - Domain filters, for low - voltage implementation, with large time - constants. In this direction, the design of a second order, low - pass filter, with the above features, and with the occupied silicon area maintained at very low levels, was achieved. In Chapters 1 and 2, an introduction to the design of integrated circuits in low voltage environment is presented. There is an introduction to the idea and the basic principles of Log - Domain filters. The key characteristics of circuits in a large signal operation point of view, and an analysis of the operators and the exponential transconductor cells are, also presented. Furthermore, the basic Log - Domain integrators has been analyzed. A topologic analysis of second order Log - Domain filters is given in Chapter 3. Filters has been initially designed firstly with the classic implementation, using Log - Domain equivalent of passive elements. In a second step, the filter has been realizes by employing the signal flow diagram (SFG) representation. These filters were simulated with the Analog Design environment of the Cadence software. the obtained simulation results confirmed the correct operation of the circuit. Two implementations for realizing the Log - Domain equivalent of a capacitor multiplier are introduced. In addition, implementations of new Log - Domain integrators, that use the capacitor multipliers, are given in Chapter 4. Using these implementations, Log - Domain filters, with reduced total area and large time - constants, are designed, simulated and characterized in Chapter 5. Finally, the layout design of a second - order has been performed in Chapter 6 and the provided post - layout simulation results show that the performance of the filter was close to that of the filter realized in schematic level.