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Gasper, Michael Rober. "Nonlinear Microwave Interactions with Voltage-Gated Graphene Devices." University of Akron / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1596648207273845.
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Chaour, Issam. "Efficiency Improvement of RF Energy Transfer by a Modified Voltage Multiplier RF DC Converter." Universitätsverlag Chemnitz, 2018. https://monarch.qucosa.de/id/qucosa%3A33143.
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Radio Frequency (RF) energy transfer is getting increasingly importance in new generations of wireless sensor networks and this trend is tremendously supported by the modern trends to Internet of things (IoT). This promising technology enables proactive energy replenishment for wireless devices. With RF energy, transmission long distances between the energy source and the receiver can be overbridged. The main challenge thereby is the power conversion efficiency from a low level RF input power to a Direct Current (DC) voltage which is able to supply the mobile system.
For this purpose, a novel approach for RF DC conversion is proposed. It consists of a modified voltage multiplier RF DC converter circuit by incorporating an inductor at the input of the circuit, which generates an induced voltage able to boost the output circuit and improve the conversion efficiency. Analytical analysis of the novel approach has been carried out to determine the optimal value of the inductor to maximize the output power. The experimental investigations show that the proposed solution is able to improve significantly both the output voltage and the power conversion efficiency, compared to the state of the art, and this especially at low input power ranges, which are often the case. At -10 dBm input power, the modified voltage multiplier RF DC converter circuit can reach 1.71 V output voltage and 49.21 % power conversion efficiency for, respectively, 500 kΩ and 10 kΩ resistive loads.
In order to validate the new proposal for the RF transfer system experimentally, microstrip meander line antennas and microstrip patch antenna arrays are designed for different ISM bands, where relevant requirements for RF energy transfer are respected. For each antenna a modified voltage multiplier RF DC converter circuit has been applied and the system is tuned to the corresponding resonant frequency to avoid mismatching. In this investigation several scenarios have been addressed, such as RF transmission energy, RF energy harvesting in Global System for Mobile (GSM) bands and Wireless Local Area Networks (WLAN) band are developed. Field test results show high performances of experimental results in comparison to the state of the art.:1 Introduction
2 Theoretical Background
3 State of the Art of RF Energy Transfer
4 Novel Approach for a RF DC Converter Circuit
5 Antennas Design
6 Experimental Verification at Specific Scenarios
7 ConclusionDie RF-Energieübertragung (RF) gewinnt in neuen Generationen von drahtlosen Sensornetzen zunehmend an Bedeutung. Dieser Trend wird durch das Internet der Dinge (IoT) weiter unterstützt. Diese vielversprechende Technologie ermöglicht eine proaktive Energieversorgung für drahtlose Geräte. Mit RF-Energie können große Entfernungen zwischen der Energiequelle und dem Empfänger überbrückt werden. Die größte Herausforderung dabei ist der Wirkungsgrad, mit dem von einer niedrigen HF-Eingangsleistung in eine Gleichspannung (DC), mit welcher das mobile System versorgt wird, gewandelt wird. Zu diesem Zweck wird ein neuer Ansatz für einen RF-DC-Wandler vorgeschlagen. Er besteht aus einer modifizierten Spannungsvervielfacher-RF-DC-Wandlerschaltung, die eine Spule am Eingang der Schaltung integriert. Diese erzeugt eine induzierte Spannung, die in der Lage ist die Ausgangsschaltung zu verstärken und den Umwandlungswirkungsgrad zu verbessern. Analytische Untersuchungen zu diesem neuartigen Ansatz wurden durchgeführt, um den optimalen Wert der Spule zu bestimmen und die Ausgangsleistung zu maximieren. Die experimentellen Untersuchungen zeigen, dass die vorgeschlagene Lösung in der Lage ist, sowohl die Ausgangsspannung als auch den Wirkungsgrad der Leistungsumwandlung im Vergleich zum Stand der Technik deutlich zu verbessern. Dies gilt besonders für niedrige Eingangsleistungsbereiche, welche häufig vorkommen. Bei -10 dBm Eingangsleistung kann die modifizierte Spannungsvervielfacher-RF-DC-Wandlerschaltung 1.71 V Ausgangsspannung und 49.21 % Leistungswandlungswirkungsgrad für jeweils 500 kΩ und 10 kΩ ohmsche Last erreichen. Um das neue RF-Übertragungssystem experimentell zu validieren, werden Mikrostreifenmäanderlinienantennen und Mikrostreifen-Patch-Antennenarrays für verschiedene ISM-Bänder ausgelegt, wobei die relevanten Anforderungen an die RF-Energieübertragung eingehalten werden. Für jede Antenne wurde eine modifizierte Spannungsvervielfacher-HF-DC-Wandlerschaltung verwendet und das System auf die entsprechende Resonanzfrequenz abgestimmt, um Fehlanpassungen zu vermeiden. Dabei wurden mehrere Szenarien untersucht, wie z.B. RF-Energieübertragung, RF-Energiegewinnung aus GSM-Bändern und WLAN-Netzwerken. Die Feldtests zeigen eine hohe Leistungsfähigkeit der experimentellen Ergebnisse im Vergleich zum Stand der Technik.:1 Introduction 2 Theoretical Background 3 State of the Art of RF Energy Transfer 4 Novel Approach for a RF DC Converter Circuit 5 Antennas Design 6 Experimental Verification at Specific Scenarios 7 Conclusion
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Kopeček, Pavel. "Analýza, vlastnosti a aplikace komerčně dostupných napěťových násobiček." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219161.
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This work deals with the analog multipliers, mainly of the voltage multipliers. Also the modifications of current output will appear here. The first part is devoted to a choice several multipliers and a description of their functions, the possible involvement and introduction of the most important catalog values. The next section deals with the simple application that contains at least one of the multipliers. Next was the implementation of selected applications and measure their actual performance parameters. Results are then compared with computer simulations. As final step is done of tolerance and sensitivity analysis of simulated configurations of circuits.
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Chaour, Issam [Verfasser], Olfa [Akademischer Betreuer] Kanoun, Olfa [Gutachter] Kanoun, Madhukar [Gutachter] Chandra, and Ahmed [Gutachter] Fakhfakh. "Efficiency Improvement of RF Energy Transfer by a Modified Voltage Multiplier RF DC Converter / Issam Chaour ; Gutachter: Olfa Kanoun, Madhukar Chandra, Ahmed Fakhfakh ; Betreuer: Olfa Kanoun." Chemnitz : Universitätsverlag Chemnitz, 2021. http://d-nb.info/1230059156/34.
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Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.
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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment.
Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques.
These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented
in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic
architecture.
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Baev, Dmitriy. "Diagnostika vysokonapěťových kondenzátorů pro kaskádní napěťový násobič." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318998.
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The main subject of the final thesis is to find a suitable method for measuring the partial discharge (PD) in the dielectric of high-voltage capacitor. In the theoretical part of my thesis contains from the mechanisms of origin and the harmful effects of partial discharge at high voltage insulation of capacitor. It describes the global galvanic method of partial discharge measurement, the principle of cascade voltage multiplier, its main components are high-voltage capacitor and diode, facilities quality measurement of capacitors for voltage multipliers, advantages and disadvantages and principles of HIPOTRONICS DDX-8003 with the pulse discrimination system. In the experimental part of the diploma thesis is familiar with the diagnostics of high – voltage capacitors by means of laboratory measurements on the electronic bridge and with the help of partial discharge measurement system. Design of suitable electrode arrangement is described which eliminates the influence of corona which makes it impossible to measure partial discharges and the dissipation factor (tg ). Analysis data from measurement and determination of quality level, eventual degradation of measured capacitors. The result of this project should be designed the methodology for finding of poor – quality capacitors in order to increase the reliability of the voltage multiplier.
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Alcazar, Yblin Janeth Acosta. "Estudo do Conversor Bosst CC-CC de Alto Ganho de TensÃo Baseado na CÃlula de ComutaÃÃo de TrÃs Estados e nas CÃlulas Multiplicadoras de TensÃo (mc)." Universidade Federal do CearÃ, 2010. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=10585.
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nÃo hÃO presente trabalho propÃe o estudo do conversor boost CC-CC de alto ganho de tensÃo baseado na cÃlula de comutaÃÃo de trÃs estados e nas cÃlulas multiplicadoras de tensÃo (mc). Este trabalho investiga um modelo matemÃtico para o citado conversor. A anÃlise proposta à baseada na ferramenta âmodelagem do interruptor PWM para conversores CC-CCâ. O modelo deve ser encontrado por uma simples inspeÃÃo do circuito do conversor. Deve ser possÃvel aplicÃ-lo para realizar diversas anÃlises, como em regime permanente, regime transitÃria e anÃlise de pequenos sinais por meio de um uma abordagem unificada. Considerando um dado nÃmero de cÃlulas multiplicadoras de tensÃo, duas situaÃÃes sÃo analisadas com esta ferramenta: operaÃÃo com uma Ãnica cÃlula multiplicadora de tensÃo (mc=1) e vÃrias cÃlulas multiplicadoras de tensÃo (mc> 1). O mÃtodo proposto à validado por simulaÃÃes e à verificada sua efetividade. AlÃm disso, à analisado neste trabalho o controle modo corrente mÃdia convencional, o qual à aplicado em uma das configuraÃÃes em estudo. O rendimento do conversor e a efetividade do controlador proposto sÃo demonstrados por resultados experimentais para um protÃtipo do laboratÃrio de 1 kW.
The present work proposes the study of the boost converter based on three-state switching cell and voltage multipliers cells (mc). A mathematical model of the aforementioned converter is investigated here. The proposed analysis is based on the tool named âPWM-Switch Modeling of DC-DC Convertersâ. The model must be found by a simple inspection of the converterâs circuit. It is possible to apply such model in order to realize various analyses such as steady-state, transient, and small-signal analysis in a single and same model. Considering the number of voltage multipliers cells (mc), two situations are analyzed: operation with a single multiplier cell (mc=1) and operation with multiple voltage multiplier cells (mc>1).The proposed method was validated through simulations and its effectiveness was verified. In addition to this, conventional average current mode control is also applied to one of the studied configurations. The performance of the converter and the effectiveness of the proposed controller are demonstrated by experimental results obtained from a 1-kW laboratory prototype.
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Chvátlina, Pavel. "Laboratorní přípravek pro testování tranzistorů IGBT." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217920.
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This master’s thesis describes the function and realization of the laboratory test equipment designed for measuring and analysing of collector current iC and voltage uCE courses during the opening and closing process of a power IGBT transistor. The opening and closing times toff and ton of the new power transistor IGBT are changing in the range from tenths to the ones s, so the reading of current iC and voltage uCE proceeds in a very short time. The measuring circuit of this test equipment is based on a short-time discharging of a condenser battery to the inductive load over the measured transistor. Consequently it is possible to replace the power supply whose maximum output power would otherwise have to be in the range of ones MW. In the final part of this thesis there are described properties and design of a high-frequency sensor with the Rogowski coil, which can be used for reading collector current course during opening and closing time of the measured transistor IGBT. Collector current iC and voltage uCE courses can be analysed with a storage oscilloscope.
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SINGH, VINIT. "HIGH TEMPERATURE CAPACITORS FOR VOLTAGE MULTIPLIERS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085685724.
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Najafi, Syed Ahmed Ali. "Energy Harvesting From Overhead Transmission Line Magnetic Fields." University of Akron / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=akron1548448189459464.
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Chaour, Issam, Ahmed Fakhfakh, and Olfa Kanoun. "Enhanced Passive RF-DC Converter Circuit Efficiency for Low RF Energy Harvesting." Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-224264.
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For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting energy at even a low input power from −40 dBm for a resistive load of 50 kΩ. It realizes a significant improvement in comparison with state of the art solutions
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CASTRO, MARCEL RENE VASCONCELOS DE. "MODELING OF VOLTAGE CONTROL AND MULTIPLE SWING BUSES IN VOLTAGE STABILITY ASSESSMENT." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2007. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=11320@1.
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CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICOO crescente aumento da complexidade dos sistemas elétricos de potência gera a necessidade de desenvolvimento de ferramentas que melhorem as condições de análise. O objetivo deste trabalho é aprimorar a ferramenta computacional de avaliação das condições de segurança (ou estabilidade) de tensão. No que diz respeito às barras associadas ao controle remoto de tensão por geração de potência reativa, são propostos novos modelos que representam mais adequadamente as condições operativas no momento do cálculo dos índices de segurança de tensão. Em relação à barra associada ao controle local de tensão por geração de potência reativa é proposta nova modelagem, aplicável tanto no problema de fluxo de potência, utilizando o método de Newton- Raphson, quanto no cálculo dos índices de segurança de tensão. Este modelo,mais robusto e flexível, inclui o controle de tensão local da barra no problema geral de fluxo de potência, formando um sistema de equações de ordem (2*número de barras+número de barras controladas localmente). Para o tratamento de múltiplas barras swing, é proposto um novo modelo, de novo para representar mais adequadamente as condições operativas. É aplicável tanto no problema básico de fluxo de potência, como no cálculo dos índices de segurança de tensão. O modelo proposto considera que apenas o ângulo de uma barra swing é especificado, com os ângulos das demais barras swing livres para variar. Testes numéricos com sistemas-teste (5 e 6 barras) comprovam a aplicabilidade e adequação dos modelos propostos comparando-os aos modelos usados atualmente.
The crescent increase of the complexity of the electric power systems generates the need of development of tools to improve the analysis conditions. The objective of this work is to improve the computational tool of voltage security (stability) conditions assessment. As regards to the buses associated to remote voltage control by reactive power generation, new models that represent more appropriately the operatives conditions at the moment of the calculations of the voltage security indexes, are proposed. As regards to the bus associated to local voltage control by reactive power generation, it is proposed a new modeling, applicable as much in the power flow problem, using the Newton-Raphson method, as in the calculation of the voltage security indexes. This model, more robust and flexible, includes the local voltage control of the bus in the general power flow problem, constituting an equations system of order (2*number of system buses + number of buses with local voltage control). As regard to the multiples swing buses, it is proposed a new model, again to represents more appropriately the operatives conditions. It is applicable as much in the basic power flow problem, as in the calculation of the voltage security indexes. The proposed model considers that just one swing bus has your voltage angle specified and the others swing buses of the power system have your voltage angles free to vary.
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Llanos, Roger Vicente Caputo. "Voltage scaling interfaces for multi-voltage digital systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/159617.
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Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação.Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
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Tong, Yajian. "Multiple-input multiple-output converters for future low-voltage DC power distribution architectures." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/52780.
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Multiple-input multiple-output (MIMO) converters have been identified as a cost-effective approach for energy harvesting and dispatching in hybrid power systems such as those envisioned in future smart homes and DC microgrids. Compared with relatively complex set-up of single-input single-output (SISO) converters linked at a common DC bus to exchange power, the MIMO converters possess promising features of fewer components, higher power density, and centralized control. This thesis addresses various issues regarding the development of MIMO converters. Both non-isolated and isolated MIMO converter topologies are proposed. Steady-state analysis and dynamic modeling of MIMO non-inverting buck–boost and flyback converters are introduced and presented in detail. Specific switching strategies are proposed and appropriate control algorithms are presented to enable power budgeting between diverse sources and loads in addition to regulating output voltages. Furthermore, a simple method is put forward for deriving the non-isolated MIMO converters with DC-link inductor (DLI) and DC-link capacitor (DLC). Based on a basic structure, a set of rules is listed for the synthesis of MIMO converters. Using the time-sharing concept, multiple sources provide energy in one period, and multiple loads draw energy in the subsequent period. In the end, general techniques are introduced for extending the SISO converters to their MIMO versions, where parts of the conventional SISO converters are replaced with multiport structures. It is envisioned that MIMO converters presented in this thesis will find their acceptance in the future in various applications with DC distribution, which are becoming increasingly accepted by industry.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Depexe, Márcio Dalcul. "Concepção de um circuito energy harvesting aplicado a redes de sensores sem fio para sistemas de iluminação." Universidade Federal de Santa Maria, 2014. http://repositorio.ufsm.br/handle/1/8556.
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Coordenação de Aperfeiçoamento de Pessoal de Nível SuperiorThis thesis aims to present the design and development of an Energy Harvesting (EH) circuit applied to wireless sensor networks (WSN), especially those that perform functions in lighting systems, such as monitoring or control. The primary function of an Energy Harvesting system is to convert, condition and manage energy from an available source in the environment, in order to power low power consumption devices, which usually would be fed by batteries. The most used energy sources in EH systems are solar, wind, electromagnetic waves, mechanical vibration and thermal differences. Thus Energy Harvesting is an alternative to increase the autonomy or even eliminate the use of batteries for portable, implanted or remote located devices. Initially, an analysis of the most appropriate energy sources to power wireless sensors networks is performed, taking into aspects such as energy density, advantages and disadvantages. Subsequently, the proposed EH circuit is developed and tested. One of the specific objectives is that the EH proposed circuit is capable to being adapted for different energy sources. The proposed circuit consists of two stages, the first is a pre-amplifier and rectifier based on Villard multiplier. The second stage consists of a low-power boost converter with a synthesized inductor. The circuit is able to operate with minimum input voltages about 0.3 V, reaching maximum output of 5 V and 100mW of power.
A presente dissertação tem por objetivo apresentar a concepção e o desenvolvimento de um circuito Energy Harvesting (EH) aplicado a redes de sensores sem fio, notadamente aquelas que desempenham funções relacionadas a sistemas de iluminação, como por exemplo, monitoramento ou controle. A função primordial de um sistema EH é obter, converter, condicionar e gerenciar energia proveniente de uma fonte disponível no meio ambiente, de modo que esta alimente dispositivos de baixo consumo que usualmente seriam alimentados através de pilhas ou baterias. As fontes de energia mais empregadas para sistemas EH são solar, eólica, ondas eletromagnéticas, diferenças térmicas e vibrações mecânicas. Desse modo, Energy Harvesting é uma alternativa para o aumento da autonomia ou mesmo da eliminação do uso de baterias para dispositivos portáteis, implantados, ou dispositvos que se encontram locais remotos. Inicialmente, uma análise das fontes de energia mais propícias para a alimentação de uma rede de sensores sem fio é realizada, tendo em vista aspectos como densidade de energia, vantagens e desvantagens. Posteriormente, a topologia de circuito EH proposta é desenvolvida e testada. Um dos objetivos específicos é que o circuito EH proposto possa ser adaptado para diferentes fontes de energia. O circuito proposto é composto por dois estágios, o primeiro, é um pré-amplificador e retificador, baseado no multiplicador de Villard. O segundo estágio é composto por um conversor Boost de baixa potência, cuja indutância é sintetizada por meio de um circuito do tipo Gyrator. O circuito é capaz de operar com tensões de entrada mínima de 0,3 V, atingindo saída máxima de 5 V e 100 mW de potência.
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Holloway, Jack Wade 1980. "Harmonic control of multiple-stator induction machines for voltage regulation." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28691.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 133-135).
Small, one to a few horsepower, three-phase induction machines with three sets of electrically-isolated, magnetically-coupled stator winding circuits are described. A voltage inverter is developed and used to drive one set of the machine stator winding circuits. The second set of machine stator winding circuits is connected to a three-phase rectifier in which a path for zero-sequence current is provided from the winding circuits to the rectifier. The last set of stator winding circuits is connected to another three-phase rectifier, however, the stator circuit star point is floating, not providing a zero-sequence current path. By controlling the phase of the third harmonic on the machine drive stator circuits, and thus the waveforms present on the secondary and tertiary stator winding circuits, the output voltage of the rectifier with a zero-sequence current path can be tune above or below the rectifier output without third harmonic injection. The rectifier connected without a zero-sequence current path does not display this tunability with respect to third harmonic phase.
by Jack Wade Holloway.
M.Eng.
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Butcher, Nicholas David. "Active Paralleling of High Power Voltage Source Inverters." Thesis, University of Canterbury. Electrical and Computer, 2007. http://hdl.handle.net/10092/3430.
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Power electronics are becoming established in ever broadening areas of industry. The transition from previous generation technology is driven by the oportunity for improvements in controllability, efficiency, and longevity. A wide variety of power semiconductors are available, however power handling capacity is still a significant limitation for many applications. An increase in the capacity of a single device is usually accompanied by a drop in switching frequency, and hence achievable system bandwidth. Increased capacity can be attained without this loss in bandwidth by using multiple lower power devices in parallel. Products based on parallel device topologies are already present in the marketplace, however there are many associated complications. The nature of these complications depends on the control method and topology used, but no system combines high performance and high power with high reliability and easy maintainability. This research aims to identify and develop a method that would provide a system of voltage source inverters with a total capacity in excess of 10MVA, with effective control bandwidth comparable to a 100kVA system. Additionally, the method should be equally applicable at still higher power levels in the future with the anticipated development of higher capacity power semiconductors. The primary goal when using paralleled devices is to achieve an even distribution of system load between them, as unbalanced load leads to poor system utilisation. Devices can be paralleled either passively, in which devices are controlled in common and characteristics inherent to the device are relied upon to balance load; or actively, in which devices are individually controlled and monitored to improve load balance. A key component of the thesis is the identification and analysis of the inadequacies inherent to passively paralleled systems. It is the limitations of passive paralleling that provide the motivation to develop an active parallel control mechanism. Following the analysis, an active control algorithm is developed and implemented on a paralleled system. The proposed system topology consists of an array of medium power Voltage Source Inverter (VSI) modules operating in parallel. Each module is controlled semi-independently at a local level, with an inter-module communications network to enable active equalisation of module load, and redundant fault management. An innovative load equalisatiion algorithm is developed and proven, the key feature of which is this inclusion of a synthetic differential resistance between modules within the system. The result is a modular expandable structure offering the potential for very high power capacity combined with quality of response usually only found in low power systems. The system as a whole is extremely reliable as any module can be isolated in the event of a fault without significantly affecting the remainder of the network. Performance results from both simulation and experimentation on a two module small scale prototype are given. Using the developed topology and control method extremely accurate load balancing can be achieved without degradation of the response characteristics. The system is tested up to only 2.4kW in the course of this research, but the correlation with simulation is high and gives confidence that the developed mechanism will allow the 10MV A goal to be achieved. Following the developmental stage of this research the technology has been applied to a commercial system comprising parallel structures of up to 8 modules with a total power handling capacity of 1MVA with no deterioration in performance. 2MVA systems are deliverable with the current technology without any changes, and higher power levels are expected to be easily achieved.
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Song, Yang. "Design of secondary voltage and stability controls with multiple control objectives." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29714.
Full textAbstract:
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Begovic, Miroslav; Committee Member: Deng, Shijie; Committee Member: Divan, Deepakraj; Committee Member: Harley, Ronald; Committee Member: Lambert, Frank; Committee Member: Shamma, Jeff. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Alshaikh, Mohammed Saleh Abdullah. "Design of variation-tolerant synchronizers for multiple clock and voltage domains." Thesis, University of Newcastle upon Tyne, 2014. http://hdl.handle.net/10443/2482.
Full textAbstract:
Parametric variability increasingly affects the performance of electronic circuits as the fabrication technology has reached the level of 32nm and beyond. These parameters may include transistor Process parameters (such as threshold voltage), supply Voltage and Temperature (PVT), all of which could have a significant impact on the speed and power consumption of the circuit, particularly if the variations exceed the design margins. As systems are designed with more asynchronous protocols, there is a need for highly robust synchronizers and arbiters. These components are often used as interfaces between communication links of different timing domains as well as sampling devices for asynchronous inputs coming from external components. These applications have created a need for new robust designs of synchronizers and arbiters that can tolerate process, voltage and temperature variations. The aim of this study was to investigate how synchronizers and arbiters should be designed to tolerate parametric variations. All investigations focused mainly on circuit-level and transistor level designs and were modeled and simulated in the UMC90nm CMOS technology process. Analog simulations were used to measure timing parameters and power consumption along with a “Monte Carlo” statistical analysis to account for process variations. Two main components of synchronizers and arbiters were primarily investigated: flip-flop and mutual-exclusion element (MUTEX). Both components can violate the input timing conditions, setup and hold window times, which could cause metastability inside their bistable elements and possibly end in failures. The mean-time between failures is an important reliability feature of any synchronizer delay through the synchronizer. The MUTEX study focused on the classical circuit, in addition to a number of tolerance, based on increasing internal gain by adding current sources, reducing the capacitive loading, boosting the transconductance of the latch, compensating the existing Miller capacitance, and adding asymmetry to maneuver the metastable point. The results showed that some circuits had little or almost no improvements, while five techniques showed significant improvements by reducing τ and maintaining high tolerance. Three design approaches are proposed to provide variation-tolerant synchronizers. wagging synchronizer proposed to First, the is significantly increase reliability over that of the conventional two flip-flop synchronizer. The robustness of the wagging technique can be enhanced by using robust τ latches or adding one more cycle of synchronization. The second approach is the Metastability Auto-Detection and Correction (MADAC) latch which relies on swiftly detecting a metastable event and correcting it by enforcing the previously stored logic value. This technique significantly reduces the resolution time down from uncertain synchronization technique is proposed to transfer signals between Multiple- Voltage Multiple-Clock Domains (MVD/MCD) that do not require conventional level-shifters between the domains or multiple power supplies within each domain. This interface circuit uses a synchronous set and feedback reset protocol which provides level-shifting and synchronization of all signals between the domains, from a wide range of voltage-supplies and clock frequencies. Overall, synchronizer circuits can tolerate variations to a greater extent by employing the wagging technique or using a MADAC latch, while MUTEX tolerance can suffice with small circuit modifications. Communication between MVD/MCD can be achieved by an asynchronous handshake without a need for adding level-shifters.
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Chen, Qing. "Analysis and design of multiple-output forward converter with weighted voltage control /." This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10032007-171757/.
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Chen, Jing. "Analysis and design of multiple-output forward converter with weighted voltage control." Diss., Virginia Tech, 1994. http://hdl.handle.net/10919/39565.
Full textAbstract:
This work presents the modeling and analyses of multiple-output forward converters with weighted voltage control. Based upon the analyses, the systematic design methodologies and design tools are provided.
A power stage de model including all the major parasitics, which are detrimental to the output voltages, is detived. A nonlinear programming based design tool is developed to search for the weighting factors. Five methods of stacking secondaries to improve cross-regulation are presented, and the improvement of cross-regulation is quantified.
A small-signal model of the multiple-output converters with coupled output filter inductors and weighted voltage control is established. The small-signal characteristics are studied, and the model shows that the system behavior is very sensitive to the coupling coefficient, which has been reported, but never been quantified. The pole-zero interlaced condition is derived. A current-mode control small-signal model is also presented, which can predict all the observed phenomena of current-mode control. Compensator design is
discussed for different types of power stage transfer functions for both voltage-mode and
current-mode control.Ph. D.
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Nik, Ali Nik Hakimi Bin. "Classification and localisation of multiple partial discharge sources within high voltage transformer windings." Thesis, University of Southampton, 2017. https://eprints.soton.ac.uk/415793/.
Full textAbstract:
Partial discharge (PD) analysis is a common method for condition monitoring and diagnostics of power transformers, which can be used as a tool for assessing the lifespan of transformers and can detect insulation malfunctions before they lead to failure. This report describes the development of analytical tools for PD activities within HV transformer windings. In most cases, PD will occur in transformer windings due to ageing processes, operational over stressing or defects introduced during manufacture, and different PD sources have different effects on the condition and performance of power equipment insulation system. Therefore, for further analyses, the ability to accurately distinguish between the PD signals generated from different sources is seen as a critical function for future diagnostic systems. Under realistic field conditions, multiple PD sources may be activated simultaneously within the transformer winding. An experiment has been designed to assess different methodologies for the identification and localisation of multiple PD sources within a HV transformer winding. Previous work at Southampton developed a non-linear based technique that facilitates identification of the location of a single PD source within an interleaved winding. It is assumed that any discharge occurring at any point along a winding will produce an electrical signal that will propagate as a travelling wave towards both ends of the winding. This project is concerned with the feasibility of locating several sources simultaneously based only on measurement data from wideband radio frequency current transformers (RFCTs) placed at the neutral to earth point and the bushing tap-point to earth. The proposed processing technique relies on the assumption that the PD pulses generated from different sources exhibit unique waveform characteristics. Due to termination and path taken characteristics, the PD signals will suffer attenuation and distortion during the propagation of the PD signals along transformer windings. Therefore, it will cause changes in the energy characteristics of the PD pulses at both measurement points, which can be used to separate, identify and locate the multiple PDs within an HV transformer winding. Based on analysis of the captured data from experiment, various approaches for identifying multiple PD sources have been assessed. Obtained results indicate that the analysis of absolute energy distributions determined using Mathematical Morphology and the use of OPTICS for clustering will reliably separate PD data from two sources that are simultaneously active within a distributed winding.
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Velaga, Srikirti. "Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368026670.
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Yamane, Shinichi. "A New Design Methodology for Extending Symmetrical Input Ranges in Four-Quadrant Low Voltage CMOS Multipliers." The Ohio State University, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=osu1421163501.
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Bade, Rajesh Kumar. "Analysis of incipient fault signatures in inductive loads energized by a common voltage bus." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3095.
Full textAbstract:
Recent research has demonstrated the use of electrical signature analysis (ESA),
that is, the use of induction motor currents and voltages, for early detection of motor
faults in the form of embedded algorithms. In the event of multiple motors energized
by a common voltage bus, the cost of installing and maintaining fault monitoring and
detection devices on each motor may be avoided, by using bus level aggregate electrical
measurements to assess the health of the entire population of motors. In this research
an approach for detecting commonly encountered induction motor mechanical faults
from bus level aggregate electrical measurements is investigated.
A mechanical fault indicator is computed processing the raw electrical measurements
through a series of signal processing algorithms. Inference of an incipient fault
is made by the percentage relative change of the fault indicator from the ÂhealthyÂ
baseline, thus defining a Fault Indicator Change (FIC).
To investigate the posed research problem, healthy and faulty motors with broken
rotor bar faults are simulated using a detailed transient motor model. The FIC
based on aggregate electrical measurements is studied through simulations of different
motor banks containing the same faulty motor. The degradation in the FIC when
using aggregate measurements, as compared to using individual motor measurements,
is investigated. For a given motor bank configuration, the variation in FIC with
increasing number of faulty motors is also studied. In addition to simulation studies
experimental results from a two-motor setup are analyzed. The FIC and degradation
in the FIC in the case of load eccentricity fault, and a combination of shaft looseness
and bearing damage is studied through staged fault experiments in the laboratory
setup.
In this research, the viability of using bus level aggregate electrical measurements
for detecting incipient faults in motors energized by a common voltage bus is
demonstrated. The proposed approach is limited in that as the power rating fraction
of faulty motors to healthy motors in a given configuration decreases, it becomes far
more difficult to detect the presence of incipient faults at very early stages.
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Leung, Lap-Fai. "Reducing energy consumption of single and multiple processors core systems using dynamic voltage scheduling /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LEUNGL.
Full textAbstract:
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.
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Dhillon, Yuvraj Singh. "Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6935.
Full textAbstract:
Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables.
A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption.
To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed.
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Macfie, Peter. "Large-scale security constrained optimal reactive power flow for operational loss management on the GB electricity transmission network." Thesis, Brunel University, 2010. http://bura.brunel.ac.uk/handle/2438/5073.
Full textAbstract:
The transmission of power across the GB transmission system, as operated by National Grid, results in inevitable loss of electrical power. Operationally these power losses cannot be eliminated, but they can be reduced by adjustment of the system voltage profile. At present the minimisation of active power losses relies upon a lengthy manually based iterative adjustment process. Therefore the system operator requires the development of advanced optimisation tools to cope with the challenges faced over the next decade, such as achieving the stringent greenhouse gas emission targets laid down by the UK government, while continue to provide an economical, secure and efficient service. To meet these challenges the research presented in this thesis has developed optimisation techniques that can assist control centre engineers by automatically setting up voltage studies that are low loss and low cost. The proposed voltage optimisation techniques have been shown to produce solutions that are secured against 800 credible contingency cases. A prototype voltage optimisation tool has been deployed, which required the development of a series of novel approaches to extend the functionality of an existing optimisation program. This research has lead to the development of novel methods for handling multi-objectives, contradictory shunt switching configurations and selecting all credible contingencies. Studies indicate that a theoretical loss saving of 1.9% is achievable, equivalent to an annual emissions saving of approximately 64,000 tonnes of carbon dioxide. A novel security constrained mixed integer non-linear optimisation technique has also been developed. The proposed method has been shown to be superior to several conventional methods on a wide range of IEEE standard network models and also on a range of large-scale GB network models. The proposed method manages to further reduce active power losses and also satisfies all security constraints.
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Mohd, Daut Mohamad Hazwan. "Pico-grid : multiple multitype energy harvesting system." Thesis, University of Cambridge, 2019. https://www.repository.cam.ac.uk/handle/1810/289426.
Full textAbstract:
This thesis focuses on the development of a low power energy harvesting system specifically targeted for wireless sensor nodes (WSN) and wireless body area network (WBAN) applications. The idea for the system is derived from the operation of a micro-grid and therefore is termed as a pico-grid and it is capable of simultaneously delivering power from multiple and multitype energy harvesters to the load at the same time, through the proposed parallel load sharing mechanism achieved by a voltage droop control method. Solar panels and thermoelectric generator (TEG) are demonstrated as the main energy harvesters for the system. Since the magnitude of the output power of the harvesters is time-varying, the droop gain in the droop feedback circuitry should be designed to be dynamic and self-adjusted according to this variation. This ensures that the maximum power is capable to be delivered to the load at all times. To achieve this, the droop gain is integrated with a light dependent resistor (LDR) and thermistor whose resistance varies with the magnitude of the source of energy for the solar panel and TEG, respectively. The experimental results demonstrate a successful variation droop mechanism and all connected sources are able to share equal load demands between them, with a maximum load sharing error of 5 %. The same mechanism is also demonstrated to work for maximum power point tracking (MPPT) functionality. This concept can potentially be extended to any other types of energy harvester. The integration of energy storage elements becomes a necessity in the pico-grid, in order to support the intermittent and sporadic nature of the output power for the harvesters. A rechargeable battery and supercapacitor are integrated in the system, and each is accurately designed to be charged when the loading in the system is low and discharged when the loading in the system is high. The dc bus voltage which indicates the magnitude of the loading in the system is utilised as the signal for the desired mode of operation. The constructed system demonstrates a successful operation of charging and discharging at specific levels of loading in the system. The system is then integrated and the first wearable prototype of the pico-grid is built and tested. A successful operation of the prototype is demonstrated and the load demand is shared equally between the source converters and energy storage. Furthermore, the pico-grid is shown to possess an inherent plug-and-play capability for the source and load converters. Few recommendations are presented in order to further improve the feasibility and reliability of the prototype for real world applications. Next, due to the opportunity of working with a new semiconductor compound and accessibility to the fabrication facilities, a ZnON thin film diode is fabricated and intended to be implemented as a flexible rectifier circuit. The fabrication process can be done at low temperature, hence opening up the possibility of depositing the device on a flexible substrate. From the temperature dependent I-V measurements, a novel method of extracting important parameters such as ideality factor, barrier height, and series resistance of the diode based on a curve fitting method is proposed. It is determined that the ideality factor of the fabricated diode is high (> 2 at RT), due to the existence of other transport mechanism apart from thermionic emission that dominates the conduction process at lower temperature. It is concluded that the high series resistance of the fabricated diode (3.8 kΩ at RT) would mainly hinder the performance of the diode in a rectifier circuit.
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Terres, Marco Antonio de Souza Madeira. "Arquiteturas de conversores de tensão para circuitos com múltiplas tensões de alimentação ajustadas de forma dinâmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/141259.
Full textAbstract:
Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%.Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.
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Jahagirdar, Anant. "SOLAR DRIVEN PHOTOELECTROCHEMICAL WATER SPLITTING FOR HYDROGEN GENERATION USING MULTIPLE BANDGAP TANDEM OF CIGS2 PV CELLS AND TH." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3505.
Full textAbstract:
The main objective of this research was to develop efficient CuIn1-xGaxS2 (CIGS2)/CdS thin film solar cells for photoelectrochemical (PEC) water splitting to produce very pure hydrogen and oxygen. Efficiencies obtained using CIGS2 have been lower than those achieved using CuInSe2 and CuIn1-xGaxSe2. The basic limitation in the efficiencies is attributed to lower open circuit voltages with respect to the bandgap of the material. Presently, the main mechanism used to increase the open circuit voltage of these copper chalcopyrites (CuInSe2 and CuInS2) is the addition of gallium. However, addition of gallium has its own challenges. This research was intended to (i) elucidate the advantages and disadvantages of gallium addition, (ii) provide an alternative technique to the photovoltaic (PV) community to increase the open circuit voltage which is independent of gallium additions, (iii) develop highly efficient CIGS2/CdS thin film solar cells and (iv) provide an alternative material in the form of CIGS2/CdS thin film solar cells and an advanced technology in the form of a multiple bandgap tandem for PEC water splitting. High gallium content was achieved by the incorporation of a highly excess copper composition. Attempts to achieve high gallium content produced reasonable but not the best solar cell performance. Few solar cells developed on a molybdenum back contact and an ITO/MoS2 transparent conducting back contact showed a PV conversion efficiency of 7.93% and 5.97%, respectively. The solar cells developed on the ITO/MoS2 back contact form the first generation CIGS2/CdS thin film solar cells and 5.97% is the first ever reported efficiency on an ITO/MoS2 transparent back contact. Reasons for the moderate performance of these solar cells were attributed to significant porosity and remnants of unsulfurized CuGa alloy in the bulk of CIGS2. This was the first attempt to a detailed study of materials and device characteristics of CIGS2/CdS thin film solar cells prepared starting with a highly excess copper content CIGS2 layer. Next, excess copper composition of 1.4 (equivalent to gallium content, x = 0.3) was chosen with the aim to achieve the best efficiency. The open circuit voltage was enhanced by depositing an intermediate layer of intrinsic ZnO between CdS and ZnO:Al layers. The systematic study of requirements for such a layer and further optimization of its thickness to achieve a higher open circuit voltage (which is the greatest challenge of the scientific community) forms an important scientific contribution of this research. The PV parameters for CIGS2/CdS thin film solar cell as measured officially at the National Renewable Energy Laboratory were: open circuit voltage of 830.5 mV, short circuit current density of 21.88 mA/cm2, fill factor of 69.13% and photovoltaic conversion efficiency of 11.99% which sets a new world record for CIGS2 cells developed using sulfurization and the open circuit voltage of 830.5 mV has become the "Voc champion value". New PEC setups with the RuS2 and Ru0.99Fe0.01S2 photoanodes were developed. RuS2 and Ru0.99Fe0.01S2 photoanodes were more stable in the electrolyte and showed better I-V characteristics than the RuO2 anode earlier used. Using two CIGS2/CdS thin film solar cells, a PEC efficiency of 8.78% was achieved with a RuS2 anode and a platinum cathode. Results of this research constitute a significant advance towards achieving practical feasibility and industrially viability of the technology of PEC hydrogen generation by water splitting.Ph.D.
Department of Mechanical, Materials and Aerospace Engineering;
Engineering and Computer Science
Materials Science and Engineering
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Kim, Changdong. "Electrooptic matched filter controlled by independent voltages applied to multiple sets of electrodes." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3305.
Full textAbstract:
Analysis and experimental results on a polarization independent electrooptic
matched filter (EMF) with a center wavelength of 1.53 μm are reported. The EMF
utilizes electrooptic phase-matched TE↔TM conversion in a Ti-diffused waveguide on
a LiNbO3 substrate. The operation of the EMF to select an optical frequency channel is
controlled by applying independent voltages to interdigital electrode sets cascaded
along a single mode waveguide. The device is inherently polarization independent and
has the potential for submicrosecond tuning. The number of selectable channels N is
related to the number of electrode sets P by the formula / 2 1 N P = + . A matrix analysis
is used to determine the TE↔TM conversion efficiency for the case that 8 P = and
5 N = . A driving circuit for the EMF was implemented using a digital-to-analog
converter (DAC) array controlled from a personal computer (PC). Transmittance
spectra of a filter produced in a LiNbO3 substrate are presented. A raised cosine
weighting function applied along the 3.8 cm length of an EMF provides a sidelobe
suppression level better than Â17 dB with a 1.0 nm 3-dB bandwidth.
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Boštík, Ondřej. "Koaxiální multiplexer pro automatizované měření AC proudu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-240832.
Full textAbstract:
Master’s thesis in the theoretical part deals with literature review on the topic of measurement errors and measurement uncertainties. The practical part deals with the simulation of additional capacitive and resistive load on the amplitude and phase error during shunts based measurement. For this simulation is used mathematical apparatus of cascade matrix of two-ports and their connections. For the actual simulation is used script for MATLAB. Furthermore, the work deals with the design of voltage follower to eliminate simulated errors and its practical realization. The last part deals with the design of the coaxial multiplexer for switching current shunts developed in the Czech Metrological Institute in Brno.
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Hsu, Wei-Han, and 徐偉瀚. "Low Voltage Multiplier Design." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/62988094270272474445.
Full textAbstract:
碩士國立中正大學
電機工程研究所
99
A low voltage Modified Booth multiplier design with reduced spurious switching is proposed in this research. In recent years, one of the most important issues is that electronic devices are forced on portable and low power design. In our research, our low voltage multiplier design can be applied in 0.35um and 65nm process technology and effectively reduce the glitch power. In multi-processors system, multiplier usually takes longest evaluation time and it is mostly used in processors. During the evaluation time, the glitch will generate unnecessary power consumption. So decreasing glitch is a suitable and efficient method. Through simulations for normal voltage, multipliers in 0.35um process with reduced spurious switching could achieve 77~79% improvement than other multiplier without the de-glitch technique. For low voltage, there could be 95% power reduction. In 65nm technology, our design could work at the lowest voltage 0.33V and compare with other de-glitch multiplier the proposed scheme can save 42% power consumptions.
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Yeha, Yu-Kwang, and 葉昱崑. "Low-Voltage and High-Speed BiCMOS Multiplier." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/08000955059537268110.
Full textAbstract:
碩士淡江大學
資訊工程研究所
83
Low voltage low power high speed integrated circuits are critical elements for portable electronic systems. In order to exploit this trend, in this thesis,a high-speed BiCMOS 16*16-bit multiplier with a supply voltage of 2.5V is proposed and ana- lyzed. Multiplication is one of the basic operation in digital sig- nal processing system, the speed of multiplication is critical of whole system's performance. The proposed low-voltage high- speed multiplier can be adopted to the design of high perfor- mance digital processing systems. Multiplication contains two basic operations:(a) partial-product generation and ;(b)partial- product addition. In order to improve the performance of the multiplier, modified Booth's algorithm and Wallace tree structure are used. The modified Booth's algorithm scheme can reduce the number of partial-product half per each multiplication. The Wa- llace- tree adder array and CLA adder are used to minimize the critical-delay-path gate stages. For high-speed and low- voltage requirement, the BiCMOS and CMOS circuits are used in this multiplier. The modified Booth's encoder and CLA are implemeted by the BiCMOS circuits for large capacitance loading. The Wallace addition tree and the Booth's decoder are implemented by the CMOS circuits for high packing density. The implementation of this chip is based upon the 1.0um DPDM BiCMOS process,which is provided by the Chip Implementation Center (CIC) of National Science Council(NSC) of the Republic of China. The procedures of design, simulation, layout,verification and testing consideration are included.
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Yi-TingLin and 林義庭. "A New High Voltage-Gain Converter with Coupled-Inductors and Voltage Multiplier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/79759125652189084636.
Full textAbstract:
碩士國立成功大學
電機工程學系
102
High step-up techniques have been explored and developed for industrial applications over the past decades. Especially for renewable energy systems, the relatively low voltage must be boosted to high one for grid-connection applications. In this thesis, a new current-fed, high step-up converter integrating coupled-inductors with voltage multiplier cell is proposed for applications in renewable energy systems. With the current-fed configuration, continuous low-ripple input current can be achieved, which can avoid the use of input electrolytic capacitor to enhance the reliability of the whole system. Also, by employing the voltage step-up cell, the voltage stress of the main switch is reduced and the leakage energy of coupled-inductors can be recycled to the output capacitor. Therefore, the low-voltage rated MOSFETs with low RDS_ON can be used to reduce the conduction losses. In addition, the reverse-recovery problem of the diodes is alleviated effectively by the leakage inductance, as designed in the proposed circuit. The operation principles, the voltage stress analyses, and the design guidelines of the components used in the proposed are discussed in detail in the thesis. Finally, a laboratory prototype circuit of 300 W, 400 V output voltage with input voltage ranging from 30 to 42 V is implemented to verify the effectiveness of the proposed converter. The results show that only one MOSFET is employed not only to simplify the circuit configuration, but improve the system reliability. A maximal efficiency of 95.63 % at 90 W and 92.98 % at the full load have been demonstrated in the experiments.
37
Chen, Tien-Hung, and 陳田宏. "Modeling and Control For Interleaved Voltage-Multiplier Boost Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/z63fe8.
Full textAbstract:
碩士國立交通大學
電控工程研究所
107
In this paper, we realize a high voltage gain DC/DC converter with an interleaved voltage multiplier boost circuit. By analyzing the mode of the circuit, we proposed a new control method with an output voltage regulation loop. Both voltage regulation and current-sharing have good performance with extended duty ratio. Furthermore, the small-signal transfer function for the output voltage control signals are obtained in the thesis. Take the interleaved voltage-doubler boost converter as an example, we use state-space average method and find that the transfer function can be derived as forth order system. According to the design specifications of the controller, we can implement the control of interleaved voltage multiplier boost circuit. Then, PI-type controller is designed to implement the voltage regulation controller. All the controllers are implemented in Field Programmable Gate Array (FPGA). The provided simulation and experimental results verify the proposed interleaved control has the characteristics of high voltage gain and current-sharing. In the same time, we prove that the switched capacitors between two phases not only have capability of step up the output voltage but also can reduce the voltage stress for two switches in some switching modes.
38
"Adiabatic quasi-static CMOS multiplier." 2000. http://library.cuhk.edu.hk/record=b5890269.
Full textAbstract:
Mak Wing-sum.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.
Includes bibliographical references (leaf [68]).
Abstracts in English and Chinese.
List of Figures --- p.I
List of Tables --- p.III
ACKNOWLEDGMENTS
ABSTRACT
Chapter Chapter I --- Introduction
Chapter 1.1 --- Introduction - Low Power --- p.I-1
Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1
Chapter 1.2.1 --- Static Power Dissipation --- p.I-2
Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5
Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8
Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10
Chapter 1.4 --- Objective of the Project --- p.I-10
Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic
Chapter 2.1 --- Low Power Design --- p.II-12
Chapter 2.2 --- Adiabatic Switching --- p.II-12
Chapter 2.3 --- Adiabatic Logic --- p.II-14
Chapter 2.4 --- History of Adiabatic Logic --- p.II-17
Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter
Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18
Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20
Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22
Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23
Chapter Chapter IV --- Power Clock Generator
Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24
Chapter 4.2 --- Power Clock Generator
Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV
Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27
Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier
Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32
Chapter 5.2 --- Structure of Multiplier --- p.V-34
Chapter Chapter VI --- Simulations
Chapter 6.1 --- AqsCMOS Inverter
Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38
Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39
Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI
Chapter 6.2 --- Power Clock Generator --- p.VI -42
Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45
Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46
Chapter ChapterVII --- evaluations
Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51
Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus
Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54
Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55
Chapter 7.2.3 --- Input Current Measurement --- p.VII -58
Chapter 7.3 --- Power Measurement --- p.VII -63
Chapter Chapter VIII --- Conclusions and Fiirthfr Developments
Chapter 8.1 --- Conclusions --- p.VIII -65
Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65
Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65
Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66
Chapter 8.2 --- Further Development --- p.VIII -66
Appendix I micro-photography of aqscmos multiplier
Appendix II micro-Photography of CMOS multiplier
Appendix III micro-photography of AqsCMOS inverter chain testing modules
Appendix IV power - meter simulation approach
Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers
Reference
39
Ann, Jiang, and 安正. "Development of Ion Fan Electrodes using adjustable voltage multiplier circuit." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/36212773267454012547.
Full textAbstract:
碩士國立臺灣大學
機械工程學研究所
101
A ion fan is consisted of a pair of electrodes between which generated ions with applied high voltages can drive the air flow. Most study use pin-to-plate or pin-to-ring as its electrodes to generate ion wind, which the pin is at high potential. However, it has been studied that if one put a ring near the high potential pin can increase the velocity of ion wind. This study investigate the high potential electrode’s shape by using multi-pin circle arrangement instead of single pin in the middle. Additionally, a high voltage power supply (HVPS) is necessary of the ion fan, this study use voltage multiplier circuit as the HVPS which consist of 50 electrolytic capacitors and diodes. The experiment showing that using different capacitance of electrolytic capacitors can decrease the voltage drop which appears in using single capacitance of electrolytic capacitors. Finally, the multi-pin circle arrangement using 3 pins has a velocity of 1.21 m/s which is larger than 0.85 m/s when using 6 pins and is slightly smaller than single pin in the middle which is 1.23 m/s while the supplying voltage was in 10.5kV.
40
Huang, Yen-Mou, and 黃彥謀. "A New Adder and Multiplier Architecture for Low-Voltage VLSI Systems." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/32043408245518498250.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
87
This thesis reports a conditional carry select (CCS) adder circuit with a successively-incremented-carry-number block (SICNB) structure for low-voltage VLSI implementation in the second chapter. Owing to the successively-incremented-carry-number block (SICNB) structure, the new 16-bit SICNB CCS adder provides a 37% faster speed as compared with the conventional conditional carry select adder based on the SPICE results at a supply voltage of 1.5V. In the third chapter, this thesis introduces sign-select Booth algorithm, and Wallace tree with 4-2 compressors. It reports a new 4-2 compressor which is superior to conventional 4-2 compressors in speed performance. Our 8x8-bit multiplier provides a 51% faster speed as compared with the multiplier using conventional 4-2 compressors and carry-skip adders based on the SPICE results at a supply voltage of 1.5V.
41
Lo, Chi-yin, and 羅吉胤. "Implementation of a Full-bridge Resonant Converter with Voltage Multiplier Using Phase-shift Control for High Voltage Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/80347611276341088475.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
97
In this thesis, a high voltage converter is studied and implemented for X-ray tube applications. This circuit is mainly composed of full-bridge resonant inverter and multi-units of full-wave voltage-doublers that utilize phase-shift control to regulate the output voltage. The operating principle and theory of the proposed converter are presented. Since the high voltage transformer have many winding, the isolation and stray components must be considered in the circuit analysis. Finally, the proposed high voltage converter is a practical application to X-ray tubes, a laboratory prototype with 400 V input and 50-70 kV/50-100 W output is implemented to verify the theoretical analysis.
42
Huang, Pin-Yu, and 黃品諭. "A Novel Taiwan Tech Voltage Multiplier for Step-Up Power Conversion Applications." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/37818340627344743068.
Full textAbstract:
博士國立臺灣科技大學
電機工程系
103
By combining two Cockcroft-Walton half-wave voltage multiplier rectifiers, a novel Taiwan Tech voltage multiplier rectifier is proposed in this dissertation. Applying it to a widely used dual-inductor current-fed converters, low voltage rating devices with low turns-ratio transformer can be used to achieve the required high voltage gain. Moreover, output voltage ripple is significantly reduced due to its built-in output voltage ripple cancellation mechanism. Consequently, small capacitance film capacitors can be used instead of high voltage-rating electrolytic capacitors. Thus, the reliability of the power converter can be enhanced. Furthermore, the proposed has significantly reduction in two key issues, voltage drop and voltage ripple, for high output voltage applications. Thus, more stages voltage multiplier with lower voltage-rating components can be applied to meet the same output voltage specification. These features make the proposed voltage multiplier rectifier desirable for high frequency, high efficiency, high output-voltage, and high reliability power applications, such as the sustainable energy source power system or some high voltage medical instrument power conversion applications. In addition to operation principle, theoretical analysis, and design considerations, a dual-inductor current-fed converter with Taiwan Tech voltage doubler rectifier and a dual-inductor current-fed boost converter with six-fold Taiwan Tech voltage multiplier rectifier as examples are described in Chapter 2 and Chapter 3, respectively. Three six-fold dual-inductor current-fed converters with a Cockcroft-Walton voltage multiplier rectifier, with a symmetrical Cockcroft-Walton voltage multiplier rectifier, and with a Taiwan Tech voltage multiplier rectifier, have been implemented with same 100 kHz, 24~36V input, 380V/380W output specifications. Also the performance comparisons among these circuits are made.
43
Chen, Yun-Wei, and 陳畇瑋. "A Voltage Multiplier Model for Low Frequency Low Duty Cycle and Subthreshold Operations." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/62420247320197521118.
Full textAbstract:
碩士國立清華大學
電子工程研究所
101
Voltage multipliers, which boost a low AC voltage to a higher DC voltage, have many applications today. The input signals, if generated on chip, can have a relatively high frequency, large signal swing and a fixed duty cycle. On the other hand, if the input signal is taken from external RF sources or mechanically generated electrical signals, then the input can have a very low signal swing, low frequency or low duty cycle. This thesis studies how to apply the conventional voltage multiplier to these low voltage, low frequency and low duty cycle conditions. The conventional voltage multiplier (Dickson charge pump) has been studied extensively. A simple analytical model relates the output voltage to the input voltage has been derived. As long as the input signal has a swing larger than the transistor’s threshold voltage, the output voltage can be predicted using a simple equation. But when the input swing is much lower than the threshold voltage, then the equation breaks down. We find that we can extend the equation to lower input swings, if threshold voltage is replaced by an effective threshold voltage. To address the low frequency and duty cycle issues, pulse clustering effects are studied. It is also found that adding a ring oscillator to increase signal frequency is a very effective approach. If possible, optimizing transistor threshold voltage can increase output voltage, increase transfer efficiency or reduce chip area without additional cost. In this thesis, a real electromotive force signal is used as input signal. The amplitude of this signal is -0.26 (V) to 0.26 (V). The oscillation frequency is 5 (Hz) and the duty cycle is 12.5%. The objective output voltage is 3.6 (V) and output current is 1 (mA). All simulations are based on TSMC 0.35um CMOS models.
44
Wang, Chu-Kang, and 汪楚剛. "A Novel Isolated Bidirectional DC Converter With Embedded High Side Voltage Multiplier Module." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/92765651368449480152.
Full textAbstract:
碩士國立清華大學
電機工程學系
101
The main purpose of this thesis is focused on the study of an interface between a battery energy storage system and a paralleled DC microgrid with a view to develop to a novel bidirectional dc converter for regulating the DC microgrid. Basically, the major contributions of this thesis can be summarized as follows. First, a new bidirectional dc converter structure is proposed. This new topology can not only achieve electrical isolation and bidirectional power flow capability, but also can be embedded with a voltage multiplier module in high voltage side to obtain N times voltage step up/down, where N is a positive integer greater than is equal to two. Also, starting from N≧2, only one more active switch and one more capacitor are required for increasing/decreasing one more voltage level step up/down. Secondly, to demonstrate the way of increasing the power handling capability, two sets of the proposed bidirectional basic converter are interconnected together such that the high voltage sides are in series and the low voltage sides are in parallel. Meanwhile, the corresponding DC and AC models are derived for feedback controller design. Finally, a 1kW prototype with 400V high side voltage and 48V low side voltage have been constructed to verify the feasibility of the proposed converter. It can be seen that maximum efficiencies are 94.1% and 94.4% for step down and step up operation modes respectively.
45
Ko, Chun-Cho, and 柯鈞琢. "Cockcroft-Walton voltage multiplier with power factor correction based on soft-switching techniques." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/nj636x.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
99
This paper proposes a soft-switching technique applying to a single-stage single-phase ac to high voltage dc converter based on Cockcroft-Walton (CW) voltage multiplier circuit. Originally operating under hard-switching, the proposed converter improves switching characteristics by adding an auxiliary circuit for achieving soft-switching. The circuit operation principle of the proposed converter is presented in this paper. The design consideration for determining the values of circuit components used in the implementation is driven as well. For improving the line condition, power factor correction is applied to the proposed converter. Some conventional PFC control methods can be easily adapted to the proposed converter with few modifications. For convenience, this paper employs a commercial PFC IC to implement the controller for the proposed converter. The PWM signal generated form the PFC IC is modified by a simple digital circuit and then sends to the main and auxiliary switches in the power stage. A 500W/1200V prototype is built for test, measurement and evaluation. Finally, the experimental results demonstrate the validity of the proposed converter.
46
Ping-HsiangHuang and 黃鈵翔. "A Novel Low Ripple Converter with Interleaved Voltage Multiplier for X-ray Machine." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/06403365558885866847.
Full textAbstract:
碩士國立成功大學
電機工程學系
104
The purpose of this study is to explore and implement a high voltage converter for X-ray machine. Currently, the X-ray machine have large output voltage ripple making the body and cause harm suffered increased X-ray imaging artifact influence doctors to determine shortcomings. In this thesis, an interleaved full-wave voltage multiplier which improve voltage ripple is proposed, its main concept is using two reverse voltage ripple in the way of superposition and cancellation so that the output voltage ripple is reduced, and finally develop a novel low ripple converter with interleaved voltage multiplier. Its input voltage is 400V, output voltage is 40kV, output power is 300W, and voltage ripple factor is 0.137%. Moreover, this proposed circuit compares voltage ripple with traditional half-wave voltage multiplier and symmetrical full-wave multiplier. Theirs voltage ripple factor are 3.98% and 0.7%. Experimental result shows the output voltage ripple is better than that of the conventional circuits.
47
Wu, Wei-Hong, and 吳威宏. "Low-Voltage Low-Power CMOS Multiplier Design Using Pipeline Latch High-Level Synthesis Approach." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/02208380310385112207.
Full textAbstract:
碩士臺灣大學
電子工程學研究所
98
The integrate-circuit technology scale down recently, more functionality can be combined into a single chip. So circuit complexity thereupon increases, performance and power consumption will be considered. The thesis describe a ways to increase speed of a circuit, and make up the high-level circuit. Chapter 1 introduce CMOS very large scale integrated circuits reason, power consumption and simulation software . Chapter 2 introduces a 16-bit Wallace tree multiplier circuit with VDD = 0.5V. Latch technology insert the multiplier become pipeline structure. Using Synopsys Primetime EDA tool analyses result, We can get the 257% increase operation frequency. Because of the final adder is bigger delay than other path of the multiplier circuit, so we can get the 95% increase operation frequency by change the VDD = 1V. Chapter 3 introduces a high-level multiplier circuit consists of 16-bit multiplier circuits, compare with high-level Wallace multiplier, performance and power consumption have not been improved, but is easily scalable to higher bit precision by duplicating sub-multiplier and adding an additional levels of reduction, allows for short design time. We have a way to increase speed by insert pipeline latch into final adder of the high-level multiplier.
48
Chan, Yi-hsun, and 詹宜勳. "High Step-Up DC-DC Converter with Cockcroft-Walton Voltage Multiplier for Solar Power System Applications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/b8drg6.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
99
This thesis proposes a high step-up dc-dc converter for boosting the low dc voltages from the dc power source systems such as batteries, photovoltaic modules, and fuel cells. Based on the high step-up ratio characteristic of Cockcroft-Walton (CW) voltage multiplier, the proposed converter can provide high step-up ratio without using the step-up transformers. This thesis also derives a new method to represent the equivalent circuit of CW voltage multiplier for simplifying the analysis of the circuit and the simulation. This thesis applies converter in solar power system and use the perturbation and observation method as the control strategy of maximum power point tracking to achieve the maximum power output of solar energy. In addition, due to the output side of CW multiplier consists of cascaded capacitors, therefore, the last stage combines three-level inverter to provide ac output. The proposed solar power system employs a digital signal processor (DSP, TMS320F2812) as the digital controller to process the feedback signals and provides the pulse width modulation signals for the switches. The voltage recorder is used to record the variation of the power from system in whole day.
49
Chen, Sing-Jhao, and 陳星兆. "A Soft-switching High Step-Up AC-DC Converter Based on Cockcroft-Walton Voltage Multiplier with PFC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/48090315570892798844.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
101
This paper proposes a single-phase soft-switching high step-up ac-dc converter based on Cockcroft-Walton voltage multiplier (CWVM) with power factor correction (PFC), which is formed by one boost inductor, one bidirectional switch, one auxiliary circuit and a CWVM. By applying PFC technology, the proposed converter promises a nearly unity power factor and low distorted line current and provides adjustable high step-up dc voltage that conventional CWVM circuit cannot achieve. In order to reduce the switching losses and EMI, an auxiliary circuit for implementing soft-commutation is added to the power stage of the proposed converter. Operating at fixed switching frequency, in which both main and auxiliary switches are turned off with ZCT. The operation principle, design considerations and control strategy of the proposed converter all are detailed and investigated in this paper. A 1.2kV/500W laboratory prototype, which employs a commercial PFC IC UC3854 as controller, is built for test, measurement and evaluation. Finally, simulation and experimental results demonstrate the validity of the proposed converter.
50
Nien, Nai-wen, and 粘乃文. "A Three-Phase to Single-Phase Matrix Converter with Power Factor Correction Applied to Cockcroft-Walton Voltage Multiplier." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/jrmkr5.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
99
This thesis presents a three-phase to single-phase matrix converter based on Cockcroft-Walton voltage multiplier. The proposed converter transfers the three-phase ac source with line frequency to a single-phase ac source with variable high frequency, then charges the voltage multiplier. Compared with the conventional Cockcroft-Walton voltage multipliers, the proposed converter provides the line current with low harmonic distortion, adjustable power factor at the ac source, ripple reduction and regulated dc output voltage. The mathematical equation for the matrix converter has been verified by using MATLAB/Simulink that includes power stage and control block diagram. Finally, computer simulation results are shown to verify the performance of the proposed three-phase to single-phase?nmatrix converter based on Cockcroft-Walton voltage multiplier.