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Journal articles on the topic 'Voltage multiplier'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

de la Cruz-Alejo, Jesús, and L. Noe Oliva-Moreno. "Low Voltage FGMOS Four Quadrants Analog Multiplier." Advanced Materials Research 918 (April 2014): 313–18. http://dx.doi.org/10.4028/www.scientific.net/amr.918.313.

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In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

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2

Suvarna, S., K. Rajesh, and T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic." International Journal of Students' Research in Technology & Management 4, no. 1 (March 10, 2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.

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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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3

Moghaddam, Majid, Mohammad Hossein Moaiyeri, Mohammad Eshghi, and Ali Jalali. "A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter." Journal of Circuits, Systems and Computers 24, no. 08 (August 12, 2015): 1550124. http://dx.doi.org/10.1142/s0218126615501248.

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This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V DDL , V DDH ) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

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4

Soto, Leopoldo, and Luis Altamirano. "A pulse voltage multiplier." Review of Scientific Instruments 70, no. 3 (March 1999): 1891–92. http://dx.doi.org/10.1063/1.1149686.

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5

Arnold, B. "Current/voltage hybrid multiplier." Electronics Letters 24, no. 14 (1988): 860. http://dx.doi.org/10.1049/el:19880586.

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6

Gupta, S. S., D. R. Bhaskar, and R. Senani. "Synthesis of New Single CFOA-Based VCOs Incorporating the Voltage Summing Property of Analog Multipliers." ISRN Electronics 2012 (September 18, 2012): 1–8. http://dx.doi.org/10.5402/2012/463680.

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Recently, current feedback operational amplifier (CFOA) and analog multiplier-(AM-) based-voltage controlled oscillators (VCOs) have been published in the literature which require 2 CFOAs and 2 AMs for linear tuning law between control voltage and frequency of oscillation. In this paper, a family of eight new voltage-controlled oscillators (VCOs), with linear tuning laws, employing only a single CFOA in conjunction with two analog multipliers (AMs), has been derived through a systematic state-variable methodology. This has been made possible by exploiting the voltage summing property of the multiplier chosen which has never been done in the literature earlier. The workability of the presented VCOs has been verified by experimental results based on AD844 type CFOAs and AD534 type AMs, and the advantages of new circuits over the previously known CFOA-AM-based VCOs have been highlighted.

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7

Eguchi, Kei, Sawai Pongswatd, Shinya Terada, and Ichirou Oota. "Parallel-Connected High Voltage Multiplier with Symmetrical Structure." Applied Mechanics and Materials 619 (August 2014): 173–77. http://dx.doi.org/10.4028/www.scientific.net/amm.619.173.

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A high voltage multiplier is proposed for non-thermal food processing systems utilizing an underwater shockwave. Unlike conventional Cockcroft-Walton Voltage Multiplier (CWVM) providing a DC output from an AC input, the proposed multiplier consists of two switched-capacitor-based DC-DC converters with different polarities. Owing to the symmetrical bipolar structure without magnetic component, the proposed multiplier can achieve faster response speed and lower voltage drop than the conventional CWVM. The theoretical analysis and simulation program with integrated circuit emphasis (SPICE) simulations show the effectiveness of the proposed voltage multiplier.

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8

Iqbal, Shahid. "A Hybrid Symmetrical Voltage Multiplier." IEEE Transactions on Power Electronics 29, no. 1 (January 2014): 6–12. http://dx.doi.org/10.1109/tpel.2013.2251474.

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9

Luo, Ye-Sing, and Shen-Iuan Liu. "A Voltage Multiplier With Adaptive Threshold Voltage Compensation." IEEE Journal of Solid-State Circuits 52, no. 8 (August 2017): 2208–14. http://dx.doi.org/10.1109/jssc.2017.2693228.

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10

Amudhavalli, Dhanaraj, Nalin Kant Mohanty, and Ashwin Kumar Sahoo. "Interleaved quadratic boost converter integrated with Dickson voltage multiplier with energy storage for high power photo voltaic applications." International Journal of Power Electronics and Drive Systems (IJPEDS) 12, no. 2 (June 1, 2021): 957. http://dx.doi.org/10.11591/ijpeds.v12.i2.pp957-967.

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In this paper interleaved quadratic boost converter with Dickson voltage multiplier is proposed. Photovoltaic system is connected to high power load through the proposed converter. Structure of this high gain interleaved converter comprised of two stages: interleaved quadratic boost converter stage and Dickson voltage multiplier stage. Interleaved quadratic boost converter is a parallel combination of two quadratic boost converter. The interleaving increases frequency of converter that could be filtered using small capacitors, making input current smoother than the current of conventional quadratic boost converter. Thus, interleaved circuit minimizes current ripple present in input current, cascading of voltage multiplier cell increases the gain voltage ratio of converter making it suitable for high power, high voltage gain photo voltaic applications. Stress voltage of the switches and reverse recovery problems gets reduced, thereby reducing EMI problems. 300W prototype capable of increasing 24V input voltage to 400V output voltage is designed and results tested using MATLAB/Simulink software. Hardware prototype is also implemented to verify simulation results. Also, application of this converter in integrated energy storage is demonstrated.

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11

Chen, Wei Ping, Tian Yang Wang, Hong Lei Xu, and Xiao Wei Liu. "A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair." Key Engineering Materials 483 (June 2011): 487–91. http://dx.doi.org/10.4028/www.scientific.net/kem.483.487.

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A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.

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12

Razavi, Seyyed Masoud, and Seyyed Reza Talebiyan. "Novel design of array multiplier." Ciência e Natura 37 (December 19, 2015): 312. http://dx.doi.org/10.5902/2179460x20788.

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In this paper a new array multiplier has been proposed, which has lower power consumption than the regular array multipliers. This technique has been applied on two conventional and leapfrog array multipliers. In the formation of 8×8 multiplier all designs proposed in this paper have been implemented using the HSPICE by the use of 180 nm TSMC technology at a supply voltage 1v. To verify the performance of the proposed structures, structures have been simulated in 130 nm & 65 nm PTM technologies. The simulation results show that applying the return technique in the array structures causes power consumption reduction and consequently PDP reduction. This improvement for 180 nm technology in the conventional array structure is 13.32 % and in the leapfrog array structure is 23.27 %. It should be noted that this technique substantially makes the number of transistors less and as a result area reduction.

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13

Hong, Sangjin, Suhwan Kim, and Wayne E. Stark. "Low-power Application-specific Parallel Array Multiplier Design for DSP Applications." VLSI Design 14, no. 3 (January 1, 2002): 287–98. http://dx.doi.org/10.1080/10655140290011087.

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Digital Signal Processing (DSP) often involves multiplications with a fixed set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error of the computation, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltage. Dissipation is further reduced when conventional array multiplier is modified disabling the multiplier rows that do not affect the multiplication's outcome. We have used our methodology to design low-power parallel array multipliers for the Fast Fourier Transform (FFT). Simulation results show that our approach can result in significant up to 76% power savings over conventional array multipliers on 64-coefficient FFT computation.

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14

Wijono, Wijono, Zainul Abidin, Waru Djuriatno, Eka Maulana, and Nola Ribath. "Design of 4-stage Marx generator using gas discharge tube." Bulletin of Electrical Engineering and Informatics 10, no. 1 (February 1, 2021): 55–61. http://dx.doi.org/10.11591/eei.v10i1.1949.

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In this paper, a Marx generator voltage multiplier as an impulse generator made of multi-stage resistors and capacitors to generate a high voltage is proposed. In order to generate a high voltage pulse, a number of capacitors are connected in parallel to charge up during on time and then in series to generate higher voltage during off period. In this research, a 6kV Marx generator voltage multiplier is designed using gas discharge tube (GDT) as an electronic switch to breakdown voltage. The Marx generator circuit is designed to charge the storage capacitor for high impulse voltage and current generator applications. According to IEC 61000-4-5 class 4 standards, the storage capacitor must be charged up to 4 kV. The results show that the proposed Marx generator can produce voltages up to 6.8 kV. However, the storage capacitor could be charged up to 1 kV, instead of 4 kV in the standard. That is because the output impulse voltage has narrow time period.

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15

Zhang, Neng, Danny Sutanto, Kashem M. Muttaqi, Bo Zhang, and Dongyuan Qiu. "High‐voltage‐gain quadratic boost converter with voltage multiplier." IET Power Electronics 8, no. 12 (December 2015): 2511–19. http://dx.doi.org/10.1049/iet-pel.2014.0767.

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16

Mandegaran, Sam, and Ali Hajimiri. "A Breakdown Voltage Multiplier for High Voltage Swing Drivers." IEEE Journal of Solid-State Circuits 42, no. 2 (February 2007): 302–12. http://dx.doi.org/10.1109/jssc.2006.889390.

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17

Sadeghi, Mohsen, Mahya Zahedi, and Maaruf Ali. "The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications." Annals of Emerging Technologies in Computing 3, no. 3 (July 1, 2019): 19–27. http://dx.doi.org/10.33166/aetic.2019.03.003.

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This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

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18

Uno, Masatoshi, Teruhisa Ueno, and Koji Yoshino. "Cell Voltage Equalizer Using a Selective Voltage Multiplier with a Reduced Selection Switch Count for Series-Connected Energy Storage Cells." Electronics 8, no. 11 (November 7, 2019): 1303. http://dx.doi.org/10.3390/electronics8111303.

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Cell voltage equalization is mandatory to eliminate voltage imbalance of series-connected energy storage cells, such as lithium-ion batteries (LIBs) and electric double-layer capacitors (EDLCs), to ensure years of safe operations. Although a variety of cell equalizers using selection switches have been proposed, conventional techniques require numerous switches in proportion to the cell count and are prone to complexity. This paper proposes a novel cell voltage equalizer using a selective voltage multiplier. By embedding selection switches into the voltage multiplier-based cell voltage equalizer, the number of selection switches can be reduced in comparison with that in conventional topologies, realizing the simplified circuit. A prototype for twelve cells was built, and an equalization test using LIBs was performed. The voltage imbalance decreased down to approximately 20 mV by the proposed equalizer, and the standard deviation of cell voltages at the end of the equalization test was as low as 10 mV, demonstrating its equalization performance.

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19

Alzahrani, Ahmad, Pourya Shamsi, and Mehdi Ferdowsi. "Interleaved Multistage Step-Up Topologies with Voltage Multiplier Cells." Energies 13, no. 22 (November 17, 2020): 5990. http://dx.doi.org/10.3390/en13225990.

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This paper proposes a family of high-voltage-gain step-up dc-dc converters for photovoltaic integration application. The proposed converters are capable of converting the low voltage from input sources to a dc bus. The proposed family is constructed of interleaved single-switch multistage boost converters and voltage multiplier cells (VMC). The proposed converters feature low voltage stress across the components, equal current sharing among all phases, and a smooth input current. Moreover, the proposed family of converters has a modular structure in both the VMC and the boost stage. That is, the VMC can have N number of cells, and the boost stage can have k number of stages. The k can be different in each phase, allowing the designers to integrate two independent renewable energy sources with different output voltages. An example converter was explained, analyzed, and simulated. An 80 W hardware prototype was implemented to confirm the converter’s operation and validate the analysis.

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20

Zhu, Binxin, Zihao Wei, Yao Chen, Han Wang, and D. Mahinda Vilathgamuwa. "Multiple Input-Terminal Voltage Multiplier Circuit." IEEE Transactions on Industry Applications 56, no. 5 (September 2020): 5075–82. http://dx.doi.org/10.1109/tia.2020.2998670.

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21

Semenov, V. K., and Yu A. Polyakov. "Circuit improvements for a voltage multiplier." IEEE Transactions on Appiled Superconductivity 11, no. 1 (March 2001): 550–53. http://dx.doi.org/10.1109/77.919404.

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22

Boonchu, Boonchai, and Wanlop Surakampontorn. "Voltage-mode threshold-independent analogue multiplier." International Journal of Electronics 96, no. 5 (May 2009): 457–66. http://dx.doi.org/10.1080/00207210902738075.

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23

Liu, S. I. "Low voltage CMOS four-quadrant multiplier." Electronics Letters 30, no. 25 (December 8, 1994): 2125–26. http://dx.doi.org/10.1049/el:19941427.

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24

Liu, Shen-Iuan, and Cheng-Chieh Chang. "Low-voltage CMOS four-quadrant multiplier." Electronics Letters 33, no. 3 (1997): 207. http://dx.doi.org/10.1049/el:19970168.

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25

Azmi, Nor A., Sohiful A. Z. Murad, Azizi Harun, and Rizalafande C. Ismail. "5V to 6kV DC-DC Converter Using Switching Regulator with Cockcroft-Walton Voltage Multiplier for High Voltage Power Supply Module." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 12, no. 2 (February 28, 2019): 162–71. http://dx.doi.org/10.2174/2352096511666180605094827.

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Background: This paper describes the design of 5 V to 6 kV DC-DC converter by using a switching regulator with Cockroft-Walton (C-W) voltage multiplier for a high voltage power supply module. Methods: The proposed design consists of Pulse Width Modulation (PWM) controller circuit, voltage multiplier, and feedback signal. A single unit of 5 V input triggers LT1618 controller circuit to generate 20 V which then produces 300 V from LT8331 output that is connected to diode-capacitor multiplier circuit to achieve final 6 kV. A negative feedback signal is required to stabilize an output voltage. With the implementation of C-W voltage multiplier technique, the output is boosted up as required from the input signal voltage 5 V DC. Results: The LTspice simulation results indicate that the proposed DC converter can generate 6.20 kV. Line regulation of 17 % and the load regulation of 14 % are obtained based on the proposed design. Conclusion: The proposed design is suitable for high voltage power supply module.

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26

Ali, Esraa Mousa, Nor Zaihar Yahaya, Omar Aqeel Saraereh, Anwar Hamdan Al Assaf, Bilal Hasan Alqasem, Shahid Iqbal, Oladimeji Ibrahim, and Amit V. Patel. "Power Conversion Using Analytical Model of Cockcroft–Walton Voltage Multiplier Rectenna." Electronics 10, no. 8 (April 7, 2021): 881. http://dx.doi.org/10.3390/electronics10080881.

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A voltage multiplier rectenna is a combination of a voltage multiplier rectifier and an antenna used for the conversion of AC to DC. It is an essential part of the system of RF energy harvesting. Conventional rectennas are characterized by low conversion efficiency. This study presents an analytical novel mode designed for RF energy harvesting systems to study the voltage and current output of rectifier stages for efficiency optimization. The design contains a voltage multiplier rectification circuit with seven stages. The Schottky diode HSMS 285-C was selected for the circuit modeling voltage multiplier circuit. Advanced Design System (ADS) simulation was used to validate the equations of the theoretical model solved with MATLAB code. The fabricated system was tested for an input power range of 10 μW to 100 mW; the maximum output power is 0.2577 mW with maximum efficiency of 29.85%.

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27

Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (September 27, 2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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28

Suresh, Lakshmy, and Anitha R. Anitha.R. "A Boost Converter with Voltage Multiplier for Photovoltaic Applications." Indian Journal of Applied Research 4, no. 4 (October 1, 2011): 185–88. http://dx.doi.org/10.15373/2249555x/apr2014/56.

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29

Korolkov, Oleg, Raul Land, Jana Toompuu, Natalja Sleptsuk, and Toomas Rang. "SiC JBS Diode Symmetrical Voltage Doubler Represented as the Diffusion-Welded Stack." Materials Science Forum 924 (June 2018): 862–65. http://dx.doi.org/10.4028/www.scientific.net/msf.924.862.

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In the present work, the prototype of a voltage multiplier represented as the diffusion-welded stack is presented. Two options of multiplier prototypes are considered: the scheme with external capacitors and the multiplier of the vertical composition using the diode's own capacitance. Oscillograms of input and output signals for both multiplier composition are presented.

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30

Mogi, Taketo, Takumi Ishii, Kazuhito Hashimoto, and Ryuhei Nakamura. "Low-voltage electrochemical CO2 reduction by bacterial voltage-multiplier circuits." Chemical Communications 49, no. 38 (2013): 3967. http://dx.doi.org/10.1039/c2cc37986d.

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31

Ali Azam Khan, Md, and Mohammad Ali Choudhury. "Efficient Voltage Regulation with Modified Hybrid SEPIC DC-DC-Converter." MATEC Web of Conferences 160 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201816002004.

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Switch mode dc-dc converters are attractive for their small size, ease of control and efficient power conversion. Output voltage is regulated by duty cycle control of semiconductor switch of switch mode dc-dc converters. The voltage gain and efficiency of practical switching regulators deviate from ideal values at extreme duty cycles. Also, desired gain /attenuation is not achievable at high/low duty cycles. In applications where high gain or high attenuation of voltage is desired with acceptable energy conversion efficiency, hybrid dc-dc switching converters are used. Hybrid dc-dc converters are combination of voltage multiplier/division circuit with appropriate SMPS circuits. By incorporating voltage multiplier/division cell with conventional SEPIC converters, desired voltage gain (either very low or very high) may be achieved at acceptable energy conversion efficiency. In the present work with an aim to attain very high voltage gain by conventional SEPIC topologies, a new voltage multiplier cell consisting of multiple inductors and diodes is proposed.

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32

Reaungepattanawiwat, Chalermpol, and Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter." Applied Mechanics and Materials 781 (August 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.

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This paper presents a high voltage gain of a DC-DC converter. The proposed system consists of voltage multiplier circuits and a coupled inductor of a boost DC-DC converter. The input voltage of the voltage multiplier circuit is the induced voltage of inductor at a boost DC-DC converter. The field programmable gate array (FGPA) is used for generating the control signal of the proposed system. To verify the proposed circuit, an experiment was conducted from the prototype circuit. The proposed circuit can step-up the voltage with high voltage gain. Moreover, the voltage across the switch is very low.

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33

Zhu, Wu, and Shui Xiu Guan. "Zero Error Analysis and Compensation of No-Beat Time Division Multiplier." Applied Mechanics and Materials 130-134 (October 2011): 3293–97. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.3293.

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Time division multiplier was widely used in high-precision industrial frequency AC power measurements.The poor stability of zero point was caused by the switch leakage and amplifier offset voltage. Based on the experimental study of the time division multiplier circuit designed in the article, the mathematical model of zero point compensation was established, and then the appropriate calibration method was proposed. Considered the amplifier offset voltage, the error model of the time division multiplier was analyzed and the error expression was obtained. These can provide theoretical guidance for choosing amplifiers of the no-beat time division multiplier.

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34

Павлов, Леонид Николаевич, and П. В. Кучернюк. "Network design of ultra low voltage multiplier." Electronics and Communications 20, no. 6 (May 30, 2016): 11–16. http://dx.doi.org/10.20535/2312-1807.2015.20.6.70063.

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35

Pavlov, Leonid Mykolaiovych, and Pavlo Valentynivych Kucherniuk. "Network design of ultra low voltage multiplier." Electronics and Communications 21, no. 1 (October 20, 2016): 11–17. http://dx.doi.org/10.20535/2312-1807.2016.21.1.80547.

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36

Iqbal, S. "A Three-Phase Symmetrical Multistage Voltage Multiplier." IEEE Power Electronics Letters 3, no. 1 (March 2005): 30–33. http://dx.doi.org/10.1109/lpel.2005.845174.

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37

Takamura, Yoshio, and Akira Nakajima. "Newly Developed Multi-Function Voltage Multiplier Circuits." IEEJ Transactions on Electronics, Information and Systems 108, no. 12 (1988): 965–72. http://dx.doi.org/10.1541/ieejeiss1987.108.12_965.

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38

Coban, A. L., and P. E. Allen. "Low-voltage, four-quadrant, analogue CMOS multiplier." Electronics Letters 30, no. 13 (June 23, 1994): 1044–45. http://dx.doi.org/10.1049/el:19940740.

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39

MOSHNYAGA, V. G. "Multiplier Energy Reduction by Dynamic Voltage Variation." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 12 (December 1, 2005): 3548–53. http://dx.doi.org/10.1093/ietfec/e88-a.12.3548.

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40

Satansup, Jetsdaporn, and Worapong Tangsrirat. "1.5-V CMOS Current Multiplier/Divider." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 3 (June 1, 2018): 1478. http://dx.doi.org/10.11591/ijece.v8i3.pp1478-1487.

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A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.

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41

Alsaleem, Abdulhakeem, Faleh Alsakran, and Marcelo Godoy Simões. "An Isolated High Voltage Boost Current-Fed DC–DC Converter Based on 1:1 Transformer Multiplier Cells and ZVS Operation." Electronics 9, no. 1 (January 6, 2020): 102. http://dx.doi.org/10.3390/electronics9010102.

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This paper presents a high step up, current fed, interleaved, isolated DC–DC converter with voltage multipliers and ZVS (zero voltage switching). The converter provides zero voltage switching for all active switches and provides a high step up voltage gain that is suitable for very low voltage source applications, such as PV and other renewable sources. In addition, this converter allows the utilization of very low voltage stress switches and diodes. It reduces the current stress by interleaving the input current, and reduces the voltage stress by utilizing a half bridge based multiplier cell integrated configuration at the output voltage while providing high frequency galvanic isolation. The isolation is achieved through the use of 1:1 transformers which are easier to design, and the need for a high turns ratio is absent in this converter. The main theory of operation and the design guideline are presented, as is a laboratory prototype, all to validate the concept.

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42

Ulyashin, Aleksander, and Aleksander Velichko. "Comparative analysis of analog parameters signal multi-pliers by differential transistor pairs." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 1 (February 25, 2021): 21–41. http://dx.doi.org/10.17212/2307-6879-2021-1-21-41.

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This paper is devoted to the comparative analysis of modern integral variables. Today, a number of foreign companies, such as Texas Instruments and Analog Devices, produce analog signal multipliers (APS) in integrated design. Russian industry produces chips of the 525PS and 174HA series. Each manufacturer uses its own method of implementing the device. The main task of such devices is to calculate the current voltage, phase, exponential and transcendental functions. Wide applicability of APS in integrated design was found in devices for analog processing and conversion of signals of communication and radio equipment, in devices for automatic control of onboard and ground radio equipment. A very important characteristic of such equipment is the dynamic range. The dynamic range of the receiver is the range of input signal amplitudes that provide the required quality of reproduction of the received message. The lower limit of the dynamic range is determined by the level of internal noise or external interference in the device, and the upper limit is determined by the device's overload capacity. In this regard, manufacturers of multipliers are faced with the task of maximizing the voltage that can be applied to its inputs. The difficulty is that the upper limit of the dynamic range is set by non-linear distortions. The non-linearity of the multiplier is a component of the multiplication error and characterizes the limiting capabilities of the APS inputs. In this paper, a comparative analysis of the main types of integral multipliers offered on the market is carried out in order to identify the best construction method for achieving the value of the dynamic range of the multiplier in 90 dB with high multiplication accuracy, which will allow using such a multiplier in modern radio equipment.

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Selvam, K. C. "A Circuit for the Square Root of the Sum of Two Squared Voltages using an IC LM311 Open Collector Comparator." Engineering, Technology & Applied Science Research 3, no. 6 (December 18, 2013): 549–51. http://dx.doi.org/10.48084/etasr.241.

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A circuit which accepts two input dc voltages V1 and V2 and provides an output dc voltage VO equal to the square root of the sum of the two squared voltages of V1 and V2, using an LM311 open collector comparator based single quadrant time division multiplier is described in this paper.

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44

Jaiwanglok, Anurak, Kei Eguchi, Krit Smerpitak, and Amphawan Julsereewong. "Modification of Cockcroft–Walton-Based High-Voltage Multipliers with 220 V and 50 Hz Input for Non-Thermal Food Processing Apparatus." Sustainability 12, no. 16 (August 6, 2020): 6330. http://dx.doi.org/10.3390/su12166330.

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A design of high-voltage multipliers to generate underwater shockwaves is one of the most important factors for successfully providing non-thermal food processing in a cost-effective manner. To be capable of fully utilizing the Cockcroft–Walton-based high-voltage multipliers for underwater shockwave generation, this paper presents a topological modification of three interesting design approaches in bipolar structure for 220 V and 50 Hz AC input to generate more than 3.5 kV DC output within short time periods. In addition to Cockcroft–Walton multipliers (CWMs), the first modified scheme employs a positive full-wave rectifier (FWR) and positive voltage multiplier block (VMB), the second modified scheme employs positive/negative half-wave rectifiers (HWRs), and the last modified scheme employs a switched-capacitor AC-AC converter. To comparatively analyze their performances, the digitally controlled operations of the modified realization schemes as well as their electrical characteristic estimation based on a four-terminal equivalent model are described in detail. The effectiveness of three modified circuit configurations and the correctness of the given theoretical analysis are verified through SPICE (Simulation Program with Integrated Circuit Emphasis) simulation results. The formulas achieved from theoretical estimation are particularly useful when designing the proposed high-voltage multipliers (HVMs) because good agreement between the theoretical and simulation results can be achieved.

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45

SAKUL, CHAIWAT, and KOBCHAI DEJHAN. "FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS." Journal of Circuits, Systems and Computers 21, no. 03 (May 2012): 1250024. http://dx.doi.org/10.1142/s0218126612500247.

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This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

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46

Prokop, Roman, Roman Sotner, and Vilem Kledrowetz. "The CMOS Highly Linear Current Amplifier with Current Controlled Gain for Sensor Measurement Applications." Sensors 20, no. 16 (August 18, 2020): 4653. http://dx.doi.org/10.3390/s20164653.

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This paper introduces a new current-controlled current-amplifier suitable for precise measurement applications. This amplifier was developed with strong emphasis on linearity leading to low total harmonic distortion (THD) of the output signal, and on linearity of the gain control. The presented circuit is characterized by low input and high output impedances. Current consumption is significantly smaller than with conventional quadratic current multipliers and is comparable in order to the maximum processed input current, which is ±200 µA. This circuit is supposed to be used in many sensor applications, as well as a precise current multiplier for general analog current signal processing. The presented amplifier (current multiplier) was designed by an uncommon topology based on linear sub-blocks using MOS transistors working in their linear region. The described circuit was designed and fabricated in a C035 I3T25 0.35-µm ON Semiconductor process because of the demand of the intended application for higher supply voltage. Nevertheless, the topology is suitable also for modern smaller CMOS technologies and lower supply voltages. The performance of the circuit was verified by laboratory measurement with parameters comparable to the Cadence simulation results and presented here.

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47

Nirlakalla, Ravi, Rao Subba, and Talari Jayachandra-Prasad. "Performance evaluation of high speed compressors for high speed multipliers." Serbian Journal of Electrical Engineering 8, no. 3 (2011): 293–306. http://dx.doi.org/10.2298/sjee1103293n.

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This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25?C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only.

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48

Murali, D., and S. Annapurani. "Improvement of Static Voltage Gain of a Non-Isolated Positive Output Single-Switch DC-DC Converter Structure Using a Diode-Capacitor Cell." Mathematical Modelling of Engineering Problems 8, no. 4 (August 31, 2021): 583–90. http://dx.doi.org/10.18280/mmep.080411.

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There are different low switching stress non-isolated DC-DC power converter structures developed for Photo-Voltaic (PV) applications with a view to achieve high voltage conversion ratio. The work proposed in this research article investigates the performance analysis of a coupled inductor and diode-capacitor multiplier cell based non-isolated high gain single-switch DC–DC conversion scheme with a single-ended primary-inductor on the input side. The presented converter suitable for renewable energy applications has the merits such as continuous input current, high voltage conversion ratio, and reduced voltage stress across the power switch. The multiplier cell consisting of two diodes and two capacitors is mainly used to enhance the converter output voltage level. A MATLAB / SIMULINK model of the suggested topology has been developed to validate its performance. During the simulation of the converter, a DC voltage of 50 V was given at the input side. The load end received a DC voltage of approximately 900 V. Thus, through this study, it was found that the addition of diode-capacitor cell can significantly improve the static gain of the suggested converter. The findings of this research may serve as a base for future studies on improvement of voltage gain of DC-DC converters.

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Sotner, Roman, Jan Jerabek, Norbert Herencsar, Jiun-Wei Horng, Kamil Vrba, and Tomas Dostal. "Simple Oscillator with Enlarged Tunability Range Based on ECCII and VGA Utilizing Commercially Available Analog Multiplier." Measurement Science Review 16, no. 2 (April 1, 2016): 35–41. http://dx.doi.org/10.1515/msr-2016-0006.

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Abstract This work presents an example of implementation of electronically controllable features to an originally unsuitable circuit structure of oscillator. Basic structure does not allow any electronic control and has mutually dependent condition of oscillation (CO) and frequency of oscillation (FO) if only values of passive elements are considered as the only way of control. Utilization of electronically controllable current conveyor of second generation (ECCII) brings control of CO independent of FO. Additional application of voltage amplifier with variable gain in both polarities (voltage-mode multiplier) to feedback loop allows also important enlargement of the range of the independent FO control. Moreover, our proposal was tested and confirmed experimentally with commercially available active elements (“Diamond transistor”, current-mode multiplier, voltage-mode multiplier) in working range of tens of MHz.

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50

Stala, R., S. Piróg, A. Penczek, A. Kawa, Z. Waradzyn, A. Mondzik, and A. Skała. "A family of high-power multilevel switched capacitor-based resonant DC-DC converters – operational parameters and novel concepts of topologies." Bulletin of the Polish Academy of Sciences Technical Sciences 65, no. 5 (October 1, 2017): 639–51. http://dx.doi.org/10.1515/bpasts-2017-0069.

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Abstract This paper presents the concept of topologies and investigation results of switched-capacitor voltage multipliers designed for application in high power systems. The analyzed family of multilevel converters includes established topologies as well as novel concepts. The application of thyristors as well as the invention of novel concepts of multiplier topologies and appropriate control make it possible to achieve high efficiency, high voltage gain, reliable and simple DC-DC converters for high power systems. Based on analytical models of the SCVMs, the paper presents a discussion of the selection of components and the efficiency of the converters as a function of converted power as well as the voltage range on the input and the output side. The results are supported by computer simulations and demonstrative experimental tests.

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