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1
Zhou, Xunwei. "Low-voltage High-efficiency Fast-transient Voltage regulator Module." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/28832.
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In order to meet demands for faster and more efficient data processing, modern microprocessors are being designed with lower voltage implementations. The processor voltage supply in future generation processors will decrease to 1.1 V ~ 1.8V. More devices will be packed on a single processor chip, and processors will operate at higher frequencies, beyond 1GHz. Therefore, microprocessors need aggressive power management. Future generation processors will draw current up to 50 A ~ 100 A [2]. These demands, in turn, will require special power supplies and Voltage Regulator Modules (VRMs) to provide lower voltages with higher currents and fast transient capabilities for microprocessors.
This work presents several low-voltage high-current VRM technologies for future generation data processing, communication, and portable applications. The developed advanced VRMs with these new technologies have advantages over conventional ones in power density, efficiency, transient response, reliability, and cost.
The multi-module interleaved quasi-square-wave VRM topology achieves a very fast transient response and a very high power density. This topology significantly reduces the filter inductance and capacitance, while having small output and input ripples. The analysis, design, and experimental verification for this new topology are presented in this work.
The current sensing and current sharing techniques are developed with simple and cost-effective implementations. With this technique, traditional current transformers and sensing resistors are not required, and the inductance value, MOSFET on resistance and other parasitics have no effect on current sharing results. The design principles are developed and experimentally verified. A generalized approach and an extension of the novel current sharing control are presented in this work.
The techniques for improving VRM light load efficiency are developed in this work. By utilizing the duty cycle signal, VRMs can be implemented with advanced power management functions to reduce further the power consumption at light loads to extend the battery-operation time in portable systems or to facilitate the compliance with various "energy star" ("green" power) requirements in office systems. Four improved approaches are presented and verified with experimental results.
The high-input-voltage VRM topology, push-pull forward converter, can be used in high-bus-voltage distributed power systems. This converter has a high efficiency, a high power density, a fast transient response, and can be easily packaged as a standard module. The circuit design and experimental evaluation are addressed to demonstrate the operation principles and advantages of this topology.Ph. D.
2
Park, Yongwan. "Fully Integrated Hybrid Voltage Regulator for Low Voltage Applications." Thesis, State University of New York at Stony Brook, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10132969.
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A novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed topology targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 10% of the output voltage) and power density. The first implementation of the proposed topology operates in a single frequency mode. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm2. This single-frequency hybrid voltage regulator is useful (due to its fast and continuous response and high power efficiency) when the output load current is relatively constant at a certain nominal value. However, the performance is degraded when the load current varies significantly beyond the nominal current since the current provided by switched-capacitor converter is constant. The second implementation of the proposed hybrid regulator topology partially alleviates this issue by employing two different frequencies depending on the load current. This design is also implemented in 45 nm technology. It is demonstrated that the power efficiency is maintained within 60% to 80% even though the load current varies by more than 100 mA. The power density remains the same (0.5 W/mm2). The simulation results of the proposed topology are highly competitive with recent work on integrated voltage regulators.
3
Nghe, Brandon K. "Cascaded Linear Regulator with Positive Voltage Tracking Switching Regulator." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2173.
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This thesis presents the design, simulation, and hardware implementation of a proposed method for improving efficiency of voltage regulator. Typically, voltage regulator used for noise-sensitive and low-power applications involves the use of a linear regulator due to its high power-supply rejection ratio properties. However, the efficiency of a linear regulator depends heavily on the difference between its input voltage and output voltage. A larger voltage difference across the linear regulator results in higher losses. Therefore, reducing the voltage difference is the key in increasing regulator’s efficiency. In this thesis, a pre switching regulator stage with positive voltage tracking cascaded to a linear regulator is proposed to provide an input voltage to a linear regulator that is slightly above the output of the linear regulator. The tracking capability is needed to provide the flexibility in having different positive output voltage levels while maintaining high overall regulator’s efficiency. Results from simulation and hardware implementation of the proposed system showed efficiency improvement of up to 23% in cases where an adjustable output voltage is necessary. Load regulation performance of the proposed method was also overall better compared to the case without the output voltage tracking method.
4
Lei, Ernest. "Cascaded Linear Regulator with Negative Voltage Tracking Switching Regulator." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2176.
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DC-DC converters can be separated into two main groups: switching converters and linear regulators. Linear regulators such as Low Dropout Regulators (LDOs) are straightforward to implement and have a very stable output with low voltage ripple. However, the efficiency of an LDO can fluctuate greatly, as the power dissipation is a function of the device’s input and output. On the other hand, a switching regulator uses a switch to regulate energy levels. These types of regulators are more versatile when a larger change of voltage is needed, as efficiency is relatively stable across larger steps of voltages. However, switching regulators tend to have a larger output voltage ripple, which can be an issue for sensitive systems. An approach to utilize both in cascaded configuration while providing a negative output voltage will be presented in this paper. The proposed two-stage conversion system consists of a switching pre-regulator that can track the negative output voltage of the second stage (LDO) such that the difference between input and output voltages is always kept small under varying output voltage while maintaining the high overall conversion efficiency. Computer simulation and hardware results demonstrate that the proposed system can track the negative output voltage well. Additionally, the results show that the proposed system can provide and maintain good overall efficiency, load regulation, and output voltage ripple across a wide range of outputs.
5
Komark, Stina. "Design of an integrated voltage regulator." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1711.
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Many analog systems need a stable power supply voltage that does not vary with temperature and time in order to operate properly. In a battery operated system the battery voltage is not stable, e.g. it decreases with decreasing temperature and with ageing. In that case a voltage regulator must be used, that regulates the battery voltage and generates a stable supply voltage to power other circuitry.
In this thesis a voltage regulator to be used in a battery operated system has been designed which meets the given specification of stability and power capabilities. A voltage reference, which is a commonly used devise in analog circuits, was also designed. The role of a reference voltage in an electrical system is the same as for a tuning fork in a musical ensemble; to set a standard to which other voltages are compared.
A functionality to detect when the lifetime of the battery is about to run out was also developed.
6
Serdyn, J. J. "Electronic voltage regulator technology for rural electrification." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/903.
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Quintero, Francisco Javier 1955. "Analysis of an integrated voltage regulator amplifier and design alternatives." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276753.
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This Thesis Research involves the analysis, simulation and design alternatives for an industrially-relevant voltage regulator. An initial prototype circuit, designed by Texas Instruments Inc., is simulated and analysed in detail. Then an alternative circuit is derived which improves the circuit performance by implementing different compensation techniques and some transistors modifications. The final circuit has excellent phase margin, transient response and load regulation.
8
Low, Aichen. "A floating-gate low dropout voltage regulator." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14886.
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Westlund, Arvid, and Oskar Bernberg. "Efficient Energy Transfer for Wireless Devices." Thesis, Uppsala universitet, Fasta tillståndets elektronik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-177255.
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This project is intended to findsuitable circuit architecture forefficient power transmission where thepower supply is low.Two circuits will be built. The firstwill receive high AC which correspondsto the voltage created in a piezoelement once subjected to stress fromfoot steps It will deliver 3.3DC.The second circuit will receive low ACwhich will represent voltage receivedfrom a wireless transfer.Due to a failing high voltage powersupply the second circuit was never putto practice. The idea was to send a wavefile through an OP-amplifier to simulatethe voltage from the piezo element. Thevoltage was then rectified and convertedto 3.3DC.Circuit 2 was tested with a frequencygenerator as power supply. The voltagewas transformed, rectified and at lastconverted to 3.3DC through a voltageregulator. Due to lack of deliveredpower from the frequency generator itwas necessary to duty cycle the load tolimit the power dissipation.The power dissipation in the voltageregulator was limited as well byswitching it on and off. When switchedoff a capacitor was charged. When in onmode the capacitor was emptied into thevoltage regulator.Det här projektet är ämnat att hittalämpliga kretsarkitetkturer för braeffektöverföring där energikällorna ärmycket begränsade.Två kretsar ska byggas. Den första skata emot hög växelspänning motsvarandespänningen som uppkommer i ettpiezoelement vilket utsätts för växlandetryck. I det här fallet trycket från enmänniskas fotsteg. Kretsen ska leverera3.3V likspänning.Den andra kretsen ska ta emot en lågväxelspänning, vilken motsvarar spänningfrån en trådlös överföring, och leverera3.3V.Krets 1 blev aldrig testad på grund avett fallerande högspänningsaggregat.Genom att skicka en wav-fil genom en OPförstärkareskulle en simulerad spänningfrån piezoelementet användas. Därefterskulle spänningen likriktas ochkonverteras ner till 3.3V.Krets 2 testades med en signalgeneratorsom spänningskälla. Spänningentransformerades först upp innan denlikriktades och skickades in i enspänningsreglator för att därefter ge ut3.3V. Med en liten levererad effekt frånsignalgeneratorn var det nödvändigt attbegränsa effektåtgången i lasten genompulsbreddmodulering. Effektåtgången ispänningsreglatorn begränsades ocksågenom att stänga av och på IC:n(spänningsregulatorn). När IC:n varavstängd laddades en kondensator upp somsedan tömdes i IC:n då den aktiveradesigen.
10
Xiao, Shangyang. "TRANSIENT RESPONSE IMPROVEMENT FOR MULTI-PHASE VOLTAGE REGULATORS." Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3909.
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Next generation microprocessor (Vcore) requirements for high current slew rates and fast transient response together with low output voltage have posed great challenges on voltage regulator (VR) design . Since the debut of Intel 80X86 series, CPUs have greatly improved in performance with a dramatic increase on power consumption. According to the latest Intel VR11 design guidelines , the operational current may ramp up to 140A with typical voltages in the 1.1V to 1.4V range, while the slew rate of the transient current can be as high as 1.9A/ns [1, 2]. Meanwhile, the transient-response requirements are becoming stringer and stringer. This dissertation presents several topics on how to improve transient response for multi-phase voltage regulators. The Adaptive Modulation Control (AMC) is a type of non-linear control method which has proven to be effective in achieving high bandwidth designs as well as stabilizing the control loop during large load transients. It adaptively adjusts control bandwidth by changing the modulation gain, depending on different load conditions. With the AMC, a multiphase voltage regulator can be designed with an aggressively high bandwidth. When in heavy load transients where the loop could be potentially unstable, the bandwidth is lowered. Therefore, the AMC provides an optimal means for robust high-bandwidth design with excellent transient performance. The Error Amplifier Voltage Positioning (EAVP) is proposed to improve transient response by removing undesired spikes and dips after initial transient response. The EAVP works only in a short period of time during transient events without modifying the power stage and changing the control loop gain. It facilitates the error amplifier voltage recovering during transient events, achieving a fast settling time without impact on the whole control loop. Coupled inductors are an emerging topology for computing power supplies as VRs with coupled inductors show dynamic and steady-state advantages over traditional VRs. This dissertation first covers the coupling mechanism in terms of both electrical and reluctance modeling. Since the magnetizing inductance plays an important role in the coupled-inductor operation, a unified State-Space Averaging model is then built for a two-phase coupled-inductor voltage regulator. The DC solutions of the phase currents are derived in order to show the impact of the magnetizing inductance on phase current balancing. A small signal model is obtained based on the state-space-averaging model. The effects of magnetizing inductance on dynamic performance are presented. The limitations of conventional DCR current-sensing for coupled inductors are addressed. Traditional inductor DCR current sensing topology and prior arts fail to extract phase currents for coupled inductors. Two new DCR current sensing topologies for coupled inductors are presented in this dissertation. By implementation of simple RC networks, the proposed topologies can preserve the coupling effect between phases. As a result, accurate phase inductor currents and total current can be sensed, resulting in excellent current and voltage regulation. While coupled-inductor topologies are showing advantages in transient response and are becoming industry practices, they are suffering from low steady-state operating efficiency. Motivated by the challenging transient and efficiency requirements, this dissertation proposes a Full Bridge Coupled Inductor (FBCI) scheme which is able to improve transient response as well as savor high efficiency at (a) steady state. The FBCI can change the circuit configuration under different operational conditions. Its "flexible" topology is able to optimize both transient response and steady-state efficiency. The flexible core configuration makes implementation easy and clear of IP issues. A novel design methodology for planar magnetics based on numerical analysis of electromagnetic fields is offered and successfully applied to the design of low-voltage high power density dc-dc converters. The design methodology features intense use of FEM simulation. The design issues of planar magnetics, including loss mechanism in copper and core, winding design on PCB, core selections, winding arrangements and so on are first reviewed. After that, FEM simulators are introduced to numerically compute the core loss and winding loss. Consequently, a software platform for magnetics design is established, and optimized magnetics can then be achieved. Dynamic voltage scaling (DVS) technology is a common industry practice in optimizing power consumption of microprocessors by dynamically altering the supply voltage under different operational modes, while maintaining the performance requirements. During DVS operation, it is desirable to position the output voltage to a new level commanded by the microprocessor (CPU) with minimum delay. However, voltage deviation and slow settling time usually exist due to large output capacitance and compensation delay in voltage regulators. Although optimal DVS can be achieved by modifying the output capacitance and compensation, this method is limited by constraints from stringent static and dynamic requirements. In this dissertation, the effects of output capacitance and compensation network on DVS operation are discussed in detail. An active compensator scheme is then proposed to ensure smooth transition of the output voltage without change of power stage and compensation during DVS. Simulation and experimental results are included to demonstrate the effectiveness of the proposed scheme.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
11
Wei, Jia. "Investigation of High-Input-Voltage Non-Isolated Voltage Regulator Modules Topology Candidates." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/32482.
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Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM), is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us.
This work presents an investigation of three 12V VRM topologies: the synchronous buck converter, the tapped-inductor buck converter and the active-clamp couple-buck converter. The limitations of today¡¯s synchronous buck approach are identified. The extreme duty cycle of the current topology makes it difficult to design an efficient VRM with decent transient response.
The tapped-inductor buck and the active-clamp couple-buck converters are discussed as solutions. The transient response and efficiency of each type of converter are compared. Ripple cancellation is also addressed. The analytical and experimental results are presented: The tapped-inductor buck can improve the efficiency, but suffers a voltage spike, which nullifies its candidacy; the active-clamp couple-buck converter can improve the efficiency while maintaining good transient response, and it is therefore a good candidate for 12V VRMs.Master of Science
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Abrie, Dewald Johan. "Supervisory control and sliding mode control of a medium voltage direct AC-AC electronic voltage regulator." Thesis, Stellenbosch : Stellenbosch University, 2013. http://hdl.handle.net/10019.1/80166.
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Thesis (MScEng)--Stellenbosch University, 2013.ENGLISH ABSTRACT: As control problems become more and more complex, techniques are required that surpass the capabilities of simple controllers that are linearized about certain parametric set points. Controllers that can operate over a large range of model parameter variations and even controllers that are largely model-independent are becoming more valuable and necessary. In this control application, voltage regulation is done on a direct AC-AC medium voltage regulator, making use of a type of regulated autotransformer configuration. The fifth order system is shown to be prone to oscillations on the input bus. This, together with the control requirement of robustness to load variations, provides a challenging control problem that is rarely addressed in literature. This thesis solves the control problem by means of applying sliding mode control on voltage regulator module level, and supervisory control on system level.
AFRIKAANSE OPSOMMING: Soos die soeke na oplossings vir hedendaagse beheer probleme al hoe meer uitdagend raak, word die behoefte vir model onafhanklike en robuuste beheerders dienooreenkomstig groter. Eenvoudige beheerders wat gelineariseer is om ’n parametriese werkpunt raak ondoeltreffend vir vandag se vereistes vir doeltreffende beheer ongeag van parametriese veranderinge. In hierdie tesis word spanning regulasie toegepas deur ’n direkte WS-na-WS medium spanning reguleerder in te span. Hierdie toestel maak gebruik van ’n tipe van outotransformator opstelling waar die sekondêre wikkelings gereguleer word deur die skakelaksie van die drywingselektroniese regulasie modules. Die vyfde-orde stelsel se intree bus is geneigd om onstabiel te raak, en moet dus aktief gedemp word terwyl die uitreespanning reguleer word. Die vereiste dat die beheer boonop robuus ten opsigte van las veranderings moet wees maak hierdie probleem ’n monster van ’n uitdaging wat skaars in die literatuur aangeraak is. Hierdie tesis los die probleem van robuuste beheer op deur glymodus beheer toe te pas op reguleerder module vlak, en ook deur toesighoudende beheer op stelsel vlak toe te pas.
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Haskell, Timothy David. "Modeling and Analysis of a Dynamic Voltage Regulator." DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/987.
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Increased government funding and incentives in recent years has led to an increase in the number of grid-tied renewable energy sources as their economic benefits become more renowned. Unfortunately, the outputs of these renewable resources are often highly variable, resulting in undesirable voltage disruptions that are harmful to sensitive loads. In addition to the energy variability of renewable energy sources, random voltage sags, swells and disruptions are already a major issue in power systems. Recent advances in power electronic devices have provided a platform for new solutions to the voltage support problem in power systems. One promising solution is the Dynamic Voltage Regulator (DVR), a series compensating device used to protect a sensitive load that is connected downstream from voltage sag or swell. For this thesis, the design, modeling, and analysis of a DVR system were performed using PSCAD software. Results from simulation demonstrate the DVR’s effectiveness in protecting a sensitive load from load and source side voltage disturbances as well as regulate the load bus voltage to its rated value.
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Ahmed, Khondker Zakir. "Low voltage autonomous buck-boost regulator for wide input energy harvesting." Thesis, Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53604.
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While high power buck-boost regulators have been extensively researched and
developed in the academia and industry, low power counterparts have only recently gained
momentum due to the advent of different battery powered and remote electronics. The
application life-time of such applications, e.g., remote surveillance electronics can be
extended tremendously by enabling energy autonomy. While battery powered electronics
last long but they must be replenished once the battery is depleted either by replacing the
battery or by retrieving the electronics and then recharging. Instead, energy harvesting from
available ambient sources on the spot will enable these electronics continuous operation
unboundedly, probably even beyond the lifetime of the electronics. Interestingly enough,
recent advancements in micro-scale energy transducers compliment these demand [1-13].
Micro-transducers producing energy from different ambient sources have been reported.
These transducers produce enough energy to support a wide range of operations of the
remote electronics concurrently. These transducers along with an additional storage
elements greatly increase the energy autonomy as well as guaranteed operation since
harvested energy can then be stored for future use when harvestable energy is temporarily
unavailable.
Recently several buck-boost regulators with low power and low input operating
voltage have been reported both from academia and industry [14-24]. Some of this work
focuses on increasing efficiency in the mid-load range (10mA-100mA), while some other
focuses on lowering input range. However, so far no one has reported a buck-boost
regulator operating with sub-200nW bias power while harvesting energy from sub-500mV input range. This work focuses on the development of a low voltage low bias current buckboost regulator to attain these goals.
In this work, complete design of a PFM mode buck-boost regulator has been
discussed in details. Basic topology of the regulator and working principle of the
implemented architecture along with the advantages of the specific topology over that of
the others have been discussed in short to provide an uninterrupted flow of idea. Later,
Transistor level design of the basic building blocks of the buck-boost regulator is discussed
in details with different design features and how those are attained through transistor level
implementation are discussed. Subsequently, the physical layout design technique and
considerations are discussed to inform the reader about the importance of the layout process
and to avoid pitfalls of design failure due to layout quality issues.
Measurement results are presented with the fabricated IC. Different
characterization profile of the IC have been discussed with measured data and capture
oscilloscope waveforms. Load regulation, line regulation, efficiency, start-up from low
voltage, regulation with line and load transient events are measured, presented and
discussed. Different characteristics of the prototype are compared with prior arts and are
presented in a comparison table. Die micrograph is also presented along with the different
issue of the IC testing
15
Woodworth, Ronald Keith. "THE DYNAMIC THERMAL ANALYSIS OF A VOLTAGE REGULATOR CIRCUIT." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275365.
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Harris, Cory Angelo. "Operation of buck regulator with ultra-low input voltage." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91825.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 101-102).
Based on the LTC3621 and LTC3624, the designed buck regulator proposed in this thesis aims to lower the allowed input voltage and increase efficiency compared to the original part without making significant changes to quiescent current and part performance. This thesis will discuss additions and modifications made to the original afformentioned parts in order to achieve said goal. This thesis will provide an in depth analysis through simulations of the results of the changes made and a comparison of performance between the original and the redisigned part.
by Cory Angelo Harris.
M. Eng.
17
Lai, Pengjie. "Improvement of Sigma Voltage Regulator - A New Power Architecture." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/31412.
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With lower output voltage (lower than 1V) and higher output current (more than 160A) required in the near future, the voltage regulators for the microprocessors, a kind of special power supplies are facing more and more critical challenges to achieve high efficiency and high power density. 90% plus efficiency for CPU VRs is expected from industry not only for the thermal management, but also for saving on electricity costs, especially for the large data-center systems. At the same time, high power density VRs are also desired due to the increasing power consumption of microprocessors as well as the precious space on CPU motherboard.
Current multi-phase Buck VR has its limitation to achieve 90% plus efficiency. With the state of art devices, the single-stage 12V/1.2V 600kHz Buck VR achieves 85% to 86% efficiency at full load condition. In addition, for the future lower output voltage application, the Buck efficiency will drop another 3~4% due to the extreme small duty cycle. From the power density point of view, due to the switching frequency limitation (normally, from 300 kHz to 600 kHz for typical CPU VRs) for acceptable efficiency performance, the multi-phase Buck VR is unable to ensure a small size since it needs bulky output capacitors to meet the challenging transient requirement as well as the output impedance requirement with relatively low bandwidth design.
To attain high efficiency and high power density at the same time, in-series two-stage power architecture was proposed. By cutting the single stage into two and utilizing the low voltage devices, the in-series two stages can achieve around 87% efficiency which is similar as single stage with second-stage operating at 1 MHz for less cost. Compared with the in-series one, the other two-stage power architecture is called â Sigmaâ architecture which is composed by an unregulated converter (DCX) and a regulated buck converter, with a special connection where the inputs are in series while outputs are paralleled. Through this topology, unlike the in-series two-stage where both two stages deliver the full load power, the power will be distributed between unregulated DCX and regulated Buck. If the unregulated DCX can achieve high efficiency, let most power be handled by it and just small power from buck, the Sigma architecture can achieve high efficiency performance based on this concept.
The design consideration and process had been investigated by CPES previous graduates. By the designed 1.2V/120A Sigma VR circuit, approaching 90% efficiency was achieved which is around 3~4% efficiency higher than state of the art multi-phase Buck VR. However, it is not the optimal design for best efficiency performance, the improvement methods for higher efficiency is deeply considered and the efficiency potential benefit of this special structure will be clarified in this thesis. Besides the efficiency interest, transient performance of Sigma VR is also a challenging issue needed to be addressed. The state of the art Buck VR needs a bunch of output bulk capacitors to meet the stringent output impedance requirement from Intel and those output bulk capacitors occupy too much space in the motherboard. For Sigma architecture, through the help of the low impedance DCX which can achieve faster current dynamic response, some low voltage bulk capacitors could be replaced by smaller input high voltage capacitors. It is still not clear for us to identify how input capacitor impacts the DCX dynamic current response and how to best choose this impact factor.
This thesis will investigate the faster DCX dynamic current performance of Sigma VR, and explain the dynamic impacts from input capacitors, from control design and from DCX impedance Lout. The high voltage capacitors could provide energy through low impedance DCX to deal with the transient load with smaller capacitance, resulting less total cost and footprint with conventional Buck solution. Low impedance DCX is also a desire for achieving fast current response for providing a â non-obstacleâ path when energy transferring from input capacitors. The control also has the impact to the DCX current response when the bandwidth is higher than certain frequency. The transient benefit will also be discussed from impedance perspective.
In order to improve the efficiency and power density of Sigma VR, several methods are proposed. As a critical component of DCX, the transformer design determines the performance of Sigma VR both to efficiency and power density. By optimizing the transformer design to achieve lower winding loss and smaller leakage inductance, the higher efficiency and faster transient DCX can be obtained. Changing the output capacitors to ceramic ones is helpful when control bandwidth is greater than 100 kHz for both lower cost and smaller footprint. Continually pushing bandwidth can reduce the required output ceramic capacitor number further. In addition, from the study of the loss breakdown, by adjusting the energy ratio of DCX and Buck can achieve higher efficiency based on current device level. What is more, with the same simple concept of adjusting power ratio of DCX and Buck, with the development of devices in the future as well as higher efficiency DCX, Sigma architecture will be more attractive for futureâ s lower output voltage VR application. And it will also be more efficient considering higher than 12V input bus voltage by letting high efficiency DCX handle more power. Utilizing this characteristic, changing the power system delivery architecture from AC input to the microprocessors, the end to end efficiency could be improved.Master of Science
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Sun, Yi. "Modeling and Design of Digitially Controlled Voltage Regulator Modules." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/36447.
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It can be expected that digital controllers will be increasingly used in low voltage, high-current and high frequency voltage regulator modules (VRMs) where conventional analog controllers are currently preferred because of the cost and performace reasons. However, there are still remaining two significant challenges for the spread of the digital control techniques: quantization effects and the delay effects.
Quantization effects might introduce the limit cycle oscillations (LCOs) to the converter, which will generate the stability issues. Actually, LCOs can not be totally eliminated theoretically. One way to reduce the possibilities of LCOs is to employ a high resolution Digital Pulse-Width-Modulator (DPWM). However, designing such a DPWM which can meet the requirements of VRMs application requires ultra-high system clock frequency, up to several GHz. Such high frequency is impractical due to huge power consumption. Hybrid DPWM might be an alternative solution but will occupy large silicon area. Single phase digital constant on-time modulation method is another good candidate to improve the DPWM resolution without adding too much cost. However, directly extending this method to multi-phase application, which is the prevalent structure in VRMs application, will introduce some issues. With more phases in parallel, the duty cycle resolution will drop more.
To solove the mentioned issue, this work proposed a multi-phase digital constant on-time modulation method. The proposed method will control the control voltage to alternate between two adjacent values, or dither, within one switching period. The outcome is that the phase duty cycleâ s resolution is improved and independent on phase number. Compared with conventional constant frequency modulation method, the proposed method can achieve about 10 times higher duty cycle resolution for the VRM application. The effectiveness of the proposed method is verified by the simulation as well as the experiment results.
Delay effect is another concern for the digital controlled VRMs. There exist several types of delays in the digital feedback loop, including the ADC conversion delay, digital compensator calculation delay, DPWM delay as well as some propagation delays. Usually these delays are inside the digital controller and it is hard to know the exact values. There are several papers talking about the small signal models of the digital voltage mode control. These models are valid only if all the delay terms are known exactly since each delay is considered separately. Actually, this process is not easy. Moreover, there is no literature talking about the complete small signal model of the digital VRMs. But in reallity, different implementations of the sampling process will give different impacts to the loop.
This work proposed the small signal signal models of digital VRMs. The analysis is based on the assumptions that DPWM is a double-edge modulation and the sampling instants are aligned with the middle of one phaseâ s off time. At first, the conversion and calculation delay is neglected. The focus of the modeling is on the small signal model of the current sampling methods and the DPWM delay. This model is valid for those digital controllers which have fast ADC and fast calculation capabilities. It is shown that even with a â fastâ controller, the current sampling and DPWM might introduce some delay to the loop.
After that, the conversion and calculation delay are considered into the modeling. Two time periods, T1ff and T1rr, are employed to describe the total delay effects in the control loop. It is observed that the total delay in the loop is integral times of sampling periods, which is never reported by any other literatures. Therefore, the proposed model only includes one delay term and the value of this delay can be found through a pre-determined lookup table. Finally, the complete small signal model of the digital VRMs considering the conversion and calculation delay is proposed. This model is helpful for the researchers to find the delay effects in their control loop based on the range of the total physical delay in the controller.
With the derived small signal mondels of digital VRMs, the design guildeline for AVP control are presented. The digital active-droop control is employed and it borrows the concept of constant output impedance control from the analog world. Two design examples are provided for the verification.Master of Science
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Jeong, Timothy. "Zero Voltage Switching Hybrid Voltage Divider Converter." DigitalCommons@CalPoly, 2021. https://digitalcommons.calpoly.edu/theses/2290.
Full textAbstract:
This project proposes a new hybrid voltage divider DC-DC converter that utilizes switching capacitors and inductors to produce zero voltage switching (ZVS) at the turn on state of its switches. By achieving ZVS, the switching losses are significantly reduced; thus, increasing the overall efficiency of the converter at various loads. The goal for this thesis is to perform analysis of the operation of the converter, derive equations for sizing the main components, and demonstrate its functionality through computer simulation and hardware prototype. Results of the simulation and hardware testing show that the proposed converter produces the desired output voltage while providing the zero voltage switching benefits. The converter’s efficiency reaches above 92% starting from 1A load and continues to increase to 97.6% at 4A load. Overall, results from this thesis verifies the potential of the proposed converter as an alternative solution to achieve a very efficient DC-DC solution when half of the input voltage is required at the output without the use of complex feedback control circuitry.
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Chewele, Youngie Klyv. "Model predictive control of AC-to-AC converter voltage regulator." Thesis, Stellenbosch : Stellenbosch University, 2014. http://hdl.handle.net/10019.1/86339.
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Thesis (MEng)--Stellenbosch University, 2014.ENGLISH ABSTRACT: The development of fast and efficient processors, programmable devices and high power semiconductors has led to the increased use of semiconductors directly in the power supply path in order to achieve strict power quality standards. New and advanced algorithms are used in the process and calculated on-line to bring about the required fast response to voltage variations. Losses in high voltage semiconductors increase with increased operating frequencies. A balance between semiconductor power losses and power quality is achieved through control of power semiconductor switching frequencies. A predictive control algorithm to achieve high power quality and limit the power losses in the high power semiconductor switches through switching frequency control is discussed for a tap switched voltage regulator. The quality of power, voltage regulator topology and the control algorithm are discussed. Simulation results of output voltage and current are shown when the control algorithm is used to control the regulator. These results are verified by practical measurements on a synchronous buck converter.
AFRIKAANSE OPSOMMING: Die ontwikkeling van vinnige en doeltreffende verwerkers, programmeerbare toestelle en hoëdrywings halfgeleiers het gelei tot 'n groter gebruik van halfgeleiers direk in die kragtoevoer pad om streng elektriese toevoer kwaliteit standaarde te bereik. Nuwe en gevorderde algoritmes word gebruik in die proses en word aan-lyn bereken om die nodige vinnige reaksie tot spanningswisselinge te gee. Verliese in hoë-spannings halfgeleiers verhoog met hoër skakel frekwensies. 'n Balans tussen die halfgeleier drywingsverliese en spanningskwalteit is behaal deur die skakel frekwensie in ag te neem in die beheer. 'n Voorspellinde-beheer algoritme om ‘n hoë toevoerkwaliteit te bereik en die drywingsverliese in die hoëdrywingshalfgeleier te beperk, deur skakel frekwensie te beheer, is bespreek vir 'n tap-geskakelde spanning reguleerder. Die toevoerkwaliteit, spanningsreguleerder topologie en die beheer algoritme word bespreek. Simulasie resultate van die uittree-spanning en stroom word getoon wanneer die beheer algoritme gebruik word om die omsetter te beheer. Hierdie resultate is deur praktiese metings op 'n sinkrone afkapper.
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Gu, Wei. "Low voltage regulator modules and single stage front-end converters." Doctoral diss., University of Central Florida, 2001. http://digital.library.ucf.edu/cdm/ref/collection/RTD/id/10000.
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University of Central Florida College of Engineering ThesisEvolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding IGHz. New high performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/us slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response.
Ph.D.
Doctorate;
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering and Computer Science
124 p.
xii, 124 leaves, bound : ill. ; 28 cm.
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Xu, Peng. "Multiphase Voltage Regulator Modules with Magnetic Integration to Power Microprocessors." Diss., Virginia Tech, 2002. http://hdl.handle.net/10919/26395.
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Advances in very large scale integration (VLSI) technologies impose challenges for voltage regulator modules (VRM) to deliver high-quality power to modern microprocessors. As an enabling technology, multiphase converters have become the standard practice in VRM industry. The primary objectives of this dissertation are to develop advanced topologies and innovative integrated magnetics for high-efficiency, high-power-density and fast-transient VRMs. The optimization of multiphase VRMs has also been addressed.
Todayâ s multiphase VRMs are almost universally based on the buck topology. With increased input voltage and decreased output voltage, the multiphase buck converter suffers from a very small duty cycle and cannot achieve a desirable efficiency. The multiphase tapped-inductor buck converter is one of the simplest topologies with a decent duty cycle. However, the leakage inductance of its tapped inductors causes a severe voltage spike problem. An improved topology, named the multiphase coupled-buck converter, is proposed. This innovative topology enables the use of a larger duty cycle with clamped device voltage and recovered leakage energy. Under the same transient responses, the multiphase coupled-buck converter has a significantly better efficiency than the multiphase buck converter.
By integrating all the magnetic components into a single core, in which the windings are wound around the center leg and the air gaps are placed on the two outer legs, it is possible for multiphase VRMs to further improve efficiency and cut the size and cost. Unfortunately, this structure suffers from an undesirable core structure and huge leakage inductance. An improved integrated magnetic structure is proposed to overcome these limitations. All the windings are wound around the two outer legs and the air gap is placed on the center leg. The improved structure also features the flux ripple cancellation in the center leg and strongly reverse-coupled inductors. Both core loss and winding loss are reduced. The steady-state current ripples can be reduced without compromising the transient responses. The overall efficiency of the converter is improved. The input inductor can also be integrated in the improved integrated magnetic structure.
Currently, selecting the appropriate number of channels for multiphase VRMs is still an empirical trial-and-error process. This dissertation proposes a methodology for determining the right number of channels for the optimal multiphase design. The problem formulation and general method for the optimization are proposed. Two examples are performed step by step to demonstrate the proposed optimization methodology. Both are focused on typical VRM 9.0 designs for the latest Pentium 4® microprocessors and their results are compared with the industry practice.Ph. D.
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Zhou, Jinghai. "High Frequency, High Current Density Voltage Regulators." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/27268.
Full textAbstract:
As a very special DC-DC converter, VRM (Voltage Regulator Module) design must follow the fast-developing trend of microprocessors. The design challenges are the high current, high di/dt, and stringent load-line requirement. When the energy is transferred from the input of a VRM, through the VRM, then through the power delivery path to the processor, it needs sufficient capacitors to relay this energy. The capacitorsâ number appears to be unrealistically large if we follow todayâ s approach for the future processors. High frequency VRM with high control bandwidth can solve this problem, however, the degradation of efficiency makes the conventional buck converter and the hard-switching isolated topologies incapable of operating at higher frequency. The research goal is to develop novel means that can help a high-output- current VRM run efficiently at high frequency.
A novel Complementary Controlled Bridge (CCB) self-driven concept is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and the self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary- side synchronous rectifier (SR) as the snubber capacitor of the primary-side switches. Compared to the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared to the existing level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal ringing is small and suitable for high-frequency applications.
Although the CCB self-driven VRM reduces the switching frequency-related losses significantly, the conduction loss is still high. Inspired by the current-doubler concept, a novel ZVS current-tripler DC-DC converter is proposed in this work. By utilizing more SR devices to share the current during the freewheeling period, the SR conduction loss is reduced. The current-tripler DC-DC converter has a delta/delta connected transformer that can be implemented with integrated magnetics. The transformer then becomes an integrated magnetic with distributed windings, which is preferred in high current applications. The current-tripler DC-DC converter in fact meets the requirements for the CCB self-driven scheme. The two concepts are then combined with an integrated gate drive transformer.
The proposed CCB self-driven concept and current-tripler concept can both be applied to the 12V non-isolated VRMs. The proposed topology is basically a buck-derived soft-switching topology with duty cycle extension and SR device self-driven capabilities. Because there is no isolation requirement, the SR gate driving becomes so simple that the voltage at the complementary controlled bridge can be used to directly drive the SR gate. Both the gate driving loss and the SR body diode conduction loss are reduced. The proposed circuit achieves similar overall efficiency to a conventional 300kHz buck converter running at 1MHz.
All the circuits proposed in this dissertation can use coupling inductors to improve both the steady-state efficiency and dynamic performances. The essence of the coupling inductors concept is to provide different equivalent inductances for the steady state and the transient. Moreover, when a current loop becomes necessary to achieve proper current sharing among phases, the current loop sample hold effect will make it difficult to push the bandwidth. The sample hold effect is alleviated by the coupling inductors concept. A small-signal model is proposed to study the system dynamic performance difference with different coupling inductor designs. As the verification, the coupling concept is applied to the 12V non-isolated CCB self-driven VRM and the bandwidth as high as one third of the switching frequency is achieved, which means a significant output capacitor reduction.Ph. D.
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Wei, Jia. "High Frequency High-Efficiency Voltage Regulators for Future Microprocessors." Diss., Virginia Tech, 2004. http://hdl.handle.net/10919/11254.
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Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. At first, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. For laptop application, the VR input voltage range covers the battery voltage range and the adaptor voltage. In the meantime, microprocessors will run at very low voltage (sub 1V), and will consume up to 150A of current, and will have dynamics of about 400A/us.
The current VR solution is the 12V-input multiphase interleaved buck converter. The switching frequency is around 300KHz. This approach has several limitations for the future. OSCON capacitor is one limitation due to its large ESR and ESL; the low switching frequency the second limitation and the large inductance is the third limitation. Analysis shows that the all-ceramic solution is a better solution than the OSCON solution when the VR switching frequency reaches 1MHz. However, the 12V-input multiphase buck converter suffers low efficiency at high switching frequency, which rules out a legitimate chance of the current VR topology benefiting from high switching frequency.
The extreme duty cycle is the fundamental reason why the 12V-input multiphase buck converter is not suitable for future VRs. Employing the transformer concept can extend duty cycle, and therefore offer an opportunity to improve efficiency. The push-pull buck (PPB) converter is proposed as a solution. The efficiency is improved compared with the buck converter. Integrated magnetic techniques can be used to further improve the efficiency and simplify the implementation. The impact of transformer concept on transient response is analyzed.
The PPB converter efficiency is still not satisfactory at 1MHz due to the switching loss. Switching loss being a barrier, soft switching is needed. The proposed soft-switched phase-shift buck (PSB) converter achieves soft switching for the top switches. Highly efficient power conversion is achieved at high switching frequency. The integrated magnetics makes the implementation concise and delivers good performance. Given that the PSB converter has good performance, the matrix-transformer phase-shift buck (MTPSB) converter is a simplified version of the four-phase PSB converter. The MTPSB converter trades off some performance with circuit complexity. This feature establishes itself as a very cost-effective solution for future VRs. The magnetic structure of the MTPSB converter is also very simple with the use of integrated magnetics.
Mobile CPUs are used in laptop computers. They require very challenging power management. The challenges for a laptop VR are different from and greater than those for a desktop VR. A laptop VR needs to have high efficiency at both heavy load and light load, good transient response and small and light form-factor, and work well with the wide input voltage range. Future mobile CPUs demand very aggressive power. The current single-stage VR approach cannot provide a suitable solution for the future. The PSB converter has disadvantages in light-load efficiency and does not work well with wide input voltage range; therefore it is not a suitable solution for laptop VRs although it is still a suitable solution for desktop VRs. The two-stage approach solves the wide-input-voltage-range issue and improves efficiency at heavy load significantly. The intermediate bus voltage Vbus is a very important parameter impacting overall efficiency. There is not one optimal Vbus value for all load conditions. The heavier the load, the higher the optimal Vbus. Based on this fact, the ABVP control is proposed. Vbus is adaptively positioned according to the load current therefore optimal Vbus is achieved under most conditions. Experimental results verify the theoretical prediction. The ONP control is another control scheme proposed to improve the light-load efficiency. By selecting optimal number of phases based on mobile processor power states, the VR light-load efficiency is improved. Experimental results show the proof. The baby-buck concept is the third concept proposed to improve the very-light-load efficiency. By operating the baby-buck channel, the two-stage VR improves efficiency at very light load. The two-stage VR featuring the three proposed control schemes has much higher efficiency than the single-stage VR over a very wide load range; therefore the battery life is extended. The two-stage VR with the proposed control schemes is a good solution for future laptop VRs.
The problem solving process in this work proves that good solutions in isolated converters can be modified to fit into the non-isolated application. Non-isolated converters and isolated converters are not two separated worlds. On the contrary, these two worlds have many things in common. Good concepts can be transplanted from one world to another with minor modification and many problems can be solved this way. Another proven point in this work is that sometimes the solution is a fundamental, such as the change of power delivery architecture. One should not be limited by what is available right now, and should think outside the box. Once a fundamental change is made, it is very beneficial to take full advantage of the change, as it provides new opportunities.Ph. D.
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Lin, Feng-Hsu. "An Integrated Rectifier/Regulator for a Wireless Battery Charging System." Cleveland, Ohio : Case Western Reserve University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=case1240273573.
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Šojdr, Marek. "Návrh nízko-příkonového interního napěťového regulátoru pro automobilové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399493.
Full textAbstract:
This master’s thesis deals with the design of integrated voltage regulator. Topologies of linear voltage regulators and their stability are discussed. Part of the thesis deals with description and simulation of blocks of selected regulator topology. The thesis describes the difficulties of integrated circuit design in the automotive industry. The electrical scheme of the designed regulator is explained. The work also focuses on the stability of designed regulator. Then presents simulations. It discusses the layout of integrated circuits and the designed voltage regulator.
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Bryndza, Ivan. "Návrh interního napěťového regulátoru pro automobilové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318167.
Full textAbstract:
This work contains topology and circuit design of a linear voltage regulator with respect to suppression of disturbances coming from supplied circuit into the input of the regulator. The converter is designed for integration in automotive sensor applications.
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Lo, Ching-Yu, and 羅靖昱. "High-Efficiency Two-Stage Voltage Regulator Module with Voltage-Divider." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/85291940869162664702.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
101
In the conventional multi-phase interleaved step-down voltage-regulator, the switching frequency is usually raised to improve system transient response and reduce LC filter size. However, the conversion efficiency is poor at light load under high switching frequency. It deteriorates the overall efficiency performance during whole server operation period. Firstly, the feasibility of a two-stage system was verified. The system consists of two multi-phase interleaved step-down modules. The pre-stage circuit is operated at relatively low switching frequency and reduces the input voltage of the post-stage by half. The post-stage is operated at higher switching frequency to increase the system bandwidth. The two-stage system can improve the light-load efficiency significantly and heavy-load efficiency slightly. On the other hand, in order to keep two-stage system’s advantage and further save the cost and reduce total size, a voltage divider has been implemented as the pre-stage module. According to the experimental verifications, a 97% conversion efficiency can be achieved.
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Shiung-hung, Tzeng, and 曾雄鴻. "8A Low Drop-Out Voltage Regulator." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/29404170619894868051.
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碩士逢甲大學
電機工程學系
88
The demand for low-voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics,i.e., cellular phones, pagers, laptops, etc. LDO’s are used coherently with dc-dc converters as well as standalone parts. The purpose of this research project is to design an 8A low drop-out voltage regulators with the following features: 1. Adjustable Output Down to 3V 2. Output Current of 8 Ampere 3. Low Drop-out Voltage 4. Extremely Tight Load and Line Regulations 5. Current and Thermal Limiting 6. Standard 3-Terminal Low Cost TO-220 This regulator will be implemented in AMS (Austria Mikro System International AG) 0.8μm 2 poly 2 metal BiCMOS technology. This regulator contains the following blocks: 1. Constant Current Source 2. Voltage Reference 3. Error Amplifier 4. Thermal Protection Circuit 5. Current Limiting Circuit The line regulation and the load regulation are the two important parameters for regulator design. Keywords： low-voltage, low drop-out voltage, line regulation, load regulation
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HSU, CHUAN-YI, and 徐銓毅. "Study on Voltage Regulator for Vehicles." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/29887972701674392376.
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碩士明志科技大學
機械工程系機械與機電工程碩士班
103
All combustion engine vehicles equipped with an alternator. The purposes of the alternator in vehicle are supplying power for the loads and changing for the battery. The speed of engine will affect the output voltage of the alternator. In order to consider both of the comfortable driving and stable power system, the voltage regulators have to use for voltage regulating in generation system. This thesis focuses on two type of voltage regulators which are transistor type and IC type voltage regulators. The implementation and experimental results are presented in the thesis. As a result, the functions of IC type voltage regulators are better than the transistor type voltage regulators.
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LEE, TING-TA, and 李亭達. "A Low-voltage Low-dropout Regulator." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/10463201607317098873.
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碩士輔仁大學
電機工程學系碩士班
104
This paper proposes a low-voltage low-dropout (LDO) regulator to provide the output voltage of 0.5V with input range from 0.6 ~ 0.9V. The low-voltage reference is generated with the zero temperature coefficient circuit composed by MOS transistors in subthreshold condition. The error amplifier is modulated for the bulk voltage of the transistor to realize low-voltage operation. The low-voltage regulator is achieved with varying the bulk potential of the transistor to obtain the optimal performance between light load and heavy load. The maximum output current is 50mA. Designed with a CMOS 0.18μm technology, this LDO regulator occupies the area of 633μm ×630μm including pads. This active area is 0.097mm2.
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"Any-Cap Low Dropout Voltage Regulator." Master's thesis, 2012. http://hdl.handle.net/2286/R.I.14671.
Full textAbstract:
abstract: Power management plays a very important role in the current electronics industry. Battery powered and handheld applications require novel power management techniques to extend the battery life. Most systems have multiple voltage regulators to provide power sources to the different circuit blocks and/or sub-systems. Some of these voltage regulators are low dropout regulators (LDOs) which typically require output capacitors in the range of 1's to 10's of µF. The necessity of output capacitors occupies valuable board space and can add additional integrated circuit (IC) pin count. A high IC pin count can restrict LDOs for system-on-chip (SoC) solutions. The presented research gives the user an option with regard to the external capacitor; the output capacitor can range from 0 - 1µF for a stable response. In general, the larger the output capacitor, the better the transient response. Because the output capacitor requirement is such a wide range, the LDO presented here is ideal for any application, whether it be for a SoC solution or stand-alone LDO that desires a filtering capacitor for optimal transient performance. The LDO architecture and compensation scheme provide a stable output response from 1mA to 200mA with output capacitors in the range of 0 - 1µF. A 2.5V, 200mA any-cap LDO was fabricated in a proprietary 1.5µm BiCMOS process, consuming 200µA of ground pin current (at 1mA load) with a dropout voltage of 250mV. Experimental results show that the proposed any-cap LDO exceeds transient performance and output capacitor requirements compared to previously published work. The architecture also has excellent line and load regulation and less sensitive to process variation. Therefore, the presented any-cap LDO is ideal for any application with a maximum supply rail of 5V.Dissertation/Thesis
M.S. Electrical Engineering 2012
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Lai, An-Koo, and 賴安谷. "1.8V Low Dropout Voltage Regulator Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/97758520326841094207.
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碩士國立臺灣海洋大學
電機工程學系
92
ABSTRACT Choosing an output capacitor for LDO regulators with PNP or PMOS pass element can be difficult due to specific ESR requirements. This application note explains why higher ESR capacitors are necessary, how to choose them, and how to determine whether or not the regulator is stable. In the typical PMOS or PNP open loop gain plot , there are three important poles in a PMOS or PNP pass element based LDO regulator. The dominant pole, P(DOM), is set in the regulator’s error amplifier. The load pole, P(LOAD), is formed by the output capacitor and load and therefore varies with load current. The pass device pole, P(PASS), is formed by the parasitic capacitance of the pass element. In order for any negative feedback system to be stable, the open loop gain of the system must be below 0 dB when the phase is 360°(180°of the fed-back signal plus the 180°from the inverting input of the error amplifier). Stated another way, the system must have sufficient phase margin, i.e., the amount of phase shift remaining until 360° degree when the gain is at 0 dB. Since each pole contributes 90°of phase shift and 20dB/decade (or -1) rolloff in gain, a three-pole, high gain system requires compensation in order to be stable. A regulator is unconditionally stable (i.e., has sufficient phase margin) if the open loop gain curve rolls off at 20dB/decade (i.e., like a single pole system) before crosses 0 dB. The most common method of compensation is to insert a zero in the system to cancel the phase shift and rolloff of one of the poles. Since an LDO already requires an output capacitor for normal operation, using the output capacitor’s ESR is typically the simplest and least expensive method for generating this zero.
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Li, Ding. "Modeling and design of a transient voltage clamp assisted voltage regulator." 2006. http://www.lib.ncsu.edu/theses/available/etd-05152006-145524/unrestricted/etd.pdf.
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Wang, Chung-Chih, and 王寵智. "Design of A High Voltage Regulator Circuits for Low Supply Voltage." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/53557650385828017980.
Full textAbstract:
碩士國立中興大學
電機工程學系
93
This thesis proposes a high voltage regulator circuit for low supply voltages, which includes ring oscillator circuit, four-phase generator circuit, high-amplitude generator circuit, charge pumping circuit, band-gap reference (BGR) circuit, voltage regulator circuit, voltage regulator controller circuit. The operations of these sub-circuits and the complete regulator are introduced. The thesis also analyzes the low voltage dual pumping circuit and compares, the results of measurement and simulations. In addition, the sub-1V CMOS band-gap reference circuit is analyzed. The theoretical derivation proves and explains why the output waveforms are different from those of the other band-gap reference circuits. Finally, the high voltage regulator circuit is used to generate the output voltages of 6V, 7V, and 8V. It has been taped out using 0.35m CMOS technology.
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Lin, Yu-Jung, and 林育蓉. "A Boost Regulator with Voltage-Mode Control for Low Voltage Applications." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/46212388465032996556.
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碩士國立成功大學
電機工程學系碩博士班
94
A dc-dc voltage-mode boost converter operated in low voltage applications is introduced in this thesis. The boost converter is used to convert Li-ion battery voltage (2.7 V ~ 4.2 V) to 5 V. The synchronous rectification architecture is used to reduce conduction loss and the high efficiency is obtained. At initial operation of the system, sudden current may be generated and soft start circuit is used to avoid this situation and to protect the converter system. When the converter system is operated in discontinuous conduction mode (DCM), higher reversed current will be occurred because of the bi-directional switching of the synchronous rectifier. In order to solve this problem, a zero current detector circuit is designed and power consumption is reduced. Finally, the feedback model is presented and simulated to select suitable compensation networks. Simulation results show that the efficiency of the boost converter is 94 % with 3.6 V input voltage and 5 V / 250 mA conduction. This circuit is implemented with TSMC 0.35μm 3.3/5 V CMOS technology.
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Yang, Cheng-Chang, and 楊政璋. "Study and Implementation of Dynamic Voltage Regulator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/73264826980945901299.
Full textAbstract:
碩士國立雲林科技大學
電機工程系碩士班
94
In the power system network, the large industrial equipments and diode bridge rectifier loads generate large non-sinusoidal currents into the distribution system. These currents contain the serious harmonics and reactive power. Reactive power and intermittent loads variation increase the power losses in the distribution and transmission system result in the voltage variation at the receiving end. Voltage sag and swell, voltage flicker and momentary interruption are the most common problems encountered. This thesis presents a single-phase and three-phase dynamic voltage regulator (DVR) with sinusoidal pulse-width modulation (SPWM) technique to control compensating voltage. When voltage sag and swell conditions occur at source terminal, compensator can provide compensation immediately and make the load voltage at the desired root mean square (RMS) value. The simulation software package MATLAB/SIMULINK is used to simulate the system operation. The digital signal processor (DSP) TMS320C32 is used to implement the proposed circuit configuration. The experimental results are presented to verify the effectiveness of the dynamic voltage regulator.
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黃柏嘉. "Bit Synchronous Single-Wire Based Voltage Regulator." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/3963cs.
Full textAbstract:
碩士逢甲大學
資電碩士在職專班
102
The most popular voltage regulators are analogue type, digital type and BSS(Bit Synchronous Single-Wire) based type. The analogue regulator provides the basic function only. If more functions is required the cost and circuit complexity is higher and higher. The digital regulator provides most of regulator functions. But it requires more space and higher cost. The new developed BSS-based regulator is the most popular voltage regulator used in automobile now. It has advantage of high reliability, easy extension and multiple control functions due to BSS communication between regulator and control system. A BSS-based voltage regulator is designed and implemented in this study. The hardware of this regulator consists of single chip micro-controller, current driver and power supplier. The software program in C language is designed to implement the system function required in this BSS-based regulator.
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Ching-Hsien, Lin, and 林青賢. "VOLTAGE REGULATOR MODULE COMPENSATOR RESEARCH AND APPLICATION." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/24417297786318987690.
Full textAbstract:
碩士元智大學
電機工程學系
92
This thesis proposes that after build VRM small signal model, besides analysis and discuss its characteristics, we can use LabVIEW software to create an application program which can help power supply designer to quickly get the simulated close-loop transfer function curve while develops and designs the converter like as VRM. After compare with the real transfer function curve and correct related parameter of the program, we can obtain a simulated program similar to real one. And base on computer’s speed up mathematic speed characteristic, we can simulate four corner transfer function curves with different conditions which have all kinds of output voltages vs. input voltages and output loads, this will contribute to quickly determine and devise the VRM loop compensation circuitry.
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Lin, Yu-Hsiang, and 林于翔. "A High-PSRR Low-Dropout Voltage Regulator." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/76281057373921718594.
Full textAbstract:
碩士國立交通大學
電機學院電信學程
104
In recent years, mobile electronic products have become very popular in human life. One more key feature of the mobile electronic product is its power circuit. If the electronic product can be designed with a good power system, the quality of the product can be enhanced. This paper presents a high PSRR LDO regulator which uses a two-stage NMOS differential amplifier combined with a NMOS differential circuit and also chooses a high PSRR bandgap circuit for reference voltage. The circuit can achieve the PSRR lower than ≤ -60dBm and -50dBm during pre-simulation and post-simulation, respectively, which are better than the typical of regular LDOs. The chip presented in this thesis was fabricated by Taiwan Semiconductor Manufacturing Company （TSMC）0.35μm 2P4M 3.3V mixed‐signal CMOS process. The chip area is 0.8mm×0.767mm.
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Chung, Shu-Ting, and 鐘淑婷. "Design of DC-DC voltage boosted regulator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/99715493263364512385.
Full textAbstract:
碩士國立中興大學
電機工程學系所
94
This content of this thesis is to present a charge pump circuit which applied to non-volatile memories with a new proposed regulator. The complete circuit includes a voltage-controlled oscillator, a four-phase generator, a high-amplitude generator, a charge pumping circuit and the new proposed voltage regulator circuit. According to prior literatures, we know that it is required a voltage regulator to control the voltage produced by charge pumping circuit for applications in non-volatile memory. In this thesis, unlike the most popular regulator using comparator to switch the oscillator on or off to regulate the charge pumping circuit, the proposed regulator circuit dynamically adjusts the frequency of oscillator circuit so that the charge pumping circuit can generate the desired constant voltage. This new simple circuit reduces ripples at the output. The DC-DC voltage boosted regulator circuit can generate the output voltages of 7V~9V according to the different reference voltages with the oscillation frequency up to 16MHz, while the output ripple of this circuit is less than 260mV.
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McCue, Benjamin Matthew. "A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator." 2010. http://trace.tennessee.edu/utk_gradthes/646.
Full textAbstract:
Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.
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Hung, Kun-Feng, and 洪昆蜂. "A LOW-VOLTAGE LDO REGULATOR WITH TEMPERATURE COMPENSATION WITHIN THE REGULATOR LOOP." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/26710542015073098405.
Full textAbstract:
碩士大同大學
電機工程學系(所)
103
Low dropout (LDO) linear regulators are widely used in various electronic products, especially in the portable electronic products as an important driver. This research focuses on the design of a low-dropout linear regulator, where the positive temperature coefficient of a PTAT (Proportional To Absolute Temperature) voltage source and the negative temperature coefficient of a CTAT (Complementary To Absolute Temperature) current source cancel each other to solve the temperature drift problems in the traditional LDO regulator. Using line voltage compensation and feedback network achieves stability in the whole load range and provides a stable reference voltage while reducing application costs and ensuring system reliability. The low dropout linear regulator design is based on TSMC 0.35um CMOS process. The input voltage is 1.8V, the maximum output voltage is 1.5881V, and the maximum output current is 100mA. The whole chip has been designed, simulated, laid out and verified using the EDA software, such as Hspice, Laker, Cadence and Calibre. The validation results indicate when load current is 100mA, the dropout voltage is 211.9mV, and other performance indicators meet the design requirements.
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Huang, Wei-Lin, and 黃威霖. "A High Efficiency CMOS DC-DC Switching Voltage Regulator for Low Voltage Applications." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/59522187804192606403.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
92
Abstract The design and implementation of a DC-DC buck switching regulator for low supply voltage electronic system is presented in this thesis. This switching regulator has low output ripple in steady state and fast transient response when the load is suddenly changed. It also has high power conversion efficiency that is suitable for portable electronic applications that are powered by batteries such as mobile phone, digital camera, PDA, etc. The switching regulator IC is designed with high operation frequency for reducing the output voltage ripple and the transient response recovery time. In addition, the feedback loop bandwidth is designed as wide as possible to achieve fast transient response. For making power conversion more efficient, the regulator is enhanced with two operation modes, PWM and PFM, for heavy and light load conditions. Another technique for increasing the power conversion efficiency is to design the buffer for driving the power MOSFET with the characteristics of anti-shoot through current and adaptive dead time control. This technique can prevent the occurrences of the shoot through current and reduce the body diode conduction time during switching transitions. To eliminate the excess large current at the start up of the regulator that may damage the devices of the power stage, the soft start operation is designed. This regulator IC is fabricated with TSMC 0.35um 2P4M 3.3V/5V Mixed Signal CMOS technology through CIC. The chip size is about 1.5×1.5 mm2. Other detailed performances will be described in the following chapters.
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Lin, Li-Chi, and 林莉琪. "An Auto-Calibration Voltage Regulator Module with Dual-Loop Adaptive Voltage Position Technique." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/uue33q.
Full textAbstract:
碩士國立交通大學
電控工程研究所
106
Owing to new technological advances, the central processor unit (CPU) used in mobile devices needs faster logic computing capability, higher reliability, and higher stability. In order to make the CPU operate in a stable environment, the power supply of the CPU requires high efficiency and low power consumption. Therefore, dynamic voltage identification (DVID) technique and adaptive voltage position (AVP) technique are usually implemented in the voltage regulator module (VRM) for the CPU. In addition, in conventional design, multiple DC-DC buck converters are used to provide multi-output voltage for the multi-cores of the CPU. However, this architecture is not suitable for the CPU because of the cost and area consideration. Consequently, a single inductor multi-output (SIMO) DC-DC converter becomes a good candidate due to the advantage of compact size and low cost. However, SIMO converter has larger output ripple and poor load variation response, which are not allowed by the CPU. As the result, each output of the SIMO converter needs to cascade a linear regulator to lower the output voltage ripple. However, due to the wide load range of CPU, the analog low-dropout (A-LDO) regulator requires larger dropout voltage, which degrades system power conversion efficiency. Therefore, the proposed VRM includes the SIMO converter and cascaded digital low-dropout (D-LDO) regulators which have low dropout voltage characteristic and thus lower the voltage ripple without degrading power conversion efficiency. Besides, the proposed VRM integrates AVP and DVID techniques as auto calibration dual-AVP (ACD-AVP) technique with the help of the D-LDO, thereby improving overall performance of the VRM under any load condition and OPPs.
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Chun-HsunWu and 吳俊勳. "Fast Transient Output-Capacitorless Low-Dropout Voltage Regulator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/69608068930430767157.
Full textAbstract:
博士國立成功大學
電機工程學系碩博士班
100
With the versatile developing trend of the portable electronic devices, the role of on-chip power converters is becoming more and more important for the integrated circuits (ICs). This dissertation first introduces three types of commonly used on-chip power converters. Following that, the topic focuses on the low-dropout voltage regulator (LDO) due to its generality and significance in the IC power supply. LDO’s basic working principle, small signal model, as well as load transient response are comprehensively illustrated. Major issues of the recent researches including the low supply voltage, low quiescent current, fast load transient response and output-capacitorless structure are discussed. Specifically, influence of the quiescent current of the OPA on LDO’s load transient and reference tracking is then reviewed in detail. To achieve fast transient but keep quiescent current as low as possible for improving the power efficiency, this dissertation proposes two dynamic bias approaches to enhance the transient response of the LDO. The first proposed circuit is called transient quiescent current booster (TQCB). Embedding a TQCB within the OPA of a LDO, theoretical analysis and test results have shown its effectiveness in the fast transient performance. However, this design does not reach the optimal power efficiency because the TQCB circuit always consumes a branch current either the LDO is working in standby or active mode. To design a faster transient response and more power-efficient LDO, a full quiescent current enhancement (FQCE) circuit which possesses the automatic shut-off function is proposed afterward. Testing results show that the voltage spike is reduced about 62% compared with the LDO without the proposed circuit in response to 50mA/300ns load change. Under such a load change, the voltage recovery time of the LDO is less than 0.5μs and the stability is guaranteed. In addition to the load transient response, the other important feature that the FQCE circuit can do is to facilitate the reference tracking speed. Reference tracking is generally required in the bio-implantable medical devices to achieve dynamic voltage and frequency scaling (DVFS) for saving more power. The key factor for optimizing the reference tracking is determined by the quiescent current Iq as well. Therefore, the FQCE circuit is also suitable to the reference tracking issue. With the FQCE circuit, a fast transient output-capaciotrless LDO working at low supply voltage with high power efficiency could be easily implemented in various IC power applications.
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Lin, Cheng-Ming, and 林政銘. "Design of Dynamic Voltage Regulator Using Fuzzy Logic." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/61780406372462614609.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
95
The power quality affects the industry to a great extent. Poor quality in the power supply, such as voltage fluctuations, may cause damage in sensitive equipments. How to maintain constant voltage profile at the load bus under disturbance conditions is of major concern in this work. The purpose of this thesis is to use fuzzy logic control to design the Dynamic Voltage Regulator (DVR). This compensator employs a direct current capacitor to offer the voltage source and uses the pulse-width modulation technology to adjust the output voltage of the three-phase voltage-source inverter. DVR can be used to compensate the voltage drop caused by balanced system fault. The effectiveness of the designed DVR is first investigated by digital simulations using the MATLAB software. Then, in the experiment, the control kernel of digital system for DVR is based on a personal computer with Adventec PCL-1800 data acquisition cards. The three-phase pulse width modulation signals are generated by computer software in order to reach the objective of voltage compensation.Finally, it is concluded from results of simulations and experiments that load bus voltage can be effectively regulated by the designed DVR.
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RU, CHEN HAN, and 陳漢儒. "Low Dropout Voltage Regulator for Biomedical Circuit Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/rt3pv2.
Full textAbstract:
碩士亞東技術學院
資訊與通訊工程研究所
98
With the increasing demanding of portable biomedical devices, how to use the battery energy efficiently is the most concerned problem. Therefore, power management system is indispensable for modern consumer products. For power management system, LDO circuit contains Error Amplifier, current reference and bandgap reference. Low-dropout (LDO) liner regulator is the most common block due to the characteristics, such as simplicity, small board space, low noise and cost. The proposed LDO implemented with a standard TSMC 0.35um Mixed-Signal 2P4M Polycide 3.3/5V process technology. Supply voltage 2.3V~3.3V, Output Voltage 1.8V. The simulation results show that maximum load current of 120mA, and show that the PSRR of 1k and 10k are -48.2dB and -32.4dB respectively; input range 2.3V and 3.3V, the LDO has temperature coefficient 6.42ppm/oC and 7.72ppm/oC respectively. The active area of this LDO is 676×567μm2.
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Jiang, Yi-Ru, and 姜怡如. "Study of a Modular Three-Phase Voltage Regulator." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/nfy443.
Full textAbstract:
碩士國立宜蘭大學
電機資訊學院碩士在職專班
102
This thesis presents a modular three-phase voltage regulator. The proposed scheme is the combination of three single-phase modules while each one of the single-phase module is a serial-capacitor compensation voltage regulator which is based on a three-arm AC voltage regulator with fictitious dc-link. Therefore, the proposed voltage regulator reduces the number of main switches and compensates the voltage of each phase independently. Furthermore, a film AC capacitor is used to replace the tranditional electrolytic capacitor, which not only reduce the size of the dc link capacitor and the stress of the switches but also increase the lifetime of the voltage regulator. Instead of the conventional high DC voltage, the voltage of the film AC capacitance can reduces the stress of switches. The three-arm topology operates as a rectifier and an inverter where the low frequency arm is switched at line-frequency that is synchronized to the source voltage to achieve low switching losses while the rectifier arm and the inverter arm are switched at high switching frequency for the output voltage regulation. The proposed scheme can compensate the voltage disturbances such as under-voltage, over-voltage, voltage sag, voltage swell, three-phase voltage unbalance and three-phase load unbalance effectively. Besides, there are several advantages of this structure, for instance: simple system-configuration, rapid voltage-compensation, easy setup-maintenance and decreasing the production cost while increasing the system power density. Eventually, some simulation and experimental results are provided to illustrate the steady-state characteristics and transient responses of the proposed modular three-phase voltage regulator.
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Gan, Yu-Sheng, and 甘昱昇. "Knee Voltage Detection Technique for Primary-Side Regulator." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/369sx7.
Full textAbstract:
碩士國立雲林科技大學
電機工程系
102
Nowadays, high-tech products are an essential part of our lives. Portable electronic devices greatly enhance the quality and convenience of life. One of the critical elements in portable electronic devices is the rechargeable battery. Therefore, how to transfer energy to the battery in a fast and efficient way under the best and the safest condition is an important issue. Universal Serial Bus (USB) is a frequently-used interface protocol in personal computer. And it’s also widely applied in the portable electronic devices. The most common charging method of portable electronic devices is to transform alternating current (AC) into direct current (DC) with the aid of the USB interface. Primary-Side Regulator (PSR) can be adopted in a low-cost and high-efficiency charger. And it is also a charger that can accept high input voltages of supply mains. Since there is no direct feedback path for Primary-Side Regulator (PSR) to obtain the accurate information of the output voltage, how to obtain the correct output information of charging system in order to maintain switching stability of constant current and constant voltage becomes a critical design issue. The knee voltage is defined as the output voltage without the voltage drop of the diode at the secondary-side. In order to acquire the correct output information, this thesis is dedicated on the knee voltage detection (KVD) technique that can track the secondary output voltage via the auxiliary-side winding with the diode being cutoff. And a dynamic self-calibrator circuit is also realized to prevent detection errors against incorrect output information. Therefore, the PSR can switch between the constant current (CC) mode and constant voltage (CV) mode accurately and stably during charging.