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1
Quintero, Francisco Javier 1955. "Analysis of an integrated voltage regulator amplifier and design alternatives." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276753.
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This Thesis Research involves the analysis, simulation and design alternatives for an industrially-relevant voltage regulator. An initial prototype circuit, designed by Texas Instruments Inc., is simulated and analysed in detail. Then an alternative circuit is derived which improves the circuit performance by implementing different compensation techniques and some transistors modifications. The final circuit has excellent phase margin, transient response and load regulation.
2
Lee, Kisun. "Advanced Control Schemes for Voltage Regulators." Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/26938.
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The microprocessor faces a big challenge of heat dissipation. In order to enhance the performance of the microprocessor without increasing the heat dissipation, the leading microprocessor company, Intel, uses several methods to reduce the power consumption. Theses methods include enhanced sleep states control, the Speed Step technology, and multi-core architecture. These are closely related to the Voltage Regulator (VR), a dedicated power supply for the microprocessor and its control method. The speed of the VR control system should be high in order to meet the stringent load-line requirements with the high current and high di/dt, otherwise, a lot of decoupling capacitors are necessary. Capacitors make the VR cost and size higher. Therefore, the VR control method is very important. This dissertation discusses the way to increase the speed of VR without degrading other functions, such as the system efficiency, and the required control functions (AVP, current sharing and interleaving).
The easiest way to increase the speed of the VR is to increase the switching frequency. However, higher switching frequency results in system efficiency degradation. This paper uses two approaches to deal with this issue. The first one is the architecture approach. The other is the fast transient control approach.
For the architecture approach, a two-stage architecture is chosen. It is already shown that with a two-stage architecture, the switching frequency of the second stage can be increased, while keeping the same system efficiency. Therefore with the two-stage architecture, a high performance VR can be easily implemented. However, the light-load efficiency of two-stage architecture is not good because the bus voltage is designed for the full-load efficiency which is not optimized for the light load. The light-load efficiency is also important factor and it should be maximized because it is related to the battery life of mobile application or the energy utilization. Therefore, Adaptive Bus Voltage Positioning (ABVP) control has been proposed. By adaptively adjusting the bus voltage according to the load current, the system efficiency can be optimized for whole load range.
The bus voltage rate of change is determined by the first stage bandwidth. In order to maintain regulation during a fast dynamic load, the first stage bandwidth should be high. However, it is observed from hardware when the first stage bandwidth is higher, the ABVP system can become unstable. To get a stable system, the first stage bandwidth is often designed to be slow which causes poor ABVP dynamic response. The large number of bus capacitors necessary for this also increases the size and cost. In this dissertation, in order to raise the first stage bandwidth, a stability analysis is performed. The instability loop (TABVP) is identified, and a small signal model to predict this loop is suggested. TABVP is related to the first stage bandwidth. With the higher first stage bandwidth, the peak magnitude of TABVP is larger. When the peak magnitude of TABVP touches 0dB, the system becomes unstable. Two solutions are proposed to reduce this TABVP magnitude without decreasing the first stage bandwidth. One method is to increase the feedforward gain and the other approach is to use a low pass filter. With these strategies, the ABVP system can be designed to be stable while pushing first stage bandwidth as high as possible. The ABVP-AVP system and its design are verified with hardware.
For the fast transient control approach hysteretic control is chosen because of its fast transient and high light-load efficiency with DCM operation. However, in order to use the hysteretic control method for multiphase VR applications interleaving must be implemented. In this dissertation, a multiphase hysteretic control method is proposed which can achieve interleaving without losing its benefits. Using the phase locked loop (PLL), this control method locks the phase and frequency of the duty cycles to the reference clocks by modifying the size of the hysteretic band, to say, hysteretic band width. By phase shifting the reference clocks, interleaving can be achieved under steady state. During the load transient, the system loses the phase-locking function due to the slow hysteretic band width changing loop, and the system then reacts quickly to the load change without the interruption from the phase locking function (or the interleaving function).
The proposed hysteretic control method consists of two loops, the fast hysteretic control loop and the slow hysteretic band width changing loop. These two nonlinear loops are difficult to model and analyze together. Therefore, assuming these two loops can be separated because of the speed difference, the phase plane model is used for the fast hysteretic control loop and the sampled data model is then used for the slow hysteretic band width changing loop. With these models, the proposed hysteretic control method can be analyzed and properly designed. However, if the transient occurs before the slow hysteretic band width changing loop settles down, the transient may start with the large hysteretic band width and the output voltage peak can exceed the specification. To prevent this, a hysteretic band width limiter is inserted.
With the hardware, the proposed hysteretic control method and its design are verified. A two-phase VR with 300kHz switching frequency is built and the output capacitance required is only 860μF comparing to 1600μF output capacitance with the 50kHz bandwidth linear control method. That is about 46% capacitor reduction.
The proposed hysteretic control method saturates the controller during the transient and the transient peak voltage is determined by the power stage parameters, the inductance and the output capacitors. By decreasing the inductance, the output capacitors are reduced. However, small inductance results in the low efficiency. In order to resolve this, the coupled inductor is used. With the coupled inductor, the transient inductance can be reduced with the same steady state inductance. Therefore, the transient speed can be faster without lowering down the system efficiency. The proposed hysteretic control method with the coupled inductor can be implemented using the DCR current sensing network.
A two-phase VR with the proposed hysteretic control and the coupled inductor is built and the output capacitance is only 660μF comparing to 860μF output capacitance with the proposed hysteretic control only. A 23% capacitor reduction is achieved. And compared to the 50kHz bandwidth linear control method, a 60% capacitor reduction is achieved.Ph. D.
3
Zhou, Jinghai. "High Frequency, High Current Density Voltage Regulators." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/27268.
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As a very special DC-DC converter, VRM (Voltage Regulator Module) design must follow the fast-developing trend of microprocessors. The design challenges are the high current, high di/dt, and stringent load-line requirement. When the energy is transferred from the input of a VRM, through the VRM, then through the power delivery path to the processor, it needs sufficient capacitors to relay this energy. The capacitorsâ number appears to be unrealistically large if we follow todayâ s approach for the future processors. High frequency VRM with high control bandwidth can solve this problem, however, the degradation of efficiency makes the conventional buck converter and the hard-switching isolated topologies incapable of operating at higher frequency. The research goal is to develop novel means that can help a high-output- current VRM run efficiently at high frequency.
A novel Complementary Controlled Bridge (CCB) self-driven concept is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and the self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary- side synchronous rectifier (SR) as the snubber capacitor of the primary-side switches. Compared to the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared to the existing level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal ringing is small and suitable for high-frequency applications.
Although the CCB self-driven VRM reduces the switching frequency-related losses significantly, the conduction loss is still high. Inspired by the current-doubler concept, a novel ZVS current-tripler DC-DC converter is proposed in this work. By utilizing more SR devices to share the current during the freewheeling period, the SR conduction loss is reduced. The current-tripler DC-DC converter has a delta/delta connected transformer that can be implemented with integrated magnetics. The transformer then becomes an integrated magnetic with distributed windings, which is preferred in high current applications. The current-tripler DC-DC converter in fact meets the requirements for the CCB self-driven scheme. The two concepts are then combined with an integrated gate drive transformer.
The proposed CCB self-driven concept and current-tripler concept can both be applied to the 12V non-isolated VRMs. The proposed topology is basically a buck-derived soft-switching topology with duty cycle extension and SR device self-driven capabilities. Because there is no isolation requirement, the SR gate driving becomes so simple that the voltage at the complementary controlled bridge can be used to directly drive the SR gate. Both the gate driving loss and the SR body diode conduction loss are reduced. The proposed circuit achieves similar overall efficiency to a conventional 300kHz buck converter running at 1MHz.
All the circuits proposed in this dissertation can use coupling inductors to improve both the steady-state efficiency and dynamic performances. The essence of the coupling inductors concept is to provide different equivalent inductances for the steady state and the transient. Moreover, when a current loop becomes necessary to achieve proper current sharing among phases, the current loop sample hold effect will make it difficult to push the bandwidth. The sample hold effect is alleviated by the coupling inductors concept. A small-signal model is proposed to study the system dynamic performance difference with different coupling inductor designs. As the verification, the coupling concept is applied to the 12V non-isolated CCB self-driven VRM and the bandwidth as high as one third of the switching frequency is achieved, which means a significant output capacitor reduction.Ph. D.
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Xiao, Shangyang. "TRANSIENT RESPONSE IMPROVEMENT FOR MULTI-PHASE VOLTAGE REGULATORS." Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3909.
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Next generation microprocessor (Vcore) requirements for high current slew rates and fast transient response together with low output voltage have posed great challenges on voltage regulator (VR) design . Since the debut of Intel 80X86 series, CPUs have greatly improved in performance with a dramatic increase on power consumption. According to the latest Intel VR11 design guidelines , the operational current may ramp up to 140A with typical voltages in the 1.1V to 1.4V range, while the slew rate of the transient current can be as high as 1.9A/ns [1, 2]. Meanwhile, the transient-response requirements are becoming stringer and stringer. This dissertation presents several topics on how to improve transient response for multi-phase voltage regulators. The Adaptive Modulation Control (AMC) is a type of non-linear control method which has proven to be effective in achieving high bandwidth designs as well as stabilizing the control loop during large load transients. It adaptively adjusts control bandwidth by changing the modulation gain, depending on different load conditions. With the AMC, a multiphase voltage regulator can be designed with an aggressively high bandwidth. When in heavy load transients where the loop could be potentially unstable, the bandwidth is lowered. Therefore, the AMC provides an optimal means for robust high-bandwidth design with excellent transient performance. The Error Amplifier Voltage Positioning (EAVP) is proposed to improve transient response by removing undesired spikes and dips after initial transient response. The EAVP works only in a short period of time during transient events without modifying the power stage and changing the control loop gain. It facilitates the error amplifier voltage recovering during transient events, achieving a fast settling time without impact on the whole control loop. Coupled inductors are an emerging topology for computing power supplies as VRs with coupled inductors show dynamic and steady-state advantages over traditional VRs. This dissertation first covers the coupling mechanism in terms of both electrical and reluctance modeling. Since the magnetizing inductance plays an important role in the coupled-inductor operation, a unified State-Space Averaging model is then built for a two-phase coupled-inductor voltage regulator. The DC solutions of the phase currents are derived in order to show the impact of the magnetizing inductance on phase current balancing. A small signal model is obtained based on the state-space-averaging model. The effects of magnetizing inductance on dynamic performance are presented. The limitations of conventional DCR current-sensing for coupled inductors are addressed. Traditional inductor DCR current sensing topology and prior arts fail to extract phase currents for coupled inductors. Two new DCR current sensing topologies for coupled inductors are presented in this dissertation. By implementation of simple RC networks, the proposed topologies can preserve the coupling effect between phases. As a result, accurate phase inductor currents and total current can be sensed, resulting in excellent current and voltage regulation. While coupled-inductor topologies are showing advantages in transient response and are becoming industry practices, they are suffering from low steady-state operating efficiency. Motivated by the challenging transient and efficiency requirements, this dissertation proposes a Full Bridge Coupled Inductor (FBCI) scheme which is able to improve transient response as well as savor high efficiency at (a) steady state. The FBCI can change the circuit configuration under different operational conditions. Its "flexible" topology is able to optimize both transient response and steady-state efficiency. The flexible core configuration makes implementation easy and clear of IP issues. A novel design methodology for planar magnetics based on numerical analysis of electromagnetic fields is offered and successfully applied to the design of low-voltage high power density dc-dc converters. The design methodology features intense use of FEM simulation. The design issues of planar magnetics, including loss mechanism in copper and core, winding design on PCB, core selections, winding arrangements and so on are first reviewed. After that, FEM simulators are introduced to numerically compute the core loss and winding loss. Consequently, a software platform for magnetics design is established, and optimized magnetics can then be achieved. Dynamic voltage scaling (DVS) technology is a common industry practice in optimizing power consumption of microprocessors by dynamically altering the supply voltage under different operational modes, while maintaining the performance requirements. During DVS operation, it is desirable to position the output voltage to a new level commanded by the microprocessor (CPU) with minimum delay. However, voltage deviation and slow settling time usually exist due to large output capacitance and compensation delay in voltage regulators. Although optimal DVS can be achieved by modifying the output capacitance and compensation, this method is limited by constraints from stringent static and dynamic requirements. In this dissertation, the effects of output capacitance and compensation network on DVS operation are discussed in detail. An active compensator scheme is then proposed to ensure smooth transition of the output voltage without change of power stage and compensation during DVS. Simulation and experimental results are included to demonstrate the effectiveness of the proposed scheme.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
5
Rincon-Mora, Gabriel Alfonso. "Current efficient, low voltage, low drop-out regulators." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/13359.
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Turner, Steven Primitivo. "Adaptive out of step relay algorithm." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-01242009-063244/.
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Olajubutu, Michael Olaolu. "Utilizing microprocessor based relays as predictive tools to mitigate voltage instability problems that stem from the fast voltage collapse and delayed voltage recovery phenomena." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Theses/OLAJUBUTU_MICHAEL_35.pdf.
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Milošević, Borka. "On voltage stability monitoring and control using multiagent systems." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/16355.
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Al-Hinai, Amer. "Voltage collapse prediction for interconnected power systems." Morgantown, W. Va. : [West Virginia University Libraries], 2000. http://etd.wvu.edu/templates/showETD.cfm?recnum=1639.
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Thesis (M.S.)--West Virginia University, 2000.Title from document title page. Document formatted into pages; contains xii, 94 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 66-67).
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López, Julià Toni. "Prospects of voltage regulators for next generation computer microprocessors." Doctoral thesis, Universitat Politècnica de Catalunya, 2010. http://hdl.handle.net/10803/77908.
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Synchronous buck converter based multiphase architectures are evaluated to
determine whether or not the most widespread voltage regulator topology can
meet the power delivery requirements of next generation computer
microprocessors. According to the prognostications, the load current will rise to
200A along with the decrease of the supply voltage to 0.5V and staggering tight
dynamic and static load line tolerances. In view of these demands, researchers face
serious challenges to bring forth compliant solutions that can further offer
acceptable conversion efficiencies and minimum mainboard area occupancy.
Among the most prominent investigation fronts are those surveying
fundamental technology improvements aiming at making power semiconductor
devices more effective at high switching frequency. The latter is of critical
importance as the increase of the switching frequency is fundamentally recognized
as the way forward to enhance power density conversion. Provided that switching
losses must be kept low to enable the miniaturization of the filter components, one
primary goal is to cope with semiconductor and system integration technologies
enabling fast dynamic operation of ultra-low ON resistance power switches.
This justifies the main focus of this thesis work, centered around a
comprehensive analysis of the MOSFET switching behavior in the synchronous
buck converter.
The MOSFETs dynamic operation, far from being well describable with the
traditional clamped inductive hard-switching mode, is strongly influenced by a
number of frequently ignored linear and nonlinear parasitic elements that must be
taken into account in order to fully predict real switching waveforms, understand
their dynamics, and most importantly, identify and quantify the related
mechanisms leading to heat generation. This will be revealed from in-depth
investigations of the switched converter under fast switching speeds and heavy
load.
Recognizing the key relevance of appropriate modeling tools that support this
task, the second focal point of the thesis aims at developing a number of suitable
models for the switching analysis of power MOSFETs.
Combined with a series of design guidelines and optimization procedures, these
models form the basis of a proposed methodological approach, where numerical
computations replace the usually enormous experimental effort to elucidate the
most effective pathways towards reducing power losses. This gives rise to the
concept referred to as virtual design loop, which is successfully applied to the
development of a new power MOSFET technology offering outstanding dynamic
and static performance characteristics. From a system perspective, the limits of the
power density conversion will be explored for this and other emerging
technologies that promise to open up a new paradigm in power integration
capabilities.
11
Sun, Julu. "Investigation of Alternative Power Architectures for CPU Voltage Regulators." Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/30119.
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Since future microprocessors will have higher current in accordance with Mooreâ s law, there are still challenges for voltage regulators (VRs). Firstly, high efficiency is required not only for easy thermal management, but also for saving on electricity costs for data centers, or battery life extension for laptop computers. At the same time, high power density is required due to the increased power of the microprocessors. This is especially true for data centers, since more microprocessors are required within a given space (per rack). High power density is also required for laptop computers to reduce the size and the weight.
To improve power density, a high frequency is required to shrink the size of the output inductors and output capacitors of the multi-phase buck VR. It has been demonstrated that the output bulk capacitors can be eliminated by raising the VR control bandwidth to around 350kHz. Assuming the bandwidth is one-third of the switching frequency, a VR should run at 1MHz to ensure a small size. However, the efficiency of a 12V VR is very poor at 1MHz due to high switching losses. As a result, a 12V VR can only run at 300kHz to 600kHz, and the power density is very low.
To attain high efficiency and high power density at the same time, two-stage power architecture was proposed. The concept is â Divide and Conquerâ . A single-stage VR is split into two stages to get better performance. The second stage has about 5V-6V input voltage; thus the duty cycle can be extended and the switching losses are greatly reduced compared with a single-stage VR. Moreover, a sub-20V MOSFET can be used to further improve the efficiency at high frequencies.
The first stage of the proposed two-stage architecture is converting 12V to 5-6V. High efficiency is required for the first stage since it is in series with the second stage. Previous first stage which is a buck converter has good efficiency but bulky size due to low frequency operation. Another problem with using a buck converter is that light-load efficiency of the first stage is poor. To solve these problems, switched-capacitor voltage dividers are proposed. Since the first stage does not require voltage regulation, the sweet point for the voltage divider can be determined and high efficiency can be achieved. At the same time, since there are no magnetic components for the switched-capacitor voltage divider, high power density can be achieved. By very careful design, a power density of more than 2000W/in3 with more than 97% efficiency can be achieved for the proposed voltage divider. The light-load efficiency of the voltage divider can be as high as 99% by reducing the switching frequency at light load.
As for the second stage, different low-voltage devices are evaluated, and the best device combinations are found for high-frequency operation. It has been demonstrated that 91% efficiency can be achieved with 600kHz frequency, and 89% efficiency can be achieved with a 1MHz frequency for the second stage. Moreover, adaptive on-time control method and a non-linear inductor structure are proposed to improve CCM and DCM efficiency for the second stage respectively.
Previously the two-stage VR was only used as a CPU VR. The two-stage concept can also be applied to other systems. In this dissertation, the two-stage power architecture is applied to two different applications: laptop computers and high-end server microprocessors. The common characteristics of the two applications are their thermal design power (TDP) requirement. Thus the first stage can be designed with much lower power than the maximum system power. It has been demonstrated that the two-stage power architecture can achieve either higher efficiency or higher power density and a lower cost when compared with the single-stage VR.
To get higher efficiency, a parallel two-stage power architecture, named sigma architecture, is proposed for VR applications. The proposed sigma VR takes advantage of the high-efficiency, fast-transient unregulated converter (DCX) and relies on this converter to deliver most of the output power, while using a low-power buck converter to achieve voltage regulation. Both the DCX converter and the buck converter can achieve around 90% efficiency when used in the sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the sigma VR is studied to achieve adaptive voltage positioning (AVP). The sigma power architecture can also be applied to low-power point of load (POL) applications to reduce the magnetic component size and improve the efficiency. Finally, the two-stage VR and the sigma VR are briefly compared.Ph. D.
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Wei, Jia. "High Frequency High-Efficiency Voltage Regulators for Future Microprocessors." Diss., Virginia Tech, 2004. http://hdl.handle.net/10919/11254.
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Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. At first, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. For laptop application, the VR input voltage range covers the battery voltage range and the adaptor voltage. In the meantime, microprocessors will run at very low voltage (sub 1V), and will consume up to 150A of current, and will have dynamics of about 400A/us.
The current VR solution is the 12V-input multiphase interleaved buck converter. The switching frequency is around 300KHz. This approach has several limitations for the future. OSCON capacitor is one limitation due to its large ESR and ESL; the low switching frequency the second limitation and the large inductance is the third limitation. Analysis shows that the all-ceramic solution is a better solution than the OSCON solution when the VR switching frequency reaches 1MHz. However, the 12V-input multiphase buck converter suffers low efficiency at high switching frequency, which rules out a legitimate chance of the current VR topology benefiting from high switching frequency.
The extreme duty cycle is the fundamental reason why the 12V-input multiphase buck converter is not suitable for future VRs. Employing the transformer concept can extend duty cycle, and therefore offer an opportunity to improve efficiency. The push-pull buck (PPB) converter is proposed as a solution. The efficiency is improved compared with the buck converter. Integrated magnetic techniques can be used to further improve the efficiency and simplify the implementation. The impact of transformer concept on transient response is analyzed.
The PPB converter efficiency is still not satisfactory at 1MHz due to the switching loss. Switching loss being a barrier, soft switching is needed. The proposed soft-switched phase-shift buck (PSB) converter achieves soft switching for the top switches. Highly efficient power conversion is achieved at high switching frequency. The integrated magnetics makes the implementation concise and delivers good performance. Given that the PSB converter has good performance, the matrix-transformer phase-shift buck (MTPSB) converter is a simplified version of the four-phase PSB converter. The MTPSB converter trades off some performance with circuit complexity. This feature establishes itself as a very cost-effective solution for future VRs. The magnetic structure of the MTPSB converter is also very simple with the use of integrated magnetics.
Mobile CPUs are used in laptop computers. They require very challenging power management. The challenges for a laptop VR are different from and greater than those for a desktop VR. A laptop VR needs to have high efficiency at both heavy load and light load, good transient response and small and light form-factor, and work well with the wide input voltage range. Future mobile CPUs demand very aggressive power. The current single-stage VR approach cannot provide a suitable solution for the future. The PSB converter has disadvantages in light-load efficiency and does not work well with wide input voltage range; therefore it is not a suitable solution for laptop VRs although it is still a suitable solution for desktop VRs. The two-stage approach solves the wide-input-voltage-range issue and improves efficiency at heavy load significantly. The intermediate bus voltage Vbus is a very important parameter impacting overall efficiency. There is not one optimal Vbus value for all load conditions. The heavier the load, the higher the optimal Vbus. Based on this fact, the ABVP control is proposed. Vbus is adaptively positioned according to the load current therefore optimal Vbus is achieved under most conditions. Experimental results verify the theoretical prediction. The ONP control is another control scheme proposed to improve the light-load efficiency. By selecting optimal number of phases based on mobile processor power states, the VR light-load efficiency is improved. Experimental results show the proof. The baby-buck concept is the third concept proposed to improve the very-light-load efficiency. By operating the baby-buck channel, the two-stage VR improves efficiency at very light load. The two-stage VR featuring the three proposed control schemes has much higher efficiency than the single-stage VR over a very wide load range; therefore the battery life is extended. The two-stage VR with the proposed control schemes is a good solution for future laptop VRs.
The problem solving process in this work proves that good solutions in isolated converters can be modified to fit into the non-isolated application. Non-isolated converters and isolated converters are not two separated worlds. On the contrary, these two worlds have many things in common. Good concepts can be transplanted from one world to another with minor modification and many problems can be solved this way. Another proven point in this work is that sometimes the solution is a fundamental, such as the change of power delivery architecture. One should not be limited by what is available right now, and should think outside the box. Once a fundamental change is made, it is very beneficial to take full advantage of the change, as it provides new opportunities.Ph. D.
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Liu, Pei-Hsin. "Advanced Control Schemes for High-Bandwidth Multiphase Voltage Regulators." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/52275.
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Advances in transistor-integration technology and multi-core technology of the latest microprocessors have driven transient requirements to become more and more stringent. Rather than relying on the bulky output capacitors as energy-storage devices, increasing the control bandwidth (BW) of the multiphase voltage regulator (VR) is a more cost-effective and space-saving approach. However, it is found that the stability margin of current-mode control in high-BW design is very sensitive to operating conditions and component tolerance, depending on the performance of the current-sensing techniques, modulation schemes, and interleaving approaches. The primary objective of this dissertation is to investigate an advanced multiphase current-mode control, which provides accurate current sensing, enhances the stability margin in high-BW design, and adaptively compensates the parameter variations.
Firstly, an equivalent circuit model for generic current-mode controls using DCR current sensing is developed to analyze the impact of component tolerance in high-BW design. Then, the existing state-of-the-art auto-tuning method used to improve current-sensing accuracy is reviewed, and the deficiency of using this method in a multiphase VR is identified. After that, enlightened by the proposed model, a novel auto-tuning method is proposed. This novel method features better tuning performance, noise-insensitivity, and simpler implementation than the state-of-the-art method.
Secondly, the current state-of-the-art adaptive current-mode control based on constant-frequency PWM is reviewed, and its inability to maintain adequate stability margin in high-BW design is recognized. Therefore, a new external ramp compensation technique is proposed to keep the stability margin insensitive to the operating conditions and component tolerance, so the proposed high-BW constant-frequency control can meet the transient requirement without the presence of bulky output capacitors. The control scheme is generic and can be used in various kinds of constant-frequency controls, such as peak-current-mode, valley-current-mode, and average-current-mode configurations.
Thirdly, an interleaving technique incorporating an adaptive PLL loop is presented, which enables the variable-frequency control to push the BW higher than proposed constant-frequency control, and avoids the beat-frequency input ripple. A generic small-signal model of the PLL loop is derived to investigate the stability issue caused by the parameter variations. Then, based on the proposed model, a simple adaptive control is developed to allow the BW of the PLL loop to be anchored at the highest phase margin. The adaptive PLL structure is applicable to different types of variable-frequency control, including constant on-time control and ramp pulse modulation.
Fourthly, a hybrid interleaving structure is explored to simplify the implementation of the adaptive PLL structure in an application with more phases. It combines the adaptive PLL loop with a pulse-distribution technique to take the advantage of the high-BW design and fast transient response without adding a burden to the controller implementation.
As a conclusion, based on the proposed analytical models, effective control concepts, systematic optimization strategies, viable implementations are fully investigated for high-BW current-mode control using different modulation techniques. Moreover, all the modeling results and the system performance are verified through simulation with a practical output filter model and an advanced mixed-signal experimental platform based on the latest MHz VR design on the laptop motherboard. In consequence, the multiphase VRs in future computation systems can be scalable easier with proposed multiphase configurations, increase the system reliability with proposed adaptive loop compensation, and minimize the total system footprint of the VR with the superior transient performance.Ph. D.
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Hau, King-kuen. "AC mains voltage regulation by solid-state power conversion techniques /." [Hong Kong] : University of Hong Kong, 1990. http://sunzi.lib.hku.hk/hkuto/record.jsp?B13009503.
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侯經權 and King-kuen Hau. "AC mains voltage regulation by solid-state power conversiontechniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209737.
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Woodworth, Ronald Keith. "THE DYNAMIC THERMAL ANALYSIS OF A VOLTAGE REGULATOR CIRCUIT." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275365.
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Jia, Zhihong. "Contingency ranking for on-line voltage stability assessment." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0016/MQ54925.pdf.
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Low, Aichen. "A floating-gate low dropout voltage regulator." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14886.
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Cheniae, Michael G. "Observability method for the least median of squares estimator as applied to power systems." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-08142009-040309/.
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SANTOS, SABRINA DA SILVA. "DYNAMIC AGGREGATION OF VOLTAGE REGULATORS: ANATEM MODELS 19, 20 AND 21." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2005. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=7115@1.
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COORDENAÇÃO DE APERFEIÇOAMENTO DO PESSOAL DE ENSINO SUPERIORA agregação dinâmica de reguladores de tensão de unidades geradoras coerentes, visando o cálculo de equivalentes dinâmicos para estudos de estabilidade transitória de sistemas de energia elétrica, é o objeto desta dissertação. A metodologia empregada para o cálculo de equivalentes dinâmicos apresenta três etapas: a identificação de geradores coerentes, a redução estática da rede e a agregação dinâmica dos modelos das unidades geradoras coerentes. A agregação dinâmica de um grupo de geradores coerentes consiste em representar este grupo através de uma ou mais unidades geradoras equivalentes. As unidades geradoras coerentes podem ser representadas por diferentes modelos de máquina síncrona, regulador de tensão, estabilizador, turbina e regulador de velocidade. Haverá, então, um modelo equivalente para cada componente da unidade geradora. Os parâmetros lineares de cada modelo equivalente são ajustados numericamente através do método de Levenberg-Marquardt para resolver o problema de otimização multivariável. O objetivo principal é a determinação do melhor modelo equivalente para uma dada composição de modelos de reguladores de tensão num grupo de unidades geradoras coerentes. O sistema teste New England é utilizado para avaliar a metodologia empregada, observando-se os desempenhos dinâmicos dos equivalentes propostos. Serão considerados modelos do banco de dados de estabilidade do sistema elétrico brasileiro.
This dissertation deals with the problem of dynamic aggregation of voltage regulators of coherent generating units to calculate dynamic equivalents for power system transient stability studies. The methodology used to calculate coherencybased dynamic equivalents has three basic steps: the identification of the coherent groups of generating units, the static reduction of the external network and the dynamic aggregation of coherent generating unit models. The dynamic aggregation of a group of coherent generating units consists of the representation of this group by one or more equivalent generating units. The coherent generating units can be represented by different models of synchronous machine, voltage regulator, stabilizer, turbine and speed governor. There will be an equivalent model for each component of the generating unit. The linear parameters of the equivalent models are numerically adjusted using the Levenberg-Marquardt method in order to solve the multivariable optimization problem. The main objective is the determination of the best equivalent model for a given composition of voltage regulator models in a group of coherent generating units. The New England system is used to evaluate the dynamic performance of the equivalents. The voltage regulator models considered in this work are in the Brazilian electrical system stability database. The swing curves of the internal system generators obtained with the equivalent system are compared with those obtained with the simulation of the complete system.
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Tong, Tao. "Improving SoC Power Delivery With Fully Integrated Switched-Capacitor Voltage Regulators." Thesis, Harvard University, 2015. http://nrs.harvard.edu/urn-3:HUL.InstRepos:23845472.
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Traditional power delivery solutions f or system-on-chip (SoC) applications rely on off-chip voltage regulators. The off-chip power delivery solution is becoming a bottleneck for SoCs, due to 1) coarse voltage domain management, 2) increased cost as well as complexity of the power delivery network, and 3) high I2R loss as supply voltages scale down with the fabrication technology. One promising solution is to integrate the voltage regulators in the SoC. While fully integrated voltage regulators (FIVRs) could resolve these problems, their performance is limited by low efficiency and high chip area overhead, especially if the conversion ratio of the converter is high (≥ 4 to-1).
This thesis presents the design and implementation of two fully integrated switched-capacitor (SC) DC-DC voltage regulators. Both regulators are implemented in the SoC along with the microprocessors they deliver power to. I first present a two-stage 4-to-1 SC regulator in a flapping wing micro-robotic bee application. The regulator converts a 3.7V battery voltage down to two lower voltages (~1.8V and ~0.9V) for the rest of the circuits in the SoC. The two-stage topology and the proposed charge recycling technique improve conversion efficiency and provide very fast load regulation to handle the dynamic current fluctuation of the load circuitry. Next, I explore the power delivery architecture at the system level and propose a joint power delivery network that combines SC FIVRs with voltage stacking. Voltage stacking reduces the maximal power that the FIVRs have to provide and “hides” the FIVR conversion loss so that the latter only applies to a portion of the total power consumed by the load. The FIVRs reduce the voltage noise of the stacked voltage domains when the load in the stacked voltage domains consumes a different amount of power. To verify the benefits of this new power delivery system, a fully integrated reconfigurable SC regulator is implemented with 16 Intel microcontroller cores that are stacked in four voltage domains. The SC regulator simultaneously provides power to the four stacked voltage domains (~0.9V) from a single input voltage (~3.6V). The regulator can dynamically change its configuration to optimize its performance according to the current profiles of the stacked load. A hybrid feedback control scheme is implemented to simultaneously regulate the four stacked domains. The proposed power delivery system achieves an average efficiency of 87% and a peak efficiency of 99%. At the end of this thesis, I present my conclusion and discuss the technologies that could further improve FIVR-based power delivery systems in the future.Engineering and Applied Sciences - Engineering Sciences
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Serdyn, J. J. "Electronic voltage regulator technology for rural electrification." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/903.
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Hjartarson, Thorhallur. "Application of catastrophe theory to voltage stability analysis of power systems." Thesis, University of British Columbia, 1990. http://hdl.handle.net/2429/29623.
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In this thesis catastrophe theory is applied to the voltage stability problem in power systems. A general model for predicting voltage stability from the system conditions is presented and then applied to both a simple 2-bus explanatory power system and to a larger more realistic power system.
The model is based on the swallowtail catastrophe which with its three control variables is able to determine the voltage stability of the system. The model is derived directly from the systems equations. The voltage stability of the system at each specified system bus is determined by comparing the values of the swallowtail catastrophe control variables with those of the unique region of voltage stability. The control variables are calculated from the system operating conditions. If the control variables specify a point inside the stability region, the system is voltage stable; otherwise it is voltage unstable.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Su, Jingdong. "A heuristic slow voltage control scheme for large power systems." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Dissertations/Spring2006/j%5Fsu%5F030206.pdf.
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Bodapatti, Nageswararao. "Fuzzy-expert system for voltage stability monitoring and control." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0010/MQ36098.pdf.
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Lakkaraju, Talpasai. "Selection of pilot buses for VAR support and voltage stability risk analysis." Morgantown, W. Va. : [West Virginia University Libraries], 2006. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=4844.
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Thesis (M.S.)--West Virginia University, 2006.Title from document title page. Document formatted into pages; contains xi, 94 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 90-94).
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Markovic, Dejan. "Induced currents in gas pipelines due to nearby power lines." Access electronically, 2005. http://www.library.uow.edu.au/adt-NWU/public/adt-NWU20060807.155002/index.html.
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Islas, Ohlmaier Abraham. "Design of programmable, low power, low dropout voltage regulators for portable applications." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4689.
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As portable electronics constantly find their way into the hands of eager consumers, the
demands placed on these products and their circuits are ever increasing. More features and more
performance are continuously demanded by consumers. This feature-driven market has brought
with it several constraints on the type of circuits utilized in developing these portable devices.
Cell-Phones, PDA's, MP3 players and various other portable electronics require different
voltage levels to power different architectures that realize the many features within the device.
This work demonstrates a technique to design Programmable Low Power Low Dropout
Voltage Regulators (LDO). The LDO proposed in this research utilizes a fast-transient feedback
loop in order to improve transient response and guarantee stability in all the programmable
output levels. Specifically, the main parameters to be improved are stability over the entire load
current range, reduced overshoot and undershoot variations in transient response, reduction of
LDO deflection voltage, minimization of standby current and low voltage (Vin = 1.2V)
operation.
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Yu, Weize. "Exploiting On-Chip Voltage Regulators as a Countermeasure Against Power Analysis Attacks." Scholar Commons, 2017. http://scholarcommons.usf.edu/etd/6986.
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Non-invasive side-channel attacks (SCA) are powerful attacks which can be used to obtain the secret key in a cryptographic circuit in feasible time without the need for expensive measurement equipment. Power analysis attacks (PAA) are a type of SCA that exploit the correlation between the leaked power consumption information and processed/stored data. Differential power analysis (DPA) and leakage power analysis (LPA) attacks are two types of PAA that exploit different characteristics of the side-channel leakage profile. DPA attacks exploit the correlation between the input data and dynamic power consumption of cryptographic circuits. Alternatively, LPA attacks utilize the correlation between the input data and leakage power dissipation of cryptographic circuits.
There is a growing trend to integrate voltage regulators fully on-chip in modern integrated circuits (ICs) to reduce the power noise, improve transient response time, and increase power efficiency. Therefore, when on-chip voltage regulation is utilized as a countermeasure against power analysis attacks, the overhead is low. However, a one-to-one relationship exists between the input power and load power when a conventional on-chip voltage regulator is utilized. In order to break the one-to-one relationship between the input power and load power, two methodologies can be considered: (a) selecting multi-phase on-chip voltage regulator and using pseudo-random number generator (PRNG) to scramble the activation or deactivation pattern of the multi-phase voltage regulator in the input power profile, (b) enabling random voltage/scaling on conventional on-chip voltage regulators to insert uncertainties to the load power profile.
In this dissertation, on-chip voltage regulators are utilized as lightweight countermeasures against power analysis attacks. Converter-reshuffling (CoRe) technique is proposed as a countermeasure against DPA attacks by using a PRNG to scramble the input power profile. The time-delayed CoRe technique is designed to eliminate machine learning-based DPA attacks through inserting a certain time delay. The charge-withheld CoRe technique is proposed to enhance the entropy of the input power profile against DPA attacks with two PRNGs. The security-adaptive (SA) voltage converter is designed to sense LPA attacks and activate countermeasure with low overhead. Additionally, three conventional on-chip voltage regulators: low-dropout (LDO) regulator, buck converter, and switched-capacitor converter are combined with three different kinds of voltage/frequency scaling techniques: random dynamic voltage and frequency scaling (RDVFS), random dynamic voltage scaling (RDVS), and aggressive voltage and frequency scaling (AVFS), respectively, against both DPA and LPA attacks.
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Gu, Wei. "Low voltage regulator modules and single stage front-end converters." Doctoral diss., University of Central Florida, 2001. http://digital.library.ucf.edu/cdm/ref/collection/RTD/id/10000.
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University of Central Florida College of Engineering ThesisEvolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding IGHz. New high performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/us slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response.
Ph.D.
Doctorate;
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering and Computer Science
124 p.
xii, 124 leaves, bound : ill. ; 28 cm.
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Law, Yiu-yip Charles, and 羅耀業. "Loss analysis of a stepping inductor VRM converter." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2003. http://hub.hku.hk/bib/B29477918.
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Dike, Damian Obioma. "Index-based reactive power compensation scheme for voltage regulation a dissertation presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=76&did=1919277961&SrchMode=1&sid=1&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1265041751&clientId=28564.
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Beckers, Peter C. "Design of a Self Regulated and Protected Electrification Transformer." Thesis, Link to the online version, 2007. http://hdl.handle.net/10019/335.
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Zhang, Xin. "Fully Distributed Control and Its Analog IC Design For Scalable Multiphase Voltage Regulators." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/29576.
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Modern microprocessors require low supply voltage (about 1V), but very high current (maximum current is 300A in servers, 100A in desktop PCs and 70A in notebook PCs), and tighter voltage regulation. However, the size of a CPU Voltage Regulator (VR) needs to be reduced. To achieve much higher power density with decent efficiency in VR design is a major challenge. Moreover, the CPU current rating can vary from 40A to 300A for different kinds of computers, and CPU power supply specifications change quickly even for the same type of computers. Since the maximum power rating of one channel converter is limited, the VR channel number may vary over a large range to meet VR specifications. Traditionally, VR design with different channel numbers needs different types of VR controllers. To reduce the developing cost of different control ICs, and to maximize the market share of one design, scalable phase design based on the same type of IC is a new trend in VR design.
To achieve higher power density and at the same time to achieve scalable phase design, the concept of Monolithic Voltage Regulator Channel (MVRC) is introduced in this dissertation. MVRC is a power IC with one channel converter's power MOSFETs, drivers and control circuitries monolithically integrated based on lateral device technology and working at high frequency. It can be used alone to supply a POL (Point of Load). And without the need for a separate master controller, multiple MVRC chips can be paralleled together to supply a higher current load such as a CPU.
To make MVRC a reality, the key is to develop a fully distributed control scheme and its associated analog IC circuitry, so that it can provide control functions required by microprocessors and the performance must be equal or better than a traditional a centralized VRM controller. These functions includes: multiphase interleaving, Adaptive Voltage Position (AVP) and current sharing.
To achieve interleaving, this dissertation introduces a novel distributed interleaving scheme that can easily achieve scalable phase interleaving without channel number limitation. Each channel's interleaving circuitry can be monolithically integrated without any external components. The proposed scheme is verified by a hardware prototype. The key building block is a self-adjusting saw-tooth generator, which can produce accurate saw-tooth waveforms without trimming. The interleaving circuit for each channel has two self-adjusting saw-tooth generators. One behaves as a Phase Lock Loop to produce accurate phase delay, and the other produces carrier signals.
To achieve Adaptive Voltage Position and current sharing, a novel distributed control scheme adopting the active droop control for each channel is introduced. Verified by hardware testing and transient simulations, the proposed distributed AVP and current sharing control scheme meets the requirements of Intel's guidelines for today and future's VR design. Monte Carlo simulation and statistics analysis show that the proposed scheme has a better AVP tolerance band than the traditional centralized control if the same current sensing scheme is used, and its current sharing performance is as good as the traditional control.
It is critical for the current sensing to achieve a tight AVP regulation window and good current sharing in both the traditional centralized control scheme and the proposed distributed control scheme. Inductor current sensing is widely adopted because of the acceptable accuracy and no extra power loss. However, the Signal-to-Noise Ratio (SNR) of the traditional inductor current sensing scheme may become too small to be acceptable in high frequency VR design where small inductor with small DCR is often adopted. To improve the SNR, a novel current sensing scheme with an accurate V/I converter is proposed. To reduce the complexity of building an accurate V/I converter with traditional Opamps, an accurate monolithic transconductance (Gm) amplifier with a large dynamic range is developed. The proposed Gm amplifier can achieve accurate V/I conversion without trimming.
To obtain further verification, above proposed control schemes are monolithically integrated in a dual channel synchronous BUCK controller using TSMC BiCMOS 0.5um process. Testing results show that all the proposed novel analog circuits work as expected. System testing results show good interleaving, current sharing and AVP performance. The silicon size of each channel is 1800×1000um².
With proposed current sensing, interleaving, AVP and current sharing, as well as their associated analog IC implementations, the technical barriers to develop a MVRC are overcome. MVRC has the potential to become a generic power IC solution for today and future POL and CPU power management.
The proposed distributed interleaving, AVP and current sharing schemes can also be used in any cellular converter system. The proposed analog building blocks like the self-adjusting saw-tooth generator and the accurate transconductance amplifier can be used as basic building blocks in any DC-DC controller.Ph. D.
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Bari, Syed Mustafa Khelat. "A Novel Inverse Charge Constant On-Time Control for High Performance Voltage Regulators." Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/82510.
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One of the fundamental characteristics of the microprocessor application is its property of dynamic load change. Although idle most of the time, it wakes up in nanoseconds to support sudden workload demands, which are becoming increasingly severe in today's multi-core processors with large core count. From the standpoint of its voltage regulator (VR) design, it must have very good efficiency at light loads, while also supporting a very fast transient response. Thus, the variable-frequency constant on-time current-mode (COTCM) control scheme is widely used in the VRs, as it can automatically reduce its switching frequency during light-load conditions. But, from transient point of view, it has some limitations in response to heavy-load demands by microprocessors; this is resolved by adding different nonlinear controls in state-of-the-art control schemes. These nonlinear controls are difficult to optimize for the widely variable transient conditions in processors. Another major issue for this ripple-based COTCM control is that when the combined inductor-current ripple in multiphase operation becomes zero because of the ripple-cancellation effect, COTCM loses its controllability. Therefore, the goal of this research is to discover a new adaptive COT control scheme that is concurrently very efficient at light-load conditions and also provides a fast and optimized transient response without adding any nonlinear control; hence providing a complete solution for today's high-performance microprocessors.
Firstly, the overview of state-of-the-art COTCM control is discussed in detail, and its limitations are analyzed. Analysis shows that one issue plaguing the COTCM control is its slow transient response in both single and multiphase operation. In this context, two methods have been proposed to improve the transient performance of conventional COTCM control in single and multiphase operations. These two methods can effectively reduce the output capacitor count in system, but the ripple-cancellation and phase overlapping issues in multiphase operation are yet to be improved. This provides motivation to search for a new COT control technique that can resolve all these problems together.
Therefore, a new concept of inverse charge constant on-time (IQCOT) control is proposed to
replace the conventional ripple-based COTCM; the goals are to improve noise immunity at the ripple-cancellation point without adding any external ramp into the system, and to improve the load step-up transient performance in multiphase operation by achieving natural and linear pulse overlapping without adding any nonlinear control. Additionally, the transient performance of the proposed IQCOT has been further improved by naturally increasing or decreasing the TON time during the load step-up or step-down transient period without adding any nonlinear control. As this transient property is inherent in proposed IQCOT control, it is adaptive to the widely variable transient requirements of processors, and always produces an optimized transient response.
In order to design the proposed control with high bandwidth for supporting fast transient response, an accurate high-frequency small-signal model needs to be derived. Therefore, a high-frequency model for the proposed IQCOT control is derived using the describing function method. The model is also verified by simulation and hardware results in different operating conditions. From the derived model it is found that the quality factor (Q) of one double-pole set varies with changes in duty cycle. To overcome this challenge, an auto-tuning method for Q-value control is also proposed in this dissertation.Ph. D.
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Souvignet, Thomas. "Contribution to the design of switched-capacitor voltage regulators in 28nm FDSOI CMOS." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0043/document.
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Les appareils multimédias portables nécessitent toujours plus d'innovation pour satisfaire les besoins des utilisateurs. Les fabricants de système-sur-puces font donc face à une forte demande en capacité de calcul jusqu'à lors réservée aux ordinateurs de bureau. Ce transfert de performance se répercute inévitablement sur la consommation de ces appareils alors que dans le même temps la capacité des batteries n'est pas en mesure de répondre à cet accroissement. De nombreux compléments matériels et logiciels sont mis en places afin d'économiser l'énergie au maximum sans toutefois dégrader les performances. La modulation de la fréquence de fonctionnement et de la tension d'alimentation est certainement la plus efficace mais reste néanmoins limitée par les coûts et les contraintes d'encombrement exigées par la taille des appareils. La réponse à un tel problème passe nécessairement par l'intégration d'une partie de l'alimentation dans la puce. La conversion DC-DC basée sur des convertisseurs à capacités commutées est prometteuse car elle permet de garder un maximum de compatibilité avec les process CMOS actuels. Cette thèse explore donc la conception d'une architecture d'alimentation utilisant des convertisseurs à capacités commutées. Un étage de puissance avec une tension d'entrée est de 1.8 V et des ratios programmables permet d'obtenir le rendement maximum pour une plage de tension de sortie allant de 0.3 à 1.2 V. La tension de sortie peut varier en fonction du point de fonctionnement requit par le système. Afin d'assurer le maximum de compatibilité avec la conception du circuit numérique à alimenter, une architecture modulaire basée sur les capacités MIM est privilégiée. Les capacités sont placées au dessus de la fonction numériques et les interrupteurs de puissance sont insérés à sa périphérie. Cette architecture permet également d'entrelacer les cellules de conversion afin de réduire l'ondulation de la tension de sortie. La fréquence de commutation du convertisseurs est communément utilisée pour réguler la tension de sortie et des stratégies de contrôles linéaires et non linéaires sont donc explorées. Un prototype de convertisseur présentant une densité de puissance de 310mW/mm2 pour un rendement de 72.5% a été fabriqué dans la technologie 28nm FDSOI de STMicroelectronics. La surface requise pour le convertisseur nécessite que 11.5% de la surface du circuit à alimenter. La méthodologie de conception du convertisseur a finalement été appliquée à un régulateur de tension dans le domaine négatif pour des applications de polarisation de caisson à basse consommationMobile and multimedia devices offer more innovations and enhancements to satisfy user requirements. Chip manufacturers thus propose high performances SoC to address these needs. Unfortunately the growth in digital resources inevitably increases the power consumption while battery life-time does not rise as fast. Aggressive power management techniques such as dynamic voltage and frequency scaling have been introduced in order to keep competitive and relevant solutions. Nonetheless continuing in this direction involves more disruptive solutions to meet space and cost constraints. Fully integrated power supply is a promising solution. Switched-capacitor DC-DC converters seem to be a suitable candidate to keep compatibility with the manufacturing process of digital SoCs. This thesis focuses on the design of an embedded power supply architecture using switched-capacitor DC-DC converters.Addressing a large range of output power with significant efficiency leads to consider a multi-ratio power stage. With respect to the typical digital SoC, the input voltage is 1.8 V and the converter is specified to deliver an output voltage in the 0.3-1.2 V range. The reference voltage is varying according to typical DVFS requirements. A modular architecture accommodates the digital design flow where the flying capacitors are situated above the digital block to supply and the power switches are located as an external ring. Such an architecture offers high flexibility. Interleaving strategy is considered to mitigate the output voltage ripple. Such a converter admits the switching frequency as a control variable and linear regulation and hysteretic control are analyzed. A prototype has been fabricated in 28nm FDSOI technology by STMicroelectronics. A power density of 310 mW/mm2 is achieved at 72.5% peak efficiency with a silicon area penalty of 11.5% of the digital block area. The successful design methodology has been also applied to the design of a negative SC converter for body-biasing purpose in FDSOI. Simulation results demonstrate a strong interest for low power application
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Abrie, Dewald Johan. "Supervisory control and sliding mode control of a medium voltage direct AC-AC electronic voltage regulator." Thesis, Stellenbosch : Stellenbosch University, 2013. http://hdl.handle.net/10019.1/80166.
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Thesis (MScEng)--Stellenbosch University, 2013.ENGLISH ABSTRACT: As control problems become more and more complex, techniques are required that surpass the capabilities of simple controllers that are linearized about certain parametric set points. Controllers that can operate over a large range of model parameter variations and even controllers that are largely model-independent are becoming more valuable and necessary. In this control application, voltage regulation is done on a direct AC-AC medium voltage regulator, making use of a type of regulated autotransformer configuration. The fifth order system is shown to be prone to oscillations on the input bus. This, together with the control requirement of robustness to load variations, provides a challenging control problem that is rarely addressed in literature. This thesis solves the control problem by means of applying sliding mode control on voltage regulator module level, and supervisory control on system level.
AFRIKAANSE OPSOMMING: Soos die soeke na oplossings vir hedendaagse beheer probleme al hoe meer uitdagend raak, word die behoefte vir model onafhanklike en robuuste beheerders dienooreenkomstig groter. Eenvoudige beheerders wat gelineariseer is om ’n parametriese werkpunt raak ondoeltreffend vir vandag se vereistes vir doeltreffende beheer ongeag van parametriese veranderinge. In hierdie tesis word spanning regulasie toegepas deur ’n direkte WS-na-WS medium spanning reguleerder in te span. Hierdie toestel maak gebruik van ’n tipe van outotransformator opstelling waar die sekondêre wikkelings gereguleer word deur die skakelaksie van die drywingselektroniese regulasie modules. Die vyfde-orde stelsel se intree bus is geneigd om onstabiel te raak, en moet dus aktief gedemp word terwyl die uitreespanning reguleer word. Die vereiste dat die beheer boonop robuus ten opsigte van las veranderings moet wees maak hierdie probleem ’n monster van ’n uitdaging wat skaars in die literatuur aangeraak is. Hierdie tesis los die probleem van robuuste beheer op deur glymodus beheer toe te pas op reguleerder module vlak, en ook deur toesighoudende beheer op stelsel vlak toe te pas.
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Šojdr, Marek. "Návrh nízko-příkonového interního napěťového regulátoru pro automobilové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399493.
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This master’s thesis deals with the design of integrated voltage regulator. Topologies of linear voltage regulators and their stability are discussed. Part of the thesis deals with description and simulation of blocks of selected regulator topology. The thesis describes the difficulties of integrated circuit design in the automotive industry. The electrical scheme of the designed regulator is explained. The work also focuses on the stability of designed regulator. Then presents simulations. It discusses the layout of integrated circuits and the designed voltage regulator.
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Ndimurwimo, Alexis. "Optimised small scale reative compensation for Eskom's Albany-Wesley 66/22Kv transmission system." Thesis, Nelson Mandela Metropolitan University, 2012. http://hdl.handle.net/10948/d1008156.
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Reactive power compensation, as generated by capacitors, has been used to mitigate the constraints of power transmission and improve the power transfer of the transmission system of the South African power utility, Eskom‟s 66/22kV Albany-Wesley transmission system. An investigation was carried out on a number of current compensation schemes, and their operations, by means of load flow analysis. Different capacitor qualities and technologies were applied to alter the transmission line characteristics that resulted in acceptable voltage regulation. This resulted in easing the load on the lines and transformers and hence reducing line losses. For long transmission lines, utilities need voltage support, as provided for by different voltage compensators, to keep the terminal voltage within standard voltage regulation, and meet the designed power demand. The approach to large and small scale compensation was tested and the outcomes revealed distinct patterns that were used to confirm the hypothesis and improve the transfer of power. The templating temperature and thermal perspective as used by Eskom on line design was discussed and used to design a new transmission line. Load flow solutions were also used to plan and design the optimised transmission system as well as to determine the specification and location of the compensating capacitor banks. Capacitor banks, as a source of reactive power, were used to model the compensation in this research. Electrical protection and faults associated with the capacitors banks were discussed, as prevention to total blackout or load shedding on the transmission line in case of established contingency. Long term investment plans, to meet future electricity demands, require substantial investment hence a financial survey was carried out. Finally this dissertation selects a viable solution to meet the electrical power demands and then recommends a way forward for the Eskom‟s 66/22kV Albany-Wesley line.
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Kim, Wonyoung. "Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators." Thesis, Harvard University, 2012. http://dissertations.umi.com/gsas.harvard:10721.
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Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time \((<0.1V/\mu s)\). This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities.Engineering and Applied Sciences
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Adewole, Adeyemi Charles. "Voltage stability assessment and wide area protection/control using synchrophasor measurements." Thesis, Cape Peninsula University of Technology, 2016. http://hdl.handle.net/20.500.11838/2380.
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Thesis (DTech (Electrical Engineering))--Cape Peninsula University of Technology, 2016.Electric power systems are being operated closer to their designed stability limits due to the constraints caused by the continuous increase in system loading, and the lack of new power stations and transmission network infrastructure to support this increase in system loading. This coupled with the practice of long distance bulk power transmission and cascading contingencies, makes system instability and consequently blackouts inevitable. In such scenarios, system instabilities like voltage instability becomes a serious threat to the secure operation of the power system, and voltage collapse (system-wide blackouts) are prone to occur. This is often compounded by the unavailability of real-time system measurements for situational awareness from the existing Supervisory Control and Data Acquisition (SCADA)/Energy Management System (EMS) platforms which are usually based on unsynchronized SCADA measurements with a slow reporting rate of 1 measurement every 2-10 seconds. This Doctoral thesis proposes non-iterative algorithms and methods of solution based on the IEEE C37.118 synchrophasor measurements from Phasor Measurement Units (PMUs) with a high reporting rate of up to 200 measurements every second (200 fps) for voltage stability assessment and automated wide area Centralised Protection/Control (CPC) against catastrophic voltage instabilities/blackouts in power systems. Extended formulations are proposed for the Optimal Placement of PMUs (OPP) in power systems with respect to voltage stability assessment. The impact of zero injection buses, critical buses, and PMU redundancy is considered in the formulation of the OPP problem solution. The extended formulations made use of Binary Integer programming (BIP) and Modal Participation Factors (MPFs) derived from the eigenvalues of the power flow Jacobian.
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Khajjayam, Ramesh Kumar V. "Impact of optimally placed VAR support on electricity spot pricing." Morgantown, W. Va. : [West Virginia University Libraries], 2006. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=4895.
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Thesis (M.S.)--West Virginia University, 2006.Title from document title page. Document formatted into pages; contains x, 105 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 99-105).
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Begovic, Miroslav M. "Analysis, monitoring and control of voltage stability in electric power systems." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54490.
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The work presented in this text concentrates on three aspects of voltage stability studies: analysis and determination of suitable proximity indicators, design of an effective real-time monitoring system, and determination of appropriate emergency control techniques. A simulation model of voltage collapse was built as analytical tool on 39-bus, 10-generator power system model. Voltage collapse was modeled as a saddle-node bifurcation of the system dynamic model reached by increasing the system loading. Suitable indicators for real-time monitoring were found to be the minimum singular value of power flow Jacobian matrix and generated reactive powers. A study of possibilities for reducing the number of measurements of voltage phasors needed for voltage stability monitoring was also made. The idea of load bus coherency with respect to voltage dynamics was introduced. An algorithm was presented which determines the coherent clusters of load buses in a power system based on an arbitrary criterion function, and the analysis completed with two proposed coherency criteria. Very good agreement was obtained by simulation between the results based on accurate and approximate measurements of the state vector. An algorithm was presented for identification of critical sets of loads in a voltage unstable power system, defined as a subset of loads whose changes have the most pronounced effect on the changes of minimum singular value of load flow Jacobian or generated reactive powers. Effects of load shedding of critical loads were investigated by simulation and favorable results obtained. An investigation was also done by sensitivity analysis of proximity indicators of the effects that locations and amounts of static var compensation have on the stability margin of the system. Static compensation was found to be of limited help when voltage instabilities due to heavy system loading occur in power systems. The feasibility of implementation of the analyses and algorithms presented in this text relies on development of a feasible integrated monitoring and control hardware. The phasor measurement system which was designed at Virginia Polytechnic institute and State University represents an excellent candidate for implementation of real-time monitoring and control procedures.Ph. D.
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Kundy, Beda Jerome. "Probabilistic analytical methods for evaluating MV distribution networks including voltage regulating devices." Thesis, Stellenbosch : Stellenbosch University, 2001. http://hdl.handle.net/10019.1/52414.
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Thesis (PhD)--Stellenbosch University, 2001.ENGLISH ABSTRACT: Accurate load models are required for the computation of load flows in MV distribution networks. Modem microprocessors in recent times enable researchers to sample and log domestic loads. The findings show that they are stochastic in nature and are best described by a beta probability distribution. . In rural areas two different load types may be present. Such loads are domestic and pump loads, the latter may be modelled as constant P - Q loads. An analytical tool for computing voltage regulation on MV distribution networks for rural areas feeding the mentioned loads is therefore required. The statistical evaluation of the consumer voltages requires a description of load currents at the time of the system maximum demand. To obtain overall consumer voltages at any specified risk for the two types of the loads, the principle of superposition is adopted. The present work deals with conventional 22kV three-phase distribution (te:. - te:.) connected networks as used by ESKOM, South Africa. As the result of the connected load, MV networks can experience poor voltage regulation. To solve the problem of voltage regulation, voltage regulators are employed. The voltage regulators considered are step-voltage regulators, capacitors and USE (Universal Semiconductor Electrification) devices. USE devices can compensate for the voltage drops of up to 35% along the MV distribution network, thus the criteria for the application of the USE devices is also investigated. The load currents are treated as signals when assessing the cost of distribution system over a period of time due to power losses. The individual load current signal is modelled by its mean and standard deviation. The analytical work for developing general expressions of the total real and total imaginary components of branch voltage drops and line power losses in single and three-phase networks without branches are presented. To deal with beta-distributed currents on MV distribution networks, new scaling factors are evaluated at each node. These new scaling factors are derived from the distribution transformer turns ratio and the deterministic component of the statistically distributed load currents treated as constant real power loads. In the case of an individual load current signal, the transformation ratio is evaluated from the distribution transformer turns ratio and the average value of the· signal treated as constant real power load. The evaluation of the consumer voltage percentile values can be accurately evaluated up to 35% voltage drop. This is possible by the application of the expanded Taylor series, using the first three terms. The coefficients of these three terms were obtained using a search engine imbedded in the probabilistic load flow. The general expressions for evaluating the overall consumer voltages due to statistical and non-statistical loads currents are also given. These non-statistical currents may be due to constant P - Q loads, line capacitance and the modeling of voltage regulators. The Newton-Raphson algorithm is applied to perform a deterministic load flow on singlephase networks. A backward and forward sweep algorithm is applied to perform a deterministic load flow on single and three-phase systems. A new procedure for modelling step-voltage regulators in three-phase (te:. - te:.) connected networks is outlined. Specifying a transformation ratio of 1.1 and 1.15 respectively, identifies the open-delta or closed-delta configuration for three-phase networks. The algorithms and the developed general expressions for single and three-phase networks without branches are presented in this work. A new algorithm is developed to enable the developed general expressions to be applied to practical MV distribution networks. The algorithms were tested for their accuracy by comparing the analytical results with Monte Carlo simulation and they compared well. An illustrative example to show the application of the present work on a practical MY distribution networks is presented. A criterion for the application of the USE devices is outlined. It is anticipated that, the work presented in this thesis will be invaluable to those involved in the design of MY distribution systems in developing countries.
AFRIKAANSE OPSOMMING: Akkurate lasrnodelle word benodig vir drywingsvloei analises in MV distribusiestelsels. As gevolg van nuwe digitale verwerkers is dit deesdae moontlik om huishoudelike laste te monitor. Die lasdata dui daarop dat laste stochasties is en kan met behulp van die Beta verdeling beskryf word. In landelike gebiede is daar twee tipes laste. Hulle is eendersyds huishoudelike laste en andersyds pomp-tipe laste wat as konstante P-Q laste beskou kan word. Dit is dus belangrik om toepaslike analitiese metodes te gebruik om die spanningsvalle by hierdie laste te bereken met inagname van die las-tipes. By die statistiese berekening van die verbruiker se spanning moet 'n statistiese model van die lasstroom verskaf word op die tydstip van maksimum aanvraag. Daarna moet die prinsiep van superposissie gebruik word om die spannings by verskeie nodes by 'n gespesifiseerde vertrouensinterval te bepaal. Hierdie proefskrif is gebaseer op konvensionele 22kV, drie fase distribusie (delta na delta) netwerke, soos deur Eskom, Suid Afrika gebruik. Hierdie stelsels ondervind dikwels nadelige spanningsvlakke en spanningsreëlaars word derhalwe aangewend. Hierdie reëlaars is gewoonlik van tap-tipe of daar kan ook gebruik gemaak word van kapasitore en ook elektroniese reëlaars soos die USE tipe toestelle. Laasgenoemde kan op LV vir spanningsvalle tot 35% kompenseer. In hierdie werk word die werkdrywing verliese in die geleiers bereken met behulp 'n seinmodel van die lasstrome. Die individuele lasstrome word by wyse van gemiddeldes en variasies beskryf. Om die algemene algoritmes vir die berekening van die reële en imaginêre spanningsvalle, asook die verliese in enkelfase en driefase stelsels daar te stel word aanvanklik gebruik gemaak van stelsels sonder vertakkings. Om die statistiese lasbeskrywing op die laagspanningskant na die MV vlak oor te dra word van nuwe skaalfaktore gebruik gemaak. Hierdie faktore word bereken op die basis van die transformator se verhouding en die deterministiese komponent van die statistiese verspreide lasstrome, as konstante reële drywingslaste beskou. Met die ontwikkelde metode kan die verbruiker se spanning by 'n gegewe vertrouensinterval akkuraat bereken word vir spanningsvalle tot 35%. Dit word moontlik gemaak deur die Taylor-reeks tot drie terme toe te pas. Daar moet egter gebruik gemaak word van toepaslike koëffisiënte wat bepaal word deur 'n geprogrammeerde soektog. 'n Algemene stel vergelykings om die spanning by enige verbruiker te bereken, ongeag die topologie van die netwerk, word ook gegee. Die Newton-Raphson metode word aangewend om die deterministiese drywingsvloei op enkelfase stelsels te bereken. A truwaartse-voorwaartse metode is gebruik om die drywingsvloei te bepaal vir driefase stelsels. 'n Nuwe prosedure is ontwikkel vir die modellering van die spanningsreëlaars in driefase, delta-delta netwerke. Deur gebruik te maak van 'n transformatorverhouding van 1.1 of 1.15 kan die oop-delta of toe-delta netwerke voorgestel word. 'n Nuwe algoritme is ontwikkelom multi-vertakkings in 'n netwerk te hanteer. Al die prosedures is deeglik met behulp van Monte Carlo simulasies getoets en die resultate is heel bevredigend. Om die metodes te illustreer word 'n gevallestudie ingesluit waar die metodes gebruik word om 'n netwerk te evalueer met en sonder die sogenaamde USE toestelle. Kriteria vir die aanwending van hierdie toerusting word voorgestel. Daar word verwag dat die werk soos in hierdie proefskrifuiteengesit is die ontwerp van MV distribusiestelsels, veral in ontwikkelende lande, heelwat sal verbeter.
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Jacobs, D. M. (Danver Maxwill). "Voltage control of medium to high power three-phase inverter supply systems." Thesis, Stellenbosch : Stellenbosch University, 2001. http://hdl.handle.net/10019.1/52608.
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Thesis (MScEng)--University of Stellenbosch, 2001.ENGLISH ABSTRACT: In this thesis a new voltage control method is developed for a three-phase inverter supply system. The inverter supply system consist of a Permanent Magnet Generator, a three-phase rectifier, a three-phase inverter plus LC-filter and a three-phase transformer in series. This system supplies power to a network or to a stand-alone load. The main focus of this thesis is on the control aspects of the inverter and the LC-filter. Different voltage control systems are investigated and compared to each other. From these methods the proposed voltage control method is developed where only the output voltages are measured to establish good voltage control. All these voltage control methods are also simulated with a software package. The proposed voltage control method compares very well with other voltage control methods. The results that are obtained in the simulations are satisfactory. The proposed voltage control method is also implemented in an 8 kW laboratory scale model and, again, very good practical results are obtained. A TMS320F240 nsp controller is used to implement the proposed voltage control method. The controller compensates well for load steps, and these results compare well to an alternative voltage control method, which was also evaluated practically.
AFRIKAANSE OPSOMMING: In hierdie tesis IS 'n nuwe spanningsbeheermetode ontwikkel VIr 'n drie-fase wisselrigter kragtoevoerstelsel. Die wisselrigter kragtoevoerstelsel bestaan uit 'n Permanent Magneet Generator, 'n drie-fase gelykrigter, 'n drie-fase wisselrigter plus Le-filter, en 'n drie-fase transformator in serie. Hierdie stelsel voorsien krag aan 'n netwerk sowel as aan 'n alleenstaande las. Die hooffokus van hierdie tesis is op die beheeraspekte van die wisselrigter en Le-filter. Verskillende spanningsbeheermetodes is deeglik ondersoek en vergelyk met mekaar. Uit hierdie metodes is dan die voorgestelde beheermetode ontwikkel waar slegs die uittreespanning gemeet word om goeie spanningsbeheer te kan doen. Al hierdie spanningsbeheermetodes is dan gesimuleer met 'n sagteware pakket. Die voorgestelde spanningsbeheermetode vergelyk baie goed met die ander spanningsbeheermetodes. Die resultate verky in die simulasies is ook baie bevredigend. Die voorgestelde beheermetode is ook geïmplementeer op 'n 8 kW laboratorium skaalmodel en weereens is baie goeie praktiese resultate verky. 'n TMS320F240 DSP-beheerder is gebruik om die voorgestelde beheermetode mee te implementeer. Die beheerder kompenseer baie goed vir lastrappe en vergelyk ook goed met 'n ander spanningsbeheermetode wat prakties ge-evalueer is.
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Rossouw, Frans Jacobus. "Analysis of voltage regulation and network support technologies." Thesis, Stellenbosch : Stellenbosch University, 2000. http://hdl.handle.net/10019.1/51588.
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Thesis (MEng)--University of Stellenbosch, 2000.ENGLISH ABSTRACT: Recent advances in semiconductor device development pushed a large number of network devices onto the market. These devices can solve network problems more effectively and economically than ever before. Network planners need tools to analyse and implement such devices to help solve the largest network problem in South Africa: voltage regulation. Rural networks experience the majority of voltage-regulation problems in South Africa. The networks are long sub-transmission and reticulation networks and are modelled by two generic networks, namely a radial network and a two-source ring network. The equations describing voltage regulation for the generic networks are developed and implemented in PSAT, a software analysis tool. The voltage regulation for two case studies that represent the two generic networks are analysed. Four generic network devices are defined and various control methods for these devices are developed to solve the network problem. The aim of PSAT is to help the network planner to quickly evaluate a number of possible solutions and to choose the best solution for further studies. This is demonstrated with the aid of the case studies. PSAT provides a sturdy platform on which future developments, such as stability analyses, can be built. However, PSAT can already function as a stand-alone analysis tool to solve voltage regulation as a network problem.
AFRIKAANSE OPSOMMING: Onlangse vooruitgang in halfgeleier ontwikkeling het 'n groot aantal netwerktoestelle op die mark geplaas. Hierdie toestelle kan netwerk probleme doeltreffender en meer ekonomies oplos as ooit vantevore. 'n Behoefte aan 'n pakket wat netwerkbeplanners in staat stelom die netwerktoestelle te analiseer, is geïdentifiseer. So 'n pakket sal hulle help om die vernaamste netwerkprobleem in Suid-Afrika, nl. spanningsregulasie, op te los. Die oorgrote meerderheid spanningsregulasie probleme word op die platteland ondervind. Plattelandse netwerke word gekenmerk deur lang sub-transmissie en retikulasie netwerke. Hierdie netwerke word met behulp van twee generiese netwerke gemodelleer. 'n Radiale netwerk en 'n dubbelbron ringnetwerk word aangewend om enige plattelandse netwerk te analiseer. Vergelykings is vir spanningsanalise ontwikkel en in PSAT, 'n analitiese sagteware pakket, geïmplementeer. Twee gevallestudies is gedoen om die twee netwerke afsonderlik voor te stel en die vergelykings van PSAT te evalueer. Alle netwerktoestelle is in een van vier generiese kategorieë geklassifiseer. Modelle is vir elk van die kategorieë ontwikkel vtr spanningsregulasie analise. Die doel van PSAT is om die netwerk beplanner te help om vinnig en effektief soveel moontlik opsies te ondersoek as oplossings vir 'n spesifieke netwerk probleem. PSAT is reeds 'n alleenstaande pakket wat in die toekoms uitgebrei sal word om na die analise van stabilitietsprobleme te kyk.
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Twining, Erika. "Voltage compensation in weak distribution networks using shunt connected voltage source converters." Monash University, Dept. of Electrical and Computer Systems Engineering, 2004. http://arrow.monash.edu.au/hdl/1959.1/9701.
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Welgemoed, Frans Marx. "Shunt reactive compensation of voltage dips and unbalance." Thesis, Stellenbosch : University of Stellenbosch, 2010. http://hdl.handle.net/10019.1/5315.
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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010.ENGLISH ABSTRACT: The use of power electronic converters provides a more efficient, accurate and dynamic solution to reactive compensation. In this thesis the application of power electronic converters to shunt reactive compensation will be discussed. In particular voltage dips and voltage unbalance are considered as both can be mitigated by means of shunt reactive compensation. A pre-existing uninterruptible power supply is adapted to operate as a shunt reactive compensator. The uninterruptible power supply consists of a 250 kVA three phase voltage source inverter. The modifications are limited to software and control algorithms that do not alter the normal operation of the uninterruptible power supply. Control algorithms are designed and discussed in detail. A typical double loop control strategy is implemented on the power electronic converter. The inner loop consists of a dead-beat current controller. The outer loop consists of three proportional and integral controllers controlling the DC-bus voltage, AC voltage and voltage unbalance respectively. Voltage dips and unbalance are compensated for using only reactive power. Focus is placed on producing a result can be used easily in practice.
AFRIKAANSE OPSOMMING: Drywings elektroniese omsetters wat gebruik word vir newe reaktiewe kompensasie lewer meer effektiewe, akkurate en dinamiese resultate. In hierdie tesis word die toepassing van drywings elektroniese omsetters vir newe reaktiewe kompensasie bespreek. Daar word meer spesifiek na spannings duike en spannings wanbalans gekyk aangesien albei met newe reaktiewe kompensasie verminder kan word. ’n Bestaande nood kragbron is aangepas om as n newe reaktiewe kompenseerder te funksioneer. Die nood kragbron bestaan hoofsaaklik uit ’n 250 kVA drie fase omsetter spanningsbron. Die aanpassings is beperk tot sagteware en beheer algoritmes wat nie die oorspronklike funksionaliteit van die nood krag bron beinvloed nie. Beheer algoritmes word ontwerp en deeglik bespreek. ’n Tipiese dubbel lus beheer strategie word op die drywings elektroniese omsetter toegepas. Die binnelus bestaan uit ’n voorspellende stroom beheerder. Die buite-lus bestaan uit drie proportioneel en integraal beheerders wat onderskeidelik die GS-bus spanning, WS spanning en spanning wanbalans reguleer. Spannings duike en wanbalans is verminder deur slegs reaktiewe drywing te gebruik. Die doel was ook om ’n prakties bruikbare resultaat te lewer.
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Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.
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SOUZA, FABIO LUIZ DE. "DYNAMIC AGGREGATION OF POWER SYSTEM STABILIZER MODELS APPLIED IN VOLTAGE REGULATORS AND CALCULATION OF DYNAMIC EQUIVALENTS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 1999. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=7314@1.
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COORDENAÇÃO DE APERFEIÇOAMENTO DO PESSOAL DE ENSINO SUPERIORO cálculo de equivalentes dinâmicos baseados em coerência apresenta três etapas básicas: a identificação de geradores coerentes, a redução estática da rede e a agregação dinâmica dos modelos das unidades geradoras coerentes. Esta dissertação trata do problema da agregação dinâmica de modelos de estabilizadores aplicados em reguladores de tensão de geradores coerentes, visando o cálculo de equivalentes dinâmicos precisos para estudos de estabilidade transitória de sistemas de energia elétrica. A determinação de um critério de escolha do melhor modelo equivalente, para uma dada composição de modelos de estabilizadores num grupo de geradores coerentes, é o objetivo principal. O ajuste dos parâmetros dos modelos equivalentes de estabilizadores dos grupos coerentes é realizado, a partir das respostas em freqüência dos modelos individuais de cada grupo, utilizando-se o método de Levenberg-Marquardt, o que caracteriza um problema de otimização multivariável. O desempenho dinâmico dos equivalentes calculados com a metodologia adotada é avaliado em um sistema teste.
The calculation of coherency-based dynamic equivalents has three main steps: the identification of coherent generators, the network reduction and the dynamic aggregation of the coherent generating unit models. This dissertation deals with the problem of dynamic aggregation of power system stabilizer models to calculate coherency-based dynamic equivalents for power system transient stability studies. The determination of a criteria to choose the best equivalent model for a given composition of power system stabilizer models in a group of coherent generators is the main objective. The parameters of the power system stabilizer equivalent models for each group of coherent generating units are adjusted to match the frequency response of the individual models. This multivariable optimization problem is solved using the Levenberg-Marquardt method. The dynamic performance of the equivalents is evaluated in a test system.