Relevant bibliographies by topics / Voltage sense amplifier

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Voltage sense amplifier'

Author: Grafiati
Published: 3 June 2025
Last updated: 19 July 2025

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Journal articles on the topic "Voltage sense amplifier"

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Tiwari, Nitendra kumar. "Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations." Journal of Futuristic Sciences and Applications 5, no. 2 (2022): 31–37. http://dx.doi.org/10.51976/jfsa.522205.

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MTCMOS (Multi-Threshold CMOS), sleepy stack, sleepy keeper, and footer stack are examples of low power saving techniques incorporated into the core gpdk 90nm technology papers used in the proposed study using Cadence. The main focus of these tests is the power consumption of various sense amplifier circuits. The simulation results show that the charge-transfer sense amplifier uses much less energy than voltage and current sense amplifiers. The present mode detecting amplifier’s power consumption can be decreased by up to 98 percent by using MTCMOS technology.
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Apeksha Garg. "Effect of Green Logistics on Designing of Single Bit Cache Memory Architecture." Communications on Applied Nonlinear Analysis 32, no. 3s (2024): 663–80. https://doi.org/10.52783/cana.v32.2725.

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The international economy's fast expansion has made logistics more crucial in addressing shifting societal demands and has also worsened sustainability and environmental issues. With an emphasis on entering and leaving logistics, this study examines the long-term effects of green logistics practices. The paper creates a theoretical framework for examining the effects of green logistical practices on single-bit cache memory architectures' economic, social, and environmental performance. This paper proposes and implements a design analysis of a single-bit static random access memory voltage differential sense amplifier architecture. It uses a write driver circuit, a static random access memory, and different differential sense amplifiers, including voltage differential sense amplifiers, current differential sense amplifiers, and charge transfer differential sense amplifiers. How well different architectures perform in terms of total power consumption, static power consumption, transistor count, and sensing delay has been determined. The voltage differential sensing amplifier for single-bit static random-access memory cells utilizes the least power (13.16µW). Longer sensing delays (12.5ηs) are present in the single-bit static random-access memory cell charge-transfer differential sense amplifier design and the single-bit random-access memory cell current differential sense amplifier architecture. Techniques for power reduction have also been employed to optimize power.
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Shrivastava, Anurag, and Mohan Gupta. "Evaluation of the Core Processor Cache Memory Architecture's Performance." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 11–18. http://dx.doi.org/10.51976/jfsa.211903.

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In this study, memory architectures for single-bit caches are studied. Voltage differential sense amplifiers and charge transfer differential sense amplifiers are used to study a six-transistor static random-access memory. In a single-bit, six-transistor static random-access memory, it has been demonstrated that the voltage differential sensing amplifier uses the least power.
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Sandhya, Kalla. "Design and High Performance Evaluation of a Low Power Bit-Line SRAM PMOS Biased Sense Amplifier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 06 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem36033.

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Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.
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Zhang, Hua. "A Sense Amplifier for Low Voltage Embedded Flash Memories." Advanced Materials Research 986-987 (July 2014): 1734–37. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1734.

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A sense amplifier applied for low voltage embedded flash memories is presented. The sense amplifier uses an enhanced current sensing method allowing power supplies lower than 1.5 V to be used. The sense amplifier was implemented in a FLASH realized with a 0.13 um FLASH technology. Simulation results showed a read access time of about 25 ns with a power supply of 1.5 V, and 32ns with a power supply of 1.2V.
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Kumar Pandey, Neeraj. "IoT Systems with Low-Power SRAM Memory Architecture." Journal of Futuristic Sciences and Applications 4, no. 2 (2021): 9–15. http://dx.doi.org/10.51976/jfsa.422102.

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A quantitative and yield analysis was made and tested on a single-bit cache memory design using a range of resistor values and various sense amplifier types, such as the voltage mode differential sense amplifier (VMDSA). In a single-bit cache memory design, the voltage mode differential sense amplifier uses the least power. The low power consumption and long access times of this SRAM will be very advantageous for the Internet of Things (IoT).
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Koo, Kyung Min, Woo Young Chung, Sang Yi Lee, Gyu Han Yoon, and Woo Young Choi. "Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage." Micromachines 12, no. 10 (2021): 1145. http://dx.doi.org/10.3390/mi12101145.

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With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage, leading to sensing failure. Previous studies indicate that the threshold voltage mismatch between the paired transistors of a sense amplifier is the most critical factor. In this study, virtual wafers were generated, including statistical VT variation. Then, we numerically investigate the prediction accuracy and reliability of the offset voltage of DRAM wafers using test point measurement for the first time. We expect that this study will be helpful in strengthening the in-line controllability of wafers to secure the DRAM sensing margin.
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Shukla, Sachchida Nand, Syed Shamroz Arshad, and Geetika Srivastava. "NPN Sziklai pair small-signal amplifier for high gain low noise submicron voltage recorder." International Journal of Power Electronics and Drive Systems (IJPEDS) 13, no. 1 (2022): 11. http://dx.doi.org/10.11591/ijpeds.v13.i1.pp11-22.

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Small signal-to-noise ratio (SNR) and multiple noise sources, coupled with very weak signal amplitudes of bio signals make brain-computer interface (BCI) application studies a challenging task. The front-end recorder amplifiers receive very-weak signal (few μV) from high impedance electrodes and for efficient processing of such weak and low frequency (<1 kHz) signals a high gain amplifier with very low operating voltage and low total harmonic distortion (THD) is required. Existing amplifiers suffer from problem of high non-linearity and low common mode rejection. A good sense amplifier at predeceasing stage can solve this problem. Utilizing very high amplification factor of Sziklai Pair, this paper proposes two circuit topologies of common-emitter and common-collector negative-positive-negative (NPN) Sziklai Pair small signal amplifiers suitable for use in preamplifier stages of such signal acquisition circuit. Present study provides broad-spectrum of analysis of these amplifiers covering effect of additional biasing resistance RA, variation of ‘ideal forward maximum beta’ β, temperature dependency, noise sensitivity and phase variation. The tunable capability of first topology makes it a suitable candidate in wide variety of other applications. The first amplifier operates on very low input voltage range (0.1μV-6mV) whereas the second amplifier works on 100 μV-11 mV range of input voltage.
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Abhinav, V. Deshpande. "OFFSET REDUCTION IN THE DOUBLE TAILED LATCH-TYPE VOLTAGE SENSE AMPLIFIER." International Journal of Advanced Trends in Engineering and Technology 4, no. 2 (2019): 1–5. https://doi.org/10.5281/zenodo.3336352.

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This research paper presents an improved double tailed latch type voltage sense amplifier by using a latch load in the first stage. A latch load at the first stage provides the second stage with a large input difference voltage. Thus, completely removes the offset voltage due to the mismatch in the transistor pairs in the second stage of the Sense Amplifier. The performance of the Sense Amplifier was simulated by using the LT Spice with a threshold mismatch of 10% in between the transistor pairs of the second stage, where it achieved the offset removal at 3 GHz clock rate with V<sub>DD </sub>= 1. 2 Volts in a 90 nm CMOS technology. Since the input transistors of the first stage are in parallel with the transistor pair of the latch, it does not affect the delay.
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Nand, Deva, and Neeta Pandey. "A New Proposal for OFCC-based Instrumentation Amplifier." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (2017): 134. http://dx.doi.org/10.11591/ijece.v7i1.pp134-143.

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This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.
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Dissertations / Theses on the topic "Voltage sense amplifier"

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Hsieh, Chaung-Lin, and 謝長霖. "Charge Transfer Sense Amplifier for Low Voltage DRAM Array." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/87822834434420620688.

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碩士<br>長庚大學<br>電子工程研究所<br>93<br>Recently, the supply voltage of Giga bit-scale DRAM array has been scaled down to sub-1V. Under sub-1V array operation, the voltage difference between BL and BLB after word line activated becomes only several tens of millivolt. The small voltage difference is near the sense limit and leads to slow sensing speed. Besides, the small voltage difference is easily disturbed by noise and causes errors on read operation. To solve this problem, a charge transfer pre-amplifier scheme (CTP) was proposed. Unlike conventional voltage type sense amplifier, charge transfer sense amplifier isolates bit lines and sense nodes. After charge transfer operation, the small voltage difference between bit lines is amplified to a larger voltage difference between sense nodes. When the voltage difference between sense nodes is large enough, the conventional voltage type sense amplifier on the next stage is activated and amplifies the voltage difference to full swing. Because of the pre-amplifier operation, the voltage type sense amplifier will sense the data in memory cell rapidly and correctly. Present charge transfer sense amplifiers have long charge transfer time, and the voltage difference after charge transfer on low supply voltage (0.5V DRAM array) is not enough. Among them, some circuits architecture need either high voltage pre-charge levels or high voltage control signals. These high voltage signals are not expected to be present in low voltage DRAM array design. The proposed sense amplifier uses cross-coupled structure and boost capacitance. The combination of cross-coupled structure and boost capacitance enables the maximum voltage difference on sense nodes in a shorter time than the prior arts. Charge transfer speed and voltage difference between sense nodes after charge transfer are improved about 40.7% and 59.29%, respectively. The power delay product (PDP) is improved about 38.26%. Besides, high voltage pre-charge levels or high voltage control signals are no more needed. For these reasons, the proposed charge transfer sense amplifier is more suitable for low voltage DRAM applications.
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Gang, Yung-jin 1957. "Ultra low voltage DRAM current sense amplifier with body bias techniques." Thesis, 1998. http://hdl.handle.net/1957/33344.

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The major limiting factor of DRAM access time is the low transconductance of the MOSFET's which have only limited current drive capability. The bipolar junction transistor(BJT) has a collector current amplification factor, ��, times base current and is limited mostly by the willingness to supply this base current. This collector current is much larger than the MOSFET drain current under similar conditions. The requirements for low power and low power densities results in lower power supply voltages which are also inconsistent with the threshold voltage variations in CMOS technology, as a consequence at least pulsed body bias or synchronous body bias will probably be utilized. Given that of the CMOS body will be driven or the CMOS gate and body connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing present CMOS process technology good results can be achieved with ultra low power using gate-body connected transistors and a current sense amplifier.<br>Graduation date: 1999
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Tsou, Po-Wei, and 鄒柏瑋. "Ultra Low Voltage SRAM with Write Back Sense Amplifier Circuit Design." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/67136639646444820985.

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碩士<br>國立清華大學<br>電機工程學系<br>98<br>In our livelihood, the Static Random Access Memory (SRAM) appears in the almost electronics and it is required more area than other circuits in the SOC chip. That shows the SRAM used up the most power of a chip. So, how to solve the problem of SRAM power consumption and not to cut down the SRAM operating performance is a big challenge. The point about all problems of SRAM for reducing the power consumption is to lower the SRAM operating voltage. But, pulling down the operating voltage that made the static noise margin (SNM) of SRAM cell characteristics be smaller. This phenomenon will to cause the read half-selected disturb problem and write half-selected disturb problem when SRAM macro operating in write mode or read mode in the ultra low voltage. If SRAM macro happens the disturb problem which made the write fail or read fail, that is no meaning for to operate at ultra low voltage. In this work, we proposed a differential read write back sense amplifier (DRWB-SA) to cancel the write half-selected disturb problem of SRAM cell. This DRWB-SA will help the SRAM to operate at the ultra low voltage. And, we analysis the SA layout style about 1 dimension or 2 dimension common-centroid and one-pitch or two-pitch to reduce the SA offset, which is made DRWB-SA can success operating at ultra low voltage by small bit line (BL) swing. To test and verify, we proposed a 64kb SRAM macro with DRWB-SA that is used two-pitch common-centroid layout is fabricated in 90nm CMOS technology. By oscilloscope and CIC 93K tester to get measurement results of the 64kb SRAM macro, that can operate down to 230mV running at 1.3MHz. Benefiting from operation at 230mV, the operating power of SRAM is 15.36uW and 32.47pJ in energy consumption.
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Lin, Huan-Ting, and 林煥庭. "A Margin Enhanced Voltage Sense Amplifier with Voltage Enhanced Feedback Scheme for Non-volatile Memories." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/b3av78.

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Lim, Huey-jen, and 林惠禎. "Low-Power Register File with Novel Low-Voltage Current Mode Sense Amplifier." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/37610064619757885057.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>High-performance low-power register file design has become one of the critical conditions for the continual advancement in wide-issue and deeply pipelined superscalar microprocessors. Frequent accesses to the register file makes it one of the major sources of power consumption and one of the prime hot-spots. A novel multi-voltage register file with one write port, two read ports and 32x32 bits implemented using TSMC 0.18μm is presented in this thesis. Low voltage techniques are applied onto the register file to reduce the power consumption while having a maximum operating frequency of 200MHz during pre-simulation. A low voltage operation of 0.5V is used for the memory core with adaptive forward body biasing. A novel low-voltage current mode sense amplifier is designed to operate with the low bit-line voltage of 0.5V of which could be used for a larger register file system. Upon simulation, an average power reduction of 80% could be achieved as compare with the normal register file working at nominal voltage.
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Lin, Chi-Chang, and 林奇昌. "A Run-Time-Calibrated Non-Strobe Sense Amplifier For Low Voltage SRAMs." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/40285367295129694855.

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碩士<br>國立中正大學<br>電機工程所<br>98<br>In this thesis focuses on low voltage and small signal amplifiers to propose a sensor mechanism to improve the overall stability and its operating voltage is set at sub-threshold voltage, the voltage drop means that the power consumption of the SRAMs, but in the process, voltage, temperature, variation caused by the traditional low-voltage sense amplifier used buffer chain amplifier, resulting in decreased overall performance, but the use of small signal amplifiers as bit line leakage in the relative impact of low voltage caused sensing serious errors , solved by leakage lookahead pre-charge circuit. First, re-design the recent literature Non-Strobed Regenerative Sense Amplifier (NSR-SA) in sub-threshold voltage, and improve both the leakage current, the main thesis is divided into two categories: 1. use stacked effect to improve the NSR-SA internal leakage current, increase their operating bandwidth 2. in the sub-threshold voltage for the serious impact of the bit-line leakage current, use leakage lookahead pre-charge circuit with the NSR-SA to solution, and its mechanism provided Run-Time-Calibrated for different variations of resistance and a higher tolerance for change, at final use the mechanism in different cells.
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Hung, Jui Yu, and 洪睿渝. "A Small Offset Voltage Sense Amplifier with Margin Enhancement and Threshold Voltage Compensated Schemes for Memories." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/p89d3w.

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碩士<br>國立清華大學<br>電機工程學系<br>103<br>In recent years, non-volatile memory is popular and used in many applications. Among them, Flash memory is the mainstream of non-volatile memory, because it provides low-cost and high capacity storage. However, Flash memory demands high program/erase voltage and long program/erase time. Even worse, Flash memory faces many challenges in scaling technology, such as small cell current, large variation of threshold voltage and coupling noise. On the other hand, emerging non-volatile memory can alleviate those concerns, and has the potential to replace Flash memory in the next generation of mainstream non-volatile storage. CRRAM performs lower program voltage and fast program time with CMOS logic process compatible. These characteristics make CRRAM attractive to industry. Nevertheless, CRRAM suffers from small R-ratio and variation of resistance. Plus the variation of CMOS logic process, it is difficult to sense the memory cell correctly. In order to improve sensing speed and yield of a memory system, we propose a small offset sense amplifier with margin enhancement and threshold voltage compensated schemes. The offset suppression of the proposed sense amplifier is about 69% at 1V and 63.8% at 0.5V by our threshold voltage compensated scheme. The margin enhancement scheme can overall achieve 3.7 times enhanced efficiency. With these two schemes, the sensing speed under 4-Sigma is improved about 30% due to reduced BL developing time. As for yield, the proposed SA only require 20mV input difference to cover 4-Sigma variation. We implement our proposed SA into an nvTCAM macro fabricated in TSMC 65nm CMOS process. The measured read access time can achieve 1.2ns by our proposed SA.
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Chiu, Zih-Yu, and 邱子育. "A Data-Aware Sense Amplifier for Low-Voltage Embedded Dynamic Random Access Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/rbg3zq.

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Li, Jia-Fang, and 李佳芳. "Triple-Margin Enhanced Current Sense Amplifier with Overdrive-Voltage Coupling for Non-Volatile Memories." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/wgb8fa.

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Liu, Yen-Chen, and 劉彥辰. "Small Offset Voltage Sense Amplifier with Margin Enhancement and Auto-Zero Schemes for Memories in Low Supply Voltage System." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/nw3t3g.

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Books on the topic "Voltage sense amplifier"

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Gang, Yung-jin. Ultra low voltage DRAM current sense amplifier with body bias techniques. 1998.

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Book chapters on the topic "Voltage sense amplifier"

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Ahir, Arti, Jitendra Kumar Saini, and Avireni Srinivasulu. "A Low-Voltage Distinctive Source-Based Sense Amplifier for Memory Circuits Using FinFETs." In Smart Innovations in Communication and Computational Sciences. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8971-8_21.

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Wicht, Bernhard. "Voltage Sense Amplifiers." In Current Sense Amplifiers. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-662-06442-9_3.

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Shailendra, Singh Rohitkumar, Pragya Sharma, M. Aarthy, and Hidenori Mimura. "High-Performance and Low-Voltage Current Sense-Amplifier Using GAA-CNTFET with Different Chirality and Channel." In Research and Education: Traditions and Innovations. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0379-3_8.

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Singh, Thakurendra, and V. K. Tomar. "Use of Sense Amplifiers for SRAM in Both Conventional Voltage and Charge Transfer Mode." In Proceedings of International Conference on Communication and Artificial Intelligence. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0976-4_57.

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Borik Stefan, Cap Ivo, Neslusan Miroslav, and Capova Klara. "Eddy Current and Magnetic Barkhausen Noise Measurement Techniques as the Tools for Evaluation of Material Property Changes Induced by Metal Working." In Studies in Applied Electromagnetics and Mechanics. IOS Press, 2017. https://doi.org/10.3233/978-1-61499-767-2-99.

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This work deals with investigation of material property changes during metal working &amp;ndash; concretely during milling. For eddy current detection, we are using the advanced single chip impedance converter. The device consists of AD5933 impedance converter, voltage controlled current source and MCU. The changes in impedance of a sensing probe are detected by using of four electrodes (couple of voltage, couple of current electrodes). The MBN measurements are performed by us designed device. The MBN device offers MBN measurements for wide range of excitation frequencies. A magnetization coil on a ferrite U &amp;ndash; core is connected to an amplifier which powers this part. The MBN signal is sensed by coil placed in U &amp;ndash; core gap and it is attached to the sample. The main aim of the work is to obtain information about the scanned surface properties using eddy current and MBN measurements.
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Conference papers on the topic "Voltage sense amplifier"

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Nam, Kyeongtae, Jaehyuk Kim, Dongil Lee, et al. "An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM." In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2024. http://dx.doi.org/10.1109/vlsitechnologyandcir46783.2024.10631481.

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Divya, Sharmila, Neha Goel, Renu Rani, Hashmat Usmani, and Sandeep Bhatia. "Sense Amplifier Performance in 180nm Technology: A Comparative Analysis of Voltage-Mode and Current-Mode." In 2024 International Conference on Communication, Computing and Energy Efficient Technologies (I3CEET). IEEE, 2024. https://doi.org/10.1109/i3ceet61722.2024.10993850.

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Bin Aslam, Talha, Mohd Aamir, Belal Iqbal, and Anuj Grover. "Investigating the Impact of Differential Voltage and Sense Amplifier Offset on Power and Delay of SRAM in 65nm LSTP Technology." In 2024 IEEE Region 10 Symposium (TENSYMP). IEEE, 2024. http://dx.doi.org/10.1109/tensymp61132.2024.10752311.

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Yong, Tang, and Feng Quan Yuan. "A Lossless Low Voltage Current Sense Amplifier." In 2006 49th IEEE International Midwest Symposium on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/mwscas.2006.382230.

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Melikyan, Vazgen, Stepan Harutyunyan, Ararat Khachatryan, and Hovhannes Harutyunyan. "A Novel Voltage Mode High Speed Sense Amplifier." In 2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO). IEEE, 2019. http://dx.doi.org/10.1109/elnano.2019.8783427.

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Attarzadeh, Hourieh, Mohammad SharifKhani, and Shah M. Jahinuzzaman. "A scalable offset-cancelled current/voltage sense amplifier." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537701.

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Choi, Woong, Jongsun Park, and Gyuseong Kang. "Dynamic stability estimation for latch-type voltage sense amplifier." In 2014 International SoC Design Conference (ISOCC). IEEE, 2014. http://dx.doi.org/10.1109/isocc.2014.7087614.

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Alam, Shamiul, Md Mazharul Islam, Md Shafayat Hossain, and Ahmedullah Aziz. "Superconducting Josephson Junction FET-based Cryogenic Voltage Sense Amplifier." In 2022 Device Research Conference (DRC). IEEE, 2022. http://dx.doi.org/10.1109/drc55272.2022.9855654.

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Shakir, Tahseen, and Manoj Sachdev. "A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs." In 2012 IEEE 25th International SOC Conference (SOCC). IEEE, 2012. http://dx.doi.org/10.1109/socc.2012.6398382.

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Lee, Choongkeun, Taegun Yim, and Hongil Yoon. "Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM." In TENCON 2018 - 2018 IEEE Region 10 Conference. IEEE, 2018. http://dx.doi.org/10.1109/tencon.2018.8650337.

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