Dissertations / Theses on the topic 'Voltage sense amplifier'

碩士<br>國立清華大學<br>電機工程學系<br>103<br>In recent years, non-volatile memory is popular and used in many applications. Among them, Flash memory is the mainstream of non-volatile memory, because it provides low-cost and high capacity storage. However, Flash memory demands high program/erase voltage and long program/erase time. Even worse, Flash memory faces many challenges in scaling technology, such as small cell current, large variation of threshold voltage and coupling noise. On the other hand, emerging non-volatile memory can alleviate those concerns, and has the potential to replace Flash memory in the next generation of mainstream non-volatile storage. CRRAM performs lower program voltage and fast program time with CMOS logic process compatible. These characteristics make CRRAM attractive to industry. Nevertheless, CRRAM suffers from small R-ratio and variation of resistance. Plus the variation of CMOS logic process, it is difficult to sense the memory cell correctly. In order to improve sensing speed and yield of a memory system, we propose a small offset sense amplifier with margin enhancement and threshold voltage compensated schemes. The offset suppression of the proposed sense amplifier is about 69% at 1V and 63.8% at 0.5V by our threshold voltage compensated scheme. The margin enhancement scheme can overall achieve 3.7 times enhanced efficiency. With these two schemes, the sensing speed under 4-Sigma is improved about 30% due to reduced BL developing time. As for yield, the proposed SA only require 20mV input difference to cover 4-Sigma variation. We implement our proposed SA into an nvTCAM macro fabricated in TSMC 65nm CMOS process. The measured read access time can achieve 1.2ns by our proposed SA.

碩士<br>國立臺灣大學<br>電機工程學研究所<br>96<br>This thesis presents a novel architecture for content-addressable memory with low power feature. This design is based on a proposed voltage compared match line sense amplifier that changes the comparison voltage of CAM word circuit. According to reducing cells on dummy word, we can reach low voltage on each match line and reduces power dissipation of the CAM system. The design was implemented in a 256-word X 144-bit ternary CAM for 1.8V 0.18-um CMOS process. Simulation results show that, for the same search time on TCAM match line, about 30% power reduction can be achieved and for the same current source on TCAM match line, about 25% speed reduction can be achieved.

碩士<br>國立中山大學<br>電機工程學系研究所<br>91<br>The first topic of this thesis is to propose a novel voltage-to-frequency converter (VFC) to provide high sensitivity. The VFC circuit is composed of one current mirror, one current multiplier, and voltage window comparators. The proposed VFC tracks the variations of the stored charge of a built-in capacitor. The voltage window comparator monitors the voltage of the capacitor to determine whether the output is pulled high or pulled down. The worth-case linear range of the output frequency of the proposed VFC is 0 to 55 MHz provided that the input voltage is 0 to 0.9 V. The error is less than 9% while the power dissipation is 0.218 mW. The second topic is to carry out a novel CMOS current-mode high- speed sense amplifier (SA). The proposed SA is composed by cascading a current-mode sense amplifier and a voltage-mode sense amplifier. The small input impedance of the current-mode amplifier alleviates the loading effect on the bitlines of SRAM cells such that the sensing speed is enhanced. The voltage-mode amplifier is responsible for boosting the logic levels to full swing. The worst access time of the proposed design is found to be less than 1.26 ns with a 1 pF load on outputs. The power dissipation is merely 0.835 mW at 793 MHz.

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.

碩士<br>國立雲林科技大學<br>電子工程系<br>106<br>Flip-Flops (FFs) are the basic storage elements used in all kinds of VLSI designs. In particular, VLSI designs nowadays often adopt intensive pipelining techniques and employ many FF rich modules. FFs thus contribute a significant portion to chip area and power consumption of the overall system design . In the first part of this paper, we propose a new type of low-cost sense amplifier flip-flop that replaces the traditional ISAFF bridge NMOS by using a simplified SRAM-based latch design and a delayed clock, and Greatly reducing the layout area and power consumption, and finally composed of 8bits shift register to do analog verification and the use of TSMC CMOS-90nm process technology to do data simulation and verification; the proposed design and the traditional circuit ISAFF, the circuit delay is reduced 7%, 12% savings in Power Delay Area (PDA) and 31% savings in area. In the second part of this paper, we propose a single-ended 8T that not only reduces the size of a single-ended 6T cell but also does not require the use of a control dummy voltage (VirVDD) to enhance writing, and utilizes two NMOS and virtual ground (VirGND2 ) Auxiliary circuit to help solve the problem of semi-selected state, the paper used TSMC's 40nm process as a verification, the operating voltage of 0.3V ~ 1V, the frequency of 21.5Hz; compared with 6T, 256bit area savings of 5%.

碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>In this thesis, two novel tolerant techniques for SRAM self-timing are presented. One of the techniques is self-activated bit-line sensing scheme (SABLS) and the other is NMOS delay chain (NDC). The sense amplifier (SA) can be either triggered by SABLS or NDC with intelligent decisions depending on on-chip variations and performance constraints. A low-swing technique for heavy-loading bit-lines is also proposed herein to support SABLS activation. The SRAM cells are designed to keep the bit-line voltage no less than VSAT spontaneously in low voltages. When in high voltages, the swing voltage of bit-line can be limited by completed signal or turning on NDC instead. Most of recent techniques may only focus on inter-die variation in their self-timing circuits, while intra-die variation is critical in the advanced technologies. Using the proposed schemes, the access failure rate will reduce 20 % compared with conventional schemes in 90nm considering both inter-die and intra-die variations. The novel self-timing activation techniques can also enables SRAM operating in a wide range of supply voltage from 1 V to 0.2V.

Αντικείμενο της παρούσας Διπλωματικής Εργασίας είναι η σχεδίαση ενός ενισχυτή χαμηλής τάσης τροφοδοσίας για την ανίχνευση καρδιακών σημάτων σε βηματοδότες. Οι επιταγές της σύγχρονης τεχνολογίας για τα ολοκληρωμένα κυκλώματα είναι η χαμηλή κατανάλωση ισχύος, η χρήση χαμηλής τάσης τροφοδοσίας, η μείωση του κόστους παραγωγής, οι όλο και μικρότερες διαστάσεις των transistors και ταυτόχρονα υψηλές επιδόσεις. Η χρήση όμως της χαμηλής τάσης τροφοδοσίας αποτελεί πρόκληση από σχεδιαστικής άποψης, για την ταυτόχρονη μείωση της κατανάλωσης ισχύος χωρίς να υποβαθμίζεται η ποιότητα του σήματος. Αυτό το πρόβλημα λύνουν μέθοδοι όπως η σχεδίαση στο πεδίο του λογαρίθμου. Τα συστήματα στο πεδίο του λογαρίθμου (Log-Domain systems) αποτελούν υποκατηγορία των συστημάτων συμπίεσης – αποσυμπίεσης (companding systems) και ανήκουν στα ELIN (Externally Linear Internaly Non-linear) συστήματα. Τα πλεονεκτήματα των συστημάτων στο πεδίο του λογαρίθμου είναι η μεγάλη δυναμική περιοχή (Dynamic Range), η δυνατότητα επεξεργασίας μεγάλων σημάτων (large signal), καθώς και η λειτουργία σε περιβάλλον χαμηλής τροφοδοσίας. Υλοποιώντας φίλτρα στο πεδίο του λογαρίθμου προσφέρονται ελκυστικά χαρακτηριστικά όπως η ηλεκτρονική ρύθμιση της συχνότητας αποκοπής ή κεντρικής συχνότητας (electronic tuning) και η σχεδίαση χωρίς παθητικές αντιστάσεις (resistorless realization). Η καρδιά είναι ένα περίπλοκο σύστημα το οποίο φροντίζει για την κυκλοφορία του αίματος στο σώμα. Το έναυσμα για την εκκίνηση κάθε καρδιακού κύκλου προέρχεται από ένα ηλεκτρικό σήμα το οποίο ξεκινάει από το φλεβοκόμβο και διαδίδεται στο υπόλοιπο μυοκάρδιο, για να ξεκινήσει ένας νέος καρδιακός κύκλος. Σε ορισμένες περιπτώσεις η καρδιά δεν λειτουργεί σωστά και το ρόλο του φλεβοκόμβου έρχεται να καλύψει το ηλεκτρονικό σύστημα του βηματοδότη, το οποίο ανιχνεύει το καρδιακό σήμα και όταν κριθεί απαραίτητο εφαρμόζει την κατάλληλη θεραπεία με ηλεκτρικές ώσεις. Για την βελτίωση της ποιότητας ζωής ασθενών με καρδιακά προβλήματα ένας βηματοδότης πρέπει να έχει όσο δυνατόν μικρότερο μέγεθος και μεγαλύτερη αυτονομία. Η πρόοδος της τεχνολογίας αποζητά τη σχεδίαση ενός συστήματος ενισχυτή για την ανίχνευση καρδιακών σημάτων πλέον ικανό να ανταπεξέλθει στη χαμηλή τάση τροφοδοσίας και να έχει μεγάλη αυτονομία λειτουργίας για την εισαγωγή του π.χ. σε ένα βηματοδότη. Το σύστημα που προτείνεται σε αυτή τη Διπλωματική Εργασία έχει ως σκοπό να εκπληρώσει τις ανάγκες αυτές χρησιμοποιώντας κυκλώματα τα οποία μπορούν να λειτουργήσουν σε χαμηλή τάση τροφοδοσίας και ταυτόχρονα να μειώνουν την κατανάλωση ισχύος. Η υλοποίηση των κυκλωμάτων μόνο με CMOS transistors στην περιοχή υποκατωφλίου, εκτός του γεγονότος ότι μειώνει το κόστος παραγωγής καθώς δεν χρησιμοποιούνται BJT transistors, προσφέρει λόγω της τεχνικής σχεδίασης στο πεδίο του λογαρίθμου και μεγάλη δυναμική περιοχή. Για την τεχνολογία 0.35μm της AMS επιτυγχάνεται λειτουργία σε περιβάλλον με 0.5V τάση τροφοδοσίας και κατανάλωση ισχύος της τάξης των 2.92nW. Ο ενισχυτής για την ανίχνευση καρδιακών σημάτων που προτείνεται, περιλαμβάνει ένα ζωνοπερατό φίλτρο σχεδιασμένο στο πεδίο του λογαρίθμου και τα κυκλώματα απόλυτης τιμής, μετατροπής της ενεργής τιμής σήματος σε σταθερό ρεύμα και συγκριτή ρεύματος.<br>This M.Sc Thesis deals with the design of a low voltage cardiac sense amplifier for pacemakers. The demands of modern technology for integrated circuits are low power consumption, ultra low power supply voltage, reduction of the production cost and high performance. Due to the fact that the use of low power supply voltage is a design challenge, the employment of the Log-Domain filter technique is an attractive solution for realizing high-performance analog processing systems. Log-Domain systems are a sub-category of compading (compressing/expanding) systems and belong to ELIN (Externally Linear Internaly Non-linear) systems. The advantages of Log-Domain systems are large dynamic range, handling of signals with relatively large amplitude, realization in a low-voltage environment, electronic tuning of their frequency characteristics and resistorless realizations. The heart is a complex system that takes care of blood circulation for the whole body. The trigger to commence the cardiac cycle is an electric signal which starts from the sinus node and expands to the rest of the myocardium in order for a new cardiac cycle to set off. In some cases, the heart does not function properly and the role of the sinus node is taken by a pacemaker, who senses the cardiac signal and when it is judged, it cures the problem with an electric pulse. In order to improve the patient’s quality of life a pacemaker has to be small in size and a prolonged battery life. Technological evolution and market demands have led to a demand for a design of a cardiac sense amplifier capable of coping with low power supply voltage and long battery life. The proposed system of this M.Sc thesis is meant to fulfill these needs by using circuits capable of functioning in a low power supply voltage environment as well as reducing power consumption. Implementing those circuits solely with CMOS transistors in the sub -threshold region, not only does it reduce the production cost since no BJT transistors are used but also it offers a large dynamic range due to the design of the circuits. For the AMS 0.35μ CMOS process of by the system functions for a power supply voltage of 0.5V while it dissipates 2.92nW. The proposed cardiac sense amplifier consists of a bandpass Log-Domain filter and circuits like an absolute value circuit, an rms-dc current converter circuit and a current comparator, which were carefully designed in order to follow the demands of modern technology and achieve the goal of low power dissipation.

The ever expanding range of applications for embedded systems continues to offer new challenges (and opportunities) to chip manufacturers. Applications ranging from exciting high resolution gaming to routine tasks like temperature control need to be supported on increasingly small devices with shrinking dimensions and tighter energy budgets. These systems benefit greatly by having the capability to operate over a wide range of supply voltages, known as ultra dynamic voltage scaling (U-DVS). This refers to systems capable of operating from nominal voltages down to sub-threshold voltages. Memories play an important role in these systems with future chips estimated to have over 80% of chip area occupied by memories. This thesis presents the design and characterization of an ultra dynamic voltage scalable memory (SRAM) that functions from nominal voltages down to sub-threshold voltages without the need for external support. The key contributions of the thesis are as follows: 1) A variation tolerant reference generation for single ended sensing: We present a reference generator, for U-DVS memories, that tracks the memory over a wide range of voltages and is tunable to allow functioning down to sub-threshold voltages. Replica columns are used to generate the reference voltage which allows the technique to track slow changes such as temperature and aging. A few configurable cells in the replica column are found to be sufficient to cover the whole range of voltages of interest. The use of tunable delay line to generate timing is shown to help in overcoming the effects of process variations. 2) Random-sampling based tuning algorithm: Tuning is necessary to overcome the in-creased effects of variation at lower voltages. We present an random-sampling based BIST tuning algorithm that significantly speed-up the tuning ensuring that the time required to tune is comparable to a single MBIST algorithm. Further, the use of redundancy after delay tuning enables maximum utilization of redundancy infrastructure to reduce power consumption and enhance performance. 3) Testing and Characterization for U-DVS systems: Testing and characterization is an important challenge in U-DVS systems that have remained largely unexplored. We propose an iterative technique that allows realization of an on-chip oscilloscope with minimal area overhead. The all digital nature of the technique makes it simple to design and implement across technology nodes. Combining the proposed techniques allows the designed 4 Kb SRAM array to function from 1.2 V down to 310 mV with reads functioning down to 190 mV. This would contribute towards moving ultra wide voltage operation a step closer towards implementation in commercial designs.

The ever expanding range of applications for embedded systems continues to offer new challenges (and opportunities) to chip manufacturers. Applications ranging from exciting high resolution gaming to routine tasks like temperature control need to be supported on increasingly small devices with shrinking dimensions and tighter energy budgets. These systems benefit greatly by having the capability to operate over a wide range of supply voltages, known as ultra dynamic voltage scaling (U-DVS). This refers to systems capable of operating from nominal voltages down to sub-threshold voltages. Memories play an important role in these systems with future chips estimated to have over 80% of chip area occupied by memories. This thesis presents the design and characterization of an ultra dynamic voltage scalable memory (SRAM) that functions from nominal voltages down to sub-threshold voltages without the need for external support. The key contributions of the thesis are as follows: 1) A variation tolerant reference generation for single ended sensing: We present a reference generator, for U-DVS memories, that tracks the memory over a wide range of voltages and is tunable to allow functioning down to sub-threshold voltages. Replica columns are used to generate the reference voltage which allows the technique to track slow changes such as temperature and aging. A few configurable cells in the replica column are found to be sufficient to cover the whole range of voltages of interest. The use of tunable delay line to generate timing is shown to help in overcoming the effects of process variations. 2) Random-sampling based tuning algorithm: Tuning is necessary to overcome the in-creased effects of variation at lower voltages. We present an random-sampling based BIST tuning algorithm that significantly speed-up the tuning ensuring that the time required to tune is comparable to a single MBIST algorithm. Further, the use of redundancy after delay tuning enables maximum utilization of redundancy infrastructure to reduce power consumption and enhance performance. 3) Testing and Characterization for U-DVS systems: Testing and characterization is an important challenge in U-DVS systems that have remained largely unexplored. We propose an iterative technique that allows realization of an on-chip oscilloscope with minimal area overhead. The all digital nature of the technique makes it simple to design and implement across technology nodes. Combining the proposed techniques allows the designed 4 Kb SRAM array to function from 1.2 V down to 310 mV with reads functioning down to 190 mV. This would contribute towards moving ultra wide voltage operation a step closer towards implementation in commercial designs.

On-chip impedance tuning is used to overcome IC perturbations caused by packaging stress. Tuning is more important for matching networks of radio frequency (RF) systems. Possible package resonance and fabrication process variations may cause instability, which is a major problem in RF systems. Thus, precautions need to be taken in order to maintain the overall stability of components and the final system itself. Electrically erasable programmable read-only memory switches (EEPROMs) occupy less die area compared to e-fuses and microelectromechanical system (MEMS) switches, thus EEPROMs are proposed to be used as tuning switches in millimetre-wave (mm-wave) applications. It is anticipated that EEPROM switches will also enable multi-time programming because of the smaller area and the fact that more switches can be used for fine-tuning. The problem addressed in this research is how suitable EEPROMs are for switching applications in the mm-wave region. The main focus of this dissertation is to characterise the suitability of EEPROM switches qualitatively for tuning with systems operating in the mm-wave spectrum. 130 nm SiGe BiCMOS IBM 8HP process technology was used for simulation and the fabricated prototypes. The Dickson charge pump (CP), two voltage doubler CPs and four floating gate (FG) devices were investigated. Literature and theoretical verification was done using computer aided design (CAD) Cadence software through circuit analysis and the layouts were also designed for integrated circuit (IC) prototype fabrication. The qualitative evaluation of the hypothesis was based on investigating reliability issues, switching characteristics, CP output drive capability and mm-wave characterisation. The maximum measured drain current for FGs was 1.4 mA, 2.7 mA and 3 mA for devices 2, 3 and 4, respectively. The ratio between ON state switching current (after tunnelling) and OFF state switching current (after injection) was 1.5, 1.35 and 6 for devices 2, 3 and 4, respectively. The ratios correlated with the expected results in terms of FG transistor area: a high area results in a higher ratio. Despite the correlation, devices 2 and 3 may be unsuitable because the ratio is less than 2: a smaller ratio between the ON and OFF states could also result in higher losses. The Dickson CP achieved an output voltage of 2.96 V from an input of 1.2 V compared to 3.08 V as computed from the theoretical analysis and 4.5 V from the simulation results. The prototypes of the voltage doubler CP did not perform as expected: a maximum of 1 V was achieved compared to 4.1 – 5 V as in the simulation results. The suitability of FG devices for switching applications depends on the ratio of the ON and OFF states (associated to insertion and isolation losses): the larger the FG transistor area, the higher the ratio. The reliability issues are dominated by the oxide thickness of the transistor, which contributes to charge leakages and charge trapping: smaller transistor length causes more uncertainties. Charge trapping in the oxide increases the probability of leakages and substrate conduction, thus introduces more losses. Based on the findings of this research work, the FG devices promise to be suitable for mm-wave switching applications and there is a need for further research investigation to characterise the devices in the mm-wave region fully. AFRIKAANS : Impedansie-instelling op skyf word gebruik om steurings in geïntegreerde stroombane wat deur verpakkingstres veroorsaak word, te oorkom. Instelling is meer belangrik om netwerke van radiofrekwensiesisteme te paar. Moontlike verpakkingresonansie en variasies in die vervaardigingsproses kan onstabiliteit veroorsaak, wat ‟n groot probleem is in radiofrekwensiesisteme. Voorsorg moet dus getref word om die oorhoofse stabiliteit van komponente en die finale sisteem self te handhaaf. Elektries uitveebare programmeerbare slegs-lees-geheueskakelaars (EEPROMs) neem minder matrysarea op as e-sekerings en die sekerings van mikro-elektromeganiese sisteme en word dus voorgestel vir gebruik as instellingskakelaars in millimetergolfaanwendings. Daar word verwag dat EEPROM-skakelaars ook multi-tydprogrammering sal moontlik maak as gevolg van die kleiner area en die feit dat meer skakelaars gebruik kan word vir fyn instellings. Die probleem wat in hierdie navorsing aandag geniet, is die geskiktheid van EEPROMS vir skakelaanwendings in die millimetergolfstreek. The hooffokus van die verhandeling is om die geskiktheid van EEPROM-skakelaars kwalitatief te karakteriseer vir instelling met sisteme wat in die millimetergolfspektrum funksioneer. Department of Electrical, Electronic and Computer Engineering v University of Pretoria 130 nm SiGe BiCMOS IBM 8HP-prosestegnologie is gebruik vir simulasie en die vervaardigde prototipes. Die Dickson-laaipomp is gebruik vir simulasie en die vervaardigde prototipes. Die Dickson-laaipomp, twee spanningverdubbelinglaaipompe en vier swewendehektoestelle is ondersoek. Literatuur- en teoretiese verifikasie is gedoen met behulp van rekenaarondersteunde-ontwerp (CAD) Cadence-sagteware deur stroombaananalise en die uitleg is ook ontwerp vir die vervaardiging van geïntegreerdestroombaanprototipes. Die kwalitatiewe evaluasie van die hipotese is gebaseer op die ondersoek van betroubaarheidkwessies, skakelingeienskappe, laaipompuitsetdryfvermoë en millimetergolfkarakterisering. Die maksimum gemete dreineerstroom vir swewende hekke was 1.4 mA, 2.7 mA en 3 mA vir onderskeidelik toestelle 2, 3 en 4. Die verhouding tussen die AAN-toestand van die skakelstroom (na tonnelling) en die AF-toestand van die skakelstroom (na inspuiting) was 1.5, 1.35 en 6 vir toestelle 2, 3 en 4, onderskeidelik. Die verhoudings het ooreengestem met die verwagte resultate rakende die swewendehek-transistorareas: ‟n groot area het ‟n hoër verhouding tot gevolg. Nieteenstaande die ooreenstemming, mag toestelle 2 en 3 moontlik nie geskik wees nie, omdat die verhouding kleiner as 2 is: ‟n kleiner verhouding tussen die AAN- en AF-toestande mag ook hoër verliese tot gevolg hê. Die Dickson-laaipomp het ‟n uitsetspanning van 2.96 V vanaf ‟n inset van 1.2 V vergeleke met 3.08 V soos bereken volgens die teoretiese analise en 4.5 V volgens die simulasieresultate. Die prototipes van die spanningverdubbelinglaaipomp het nie gefunksioneer soos verwag is nie: ‟n maksimum van 1 V is bereik vergeleke met 4.1 – 5 V soos in die simulasieresultate. Die geskiktheid van swewendehektoestelle vir skakelingtoepassings hang af van die verhouding van die AAN- en AF-toestande (wat met invoer-en isolasieverlies geassosieer word): hoe groter die swewendehektransistorarea, hoe hoër die verhouding. Die betroubaarheidkwessies word oorheers deur die oksieddikte van die transistor, wat bydra tot ladinglekkasies en ladingvasvangs: korter transistorlengte veroorsaak meer onsekerheid. Ladingvasvangs in die oksied verhoog die moontlikheid van lekkasies en substraatgeleiding en veroorsaak dus groter verlies. Die bevindings van hierdie navorsing toon dat swewendehektoestelle waarskynlik geskik is vir millimetergolfaanwendings en verdere navorsing is nodig om die toestelle volledig in die millimetergolfstreek te karakteriseer. Copyright<br>Dissertation (MEng)--University of Pretoria, 2013.<br>Electrical, Electronic and Computer Engineering<br>unrestricted