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Journal articles on the topic 'Voltage sense amplifier'

Author: Grafiati

Published: 3 June 2025

Last updated: 13 July 2025

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1

Tiwari, Nitendra kumar. "Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations." Journal of Futuristic Sciences and Applications 5, no. 2 (2022): 31–37. http://dx.doi.org/10.51976/jfsa.522205.

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MTCMOS (Multi-Threshold CMOS), sleepy stack, sleepy keeper, and footer stack are examples of low power saving techniques incorporated into the core gpdk 90nm technology papers used in the proposed study using Cadence. The main focus of these tests is the power consumption of various sense amplifier circuits. The simulation results show that the charge-transfer sense amplifier uses much less energy than voltage and current sense amplifiers. The present mode detecting amplifier’s power consumption can be decreased by up to 98 percent by using MTCMOS technology.

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2

Apeksha Garg. "Effect of Green Logistics on Designing of Single Bit Cache Memory Architecture." Communications on Applied Nonlinear Analysis 32, no. 3s (2024): 663–80. https://doi.org/10.52783/cana.v32.2725.

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The international economy's fast expansion has made logistics more crucial in addressing shifting societal demands and has also worsened sustainability and environmental issues. With an emphasis on entering and leaving logistics, this study examines the long-term effects of green logistics practices. The paper creates a theoretical framework for examining the effects of green logistical practices on single-bit cache memory architectures' economic, social, and environmental performance. This paper proposes and implements a design analysis of a single-bit static random access memory voltage differential sense amplifier architecture. It uses a write driver circuit, a static random access memory, and different differential sense amplifiers, including voltage differential sense amplifiers, current differential sense amplifiers, and charge transfer differential sense amplifiers. How well different architectures perform in terms of total power consumption, static power consumption, transistor count, and sensing delay has been determined. The voltage differential sensing amplifier for single-bit static random-access memory cells utilizes the least power (13.16µW). Longer sensing delays (12.5ηs) are present in the single-bit static random-access memory cell charge-transfer differential sense amplifier design and the single-bit random-access memory cell current differential sense amplifier architecture. Techniques for power reduction have also been employed to optimize power.

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3

Shrivastava, Anurag, and Mohan Gupta. "Evaluation of the Core Processor Cache Memory Architecture's Performance." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 11–18. http://dx.doi.org/10.51976/jfsa.211903.

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In this study, memory architectures for single-bit caches are studied. Voltage differential sense amplifiers and charge transfer differential sense amplifiers are used to study a six-transistor static random-access memory. In a single-bit, six-transistor static random-access memory, it has been demonstrated that the voltage differential sensing amplifier uses the least power.

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4

Sandhya, Kalla. "Design and High Performance Evaluation of a Low Power Bit-Line SRAM PMOS Biased Sense Amplifier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 06 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem36033.

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Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

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5

Zhang, Hua. "A Sense Amplifier for Low Voltage Embedded Flash Memories." Advanced Materials Research 986-987 (July 2014): 1734–37. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1734.

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A sense amplifier applied for low voltage embedded flash memories is presented. The sense amplifier uses an enhanced current sensing method allowing power supplies lower than 1.5 V to be used. The sense amplifier was implemented in a FLASH realized with a 0.13 um FLASH technology. Simulation results showed a read access time of about 25 ns with a power supply of 1.5 V, and 32ns with a power supply of 1.2V.

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6

Kumar Pandey, Neeraj. "IoT Systems with Low-Power SRAM Memory Architecture." Journal of Futuristic Sciences and Applications 4, no. 2 (2021): 9–15. http://dx.doi.org/10.51976/jfsa.422102.

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A quantitative and yield analysis was made and tested on a single-bit cache memory design using a range of resistor values and various sense amplifier types, such as the voltage mode differential sense amplifier (VMDSA). In a single-bit cache memory design, the voltage mode differential sense amplifier uses the least power. The low power consumption and long access times of this SRAM will be very advantageous for the Internet of Things (IoT).

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7

Koo, Kyung Min, Woo Young Chung, Sang Yi Lee, Gyu Han Yoon, and Woo Young Choi. "Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage." Micromachines 12, no. 10 (2021): 1145. http://dx.doi.org/10.3390/mi12101145.

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With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage, leading to sensing failure. Previous studies indicate that the threshold voltage mismatch between the paired transistors of a sense amplifier is the most critical factor. In this study, virtual wafers were generated, including statistical VT variation. Then, we numerically investigate the prediction accuracy and reliability of the offset voltage of DRAM wafers using test point measurement for the first time. We expect that this study will be helpful in strengthening the in-line controllability of wafers to secure the DRAM sensing margin.

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8

Shukla, Sachchida Nand, Syed Shamroz Arshad, and Geetika Srivastava. "NPN Sziklai pair small-signal amplifier for high gain low noise submicron voltage recorder." International Journal of Power Electronics and Drive Systems (IJPEDS) 13, no. 1 (2022): 11. http://dx.doi.org/10.11591/ijpeds.v13.i1.pp11-22.

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Small signal-to-noise ratio (SNR) and multiple noise sources, coupled with very weak signal amplitudes of bio signals make brain-computer interface (BCI) application studies a challenging task. The front-end recorder amplifiers receive very-weak signal (few μV) from high impedance electrodes and for efficient processing of such weak and low frequency (<1 kHz) signals a high gain amplifier with very low operating voltage and low total harmonic distortion (THD) is required. Existing amplifiers suffer from problem of high non-linearity and low common mode rejection. A good sense amplifier at predeceasing stage can solve this problem. Utilizing very high amplification factor of Sziklai Pair, this paper proposes two circuit topologies of common-emitter and common-collector negative-positive-negative (NPN) Sziklai Pair small signal amplifiers suitable for use in preamplifier stages of such signal acquisition circuit. Present study provides broad-spectrum of analysis of these amplifiers covering effect of additional biasing resistance RA, variation of ‘ideal forward maximum beta’ β, temperature dependency, noise sensitivity and phase variation. The tunable capability of first topology makes it a suitable candidate in wide variety of other applications. The first amplifier operates on very low input voltage range (0.1μV-6mV) whereas the second amplifier works on 100 μV-11 mV range of input voltage.

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9

Abhinav, V. Deshpande. "OFFSET REDUCTION IN THE DOUBLE TAILED LATCH-TYPE VOLTAGE SENSE AMPLIFIER." International Journal of Advanced Trends in Engineering and Technology 4, no. 2 (2019): 1–5. https://doi.org/10.5281/zenodo.3336352.

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This research paper presents an improved double tailed latch type voltage sense amplifier by using a latch load in the first stage. A latch load at the first stage provides the second stage with a large input difference voltage. Thus, completely removes the offset voltage due to the mismatch in the transistor pairs in the second stage of the Sense Amplifier. The performance of the Sense Amplifier was simulated by using the LT Spice with a threshold mismatch of 10% in between the transistor pairs of the second stage, where it achieved the offset removal at 3 GHz clock rate with V<sub>DD </sub>= 1. 2 Volts in a 90 nm CMOS technology. Since the input transistors of the first stage are in parallel with the transistor pair of the latch, it does not affect the delay.

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10

Nand, Deva, and Neeta Pandey. "A New Proposal for OFCC-based Instrumentation Amplifier." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (2017): 134. http://dx.doi.org/10.11591/ijece.v7i1.pp134-143.

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This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.

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11

Deva, Nand, and Pandey Neeta. "A New Proposal for OFCC-based Instrumentation Amplifier." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (2017): 134–43. https://doi.org/10.11591/ijece.v7i1.pp134-143.

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This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.

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12

Sachchida, Nand Shukla, Shamroz Arshad Syed, and Srivastava Geetika. "NPN Sziklai pair small-signal amplifier for high gain low noise submicron voltage recorder." International Journal of Power Electronics and Drive Systems (IJPEDS) 13, no. 1 (2022): 11–22. https://doi.org/10.11591/ijpeds.v13.i1.pp11-22.

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Abstract:

Small signal-to-noise ratio (SNR) and multiple noise sources, coupled with very weak signal amplitudes of bio signals make brain-computer interface (BCI) application studies a challenging task. The front-end recorder amplifiers receive very-weak signal (few μV) from high impedance electrodes and for efficient processing of such weak and low frequency (<1 kHz) signals a high gain amplifier with very low operating voltage and low total harmonic distortion (THD) is required. Existing amplifiers suffer from problem of high non-linearity and low common mode rejection. A good sense amplifier at predeceasing stage can solve this problem. Utilizing very high amplification factor of Sziklai Pair, this paper proposes two circuit topologies of common-emitter and common-collector negative-positive-negative (NPN) Sziklai Pair small signal amplifiers suitable for use in preamplifier stages of such signal acquisition circuit. Present study provides broad-spectrum of analysis of these amplifiers covering effect of additional biasing resistance RA, variation of ‘ideal forward maximum beta’ β, temperature dependency, noise sensitivity and phase variation. The tunable capability of first topology makes it a suitable candidate in wide variety of other applications. The first amplifier operates on very low input voltage range (0.1 μV-6 mV) whereas the second amplifier works on 100 μV-11 mV range of input voltage.

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13

Kim, Dong-Yeong, Geon Kim, Jin-Hyo Park, Su-Yeon Kim, Je-Won Park, and Myoung-Jin Lee. "Offset Reduction Scheme of the Voltage Latched Sense Amplifier." Journal of the Institute of Electronics and Information Engineers 59, no. 6 (2022): 32–35. http://dx.doi.org/10.5573/ieie.2022.59.6.32.

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14

Zhang, Hua, and Ling Lu. "A Low-Voltage Sense Amplifier for Embedded Flash Memories." IEEE Transactions on Circuits and Systems II: Express Briefs 62, no. 3 (2015): 236–40. http://dx.doi.org/10.1109/tcsii.2014.2368259.

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15

Ali, Luqman Sufer, and Asmaa Salim Mayoof. "Design of Current Mode MTCMOS Sense Amplifier with Low Power and High Speed." Tikrit Journal of Engineering Sciences 23, no. 2 (2016): 96–102. http://dx.doi.org/10.25130/tjes.23.2.11.

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This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipation problem in the higher technology design. Simulated results show the current mode sense amplifier with MTCMOS technology has 0.82ns time delay and 0.395μW power dissipation. The designs and simulations in 0.25μm CMOS technology with supply voltage equal to 1.8 V have been carried out to evaluate the efficiency of the current mode sense amplifier with MTCMOS technique proposed.

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16

SINGH, AJAY KUMAR, MAH MENG SEONG, and C. M. R. PRABHU. "LOW POWER AND HIGH PERFORMANCE SINGLE-ENDED SENSE AMPLIFIER." Journal of Circuits, Systems and Computers 22, no. 07 (2013): 1350062. http://dx.doi.org/10.1142/s021812661350062x.

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This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation.

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17

Giagkoulovits, Christos, and Costas Psychalinos. "0.5 V Cardiac Sense Amplifier Realization Using Log-Domain Filtering." ISRN Biomedical Engineering 2013 (June 23, 2013): 1–11. http://dx.doi.org/10.1155/2013/369850.

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A novel configuration of a cardiac sense amplifier for pacemakers, realized using the concept of Log-Domain filtering, is introduced in this paper. The analog part of the amplifier operates under a single 0.5 V power supply voltage. Compared to the corresponding already published configuration, the proposed scheme offers the benefits of reduced operating voltage and dc power dissipation. The performance of the intermediate stages, as well as of the whole system, has been evaluated through the utilization of the Analog Design Environment of the Cadence software and, also, the design kit provided by the AMS 0.35 μm CMOS process.

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18

Dinesh Kumar, S., and N. Viswanathan. "Analyzing the Performance of a Low Power, High Performance Latch-Based Static Random-Access Memory Sense Amplifier for Epilepsy Detection." Journal of Nanoelectronics and Optoelectronics 19, no. 7 (2024): 759–67. http://dx.doi.org/10.1166/jno.2024.3622.

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Epilepsy is a neurological disorder characterized by unpredictable seizures, making early detection crucial for effective management and treatment. Traditional detection methods often rely on bulky and power-hungry equipment, limiting their practicality for continuous monitoring. As such, there is a growing demand for lowpower, high-performance sensing technologies to enable wearable or implantable epilepsy detection devices. In this context, the development of a latch-based SRAM sense amplifier presents a promising avenue for achieving both sensitivity and power efficiency in seizure detection systems. The proposed latch-based SRAM sense amplifier architecture is meticulously designed to meet the specific requirements of epilepsy detection applications. Leveraging advanced semiconductor technologies and circuit design techniques, we optimize the sense amplifier’s performance parameters, including sensitivity, speed, and power consumption. Through extensive simulations using industry-standard tools, we evaluate the sense amplifier’s performance under varying conditions, such as input signal amplitude, frequency, and power supply voltage. Additionally, we compare the proposed architecture with existing solutions to assess its superiority in terms of both performance and energy efficiency. Our analysis reveals that the developed latch-based SRAM sense amplifier exhibits superior sensitivity to subtle signals associated with epileptic activity while consuming significantly less power compared to conventional designs. The sense amplifier demonstrates rapid response times, enabling real-time detection and timely intervention in seizure events. By combining sensitivity, speed, and energy efficiency, the proposed architecture offers a compelling solution to the challenges associated with continuous monitoring of epileptic seizures.

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19

Guo, Jiarong. "A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory." Journal of Semiconductors 38, no. 4 (2017): 045001. http://dx.doi.org/10.1088/1674-4926/38/4/045001.

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20

KONG, ZHI-HUI, KIAT-SENG YEO, and CHIP-HONG CHANG. "AN ULTRA LOW-POWER CURRENT-MODE SENSE AMPLIFIER FOR SRAM APPLICATIONS." Journal of Circuits, Systems and Computers 14, no. 05 (2005): 939–51. http://dx.doi.org/10.1142/s021812660500274x.

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A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.

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21

Mönch, Stefan, Richard Reiner, Michael Basler, et al. "Three-Phase Motor Inverter and Current Sensing GaN Power IC." Sensors 23, no. 14 (2023): 6512. http://dx.doi.org/10.3390/s23146512.

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A three-phase GaN-based motor inverter IC with three integrated phase current mirror sensors (sense-FETs or sense-HEMTs, 1200:1 ratio), a temperature sensor, and an amplifier is presented and experimentally operated. The three low-side currents are read out by virtual grounding transimpedance amplifiers. A modified summed DC current readout circuit using only one amplifier is also discussed. During continuous 24 V motor operation with space-vector pulse width modulation (SVPWM), the sensor signal is measured and a bidirectional measurement capability is verified. The measured risetime of the sensor signal is 51 ns, indicating around 7 MHz bandwidth (without intentional optimization for high bandwidth). The IC is operated up to 32 V on DC-biased semi-floating substrate to limit negative static back-gating of the high-side transistors to around −7% of the DC-link voltage. Analysis of the capacitive coupling from the three switch-nodes to the substrate is calculated for SVPWM based on capacitance measurement, resulting in four discrete semi-floating substrate voltage levels, which is experimentally verified. Integrated advanced power converter topologies with sensors improve the power density of power electronics applications, such as for low-voltage motor drive.

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22

Rahman, L. F., Mamun Bin Ibne Reaz, and M. A. M. Ali. "A LOW VOLTAGE-TYPE SENSE AMPLIFIER DESIGN FOR EEPROM MEMORY." Telecommunications and Radio Engineering 70, no. 15 (2011): 1379–85. http://dx.doi.org/10.1615/telecomradeng.v70.i15.80.

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23

Li, Ming, Li-Wu Yang, and Jin-Feng Kang. "A Voltage-Type Sense Amplifier for Low-Power Nonvolatile Memories." ECS Transactions 27, no. 1 (2019): 131–36. http://dx.doi.org/10.1149/1.3360608.

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24

Sanghoon Hong, Sejun Kim, Jae-Kyung Wee, and Seongsoo Lee. "Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier." IEEE Journal of Solid-State Circuits 37, no. 10 (2002): 1356–60. http://dx.doi.org/10.1109/jssc.2002.803052.

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25

Dai, Chenghu, Yixiao Lu, Wenjuan Lu, Zhiting Lin, Xiulong Wu, and Chunyu Peng. "Low-Power Single Bitline Load Sense Amplifier for DRAM." Electronics 12, no. 19 (2023): 4024. http://dx.doi.org/10.3390/electronics12194024.

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With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits.

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26

Deng, Xiao Ying, Yan Yan Mo, and Jian Hui Ning. "High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop." Applied Mechanics and Materials 713-715 (January 2015): 1042–47. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.1042.

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With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

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N, Sivakumar, Venkatesh Kavididevi, Sathiya M, and Pandi Maharajan M. "AN IMPROVISED METHOD TO SECURE SENSE AMPLIFIER USING MACHINE LEARNING ASSISTED MEMRISTORS." ICTACT Journal on Microelectronics 9, no. 1 (2023): 1503–7. https://doi.org/10.21917/ijme.2023.0260.

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The rapid development of memristor technology gives hope for a solution to both issues since it promises to enhance the capabilities of electronics beyond what CMOS technology can provide on its own and makes it possible to implement unconventional computer designs. In this paper, we present a novel sensing amplifier that possesses unwavering consistency. The proposed sensory amplifier makes use of a Machine Learning Assisted Memristor (MLAM) circuit to reliably recreate the same values as the original randomly generated keys, despite variations in noise, supply voltage, and temperature. When compared to the other available topologies, the recommended sensory amplifier uses an amplifier structure to provide a quick response time and good traits of originality and unpredictability.

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28

Peng, Chunyu, Lingyu Kong, Xiulong Wu, et al. "Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique." IEICE Electronics Express 15, no. 10 (2018): 20180332. http://dx.doi.org/10.1587/elex.15.20180332.

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29

Patel, Dhruv, Adam Neale, Derek Wright, and Manoj Sachdev. "Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 7 (2019): 2519–32. http://dx.doi.org/10.1109/tcsi.2019.2899314.

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30

Wicht, B., T. Nirschl, and D. Schmitt-Landsiedel. "Yield and speed optimization of a latch-type voltage sense amplifier." IEEE Journal of Solid-State Circuits 39, no. 7 (2004): 1148–58. http://dx.doi.org/10.1109/jssc.2004.829399.

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31

Li, Ming, JinFeng Kang, and YangYuan Wang. "A novel voltage-type sense amplifier for low-power nonvolatile memories." Science China Information Sciences 53, no. 8 (2010): 1676–81. http://dx.doi.org/10.1007/s11432-010-4015-8.

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32

Jiang, Liu, Wang Xueqiang, Wang Qin, et al. "A low-voltage sense amplifier for high-performance embedded flash memory." Journal of Semiconductors 31, no. 10 (2010): 105001. http://dx.doi.org/10.1088/1674-4926/31/10/105001.

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33

Yu, Qun Ling, Na Bai, Yan Zhou, Rui Xing Li, Jun Ning Chen, and Zheng Ping Li. "An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM." Advanced Materials Research 542-543 (June 2012): 769–74. http://dx.doi.org/10.4028/www.scientific.net/amr.542-543.769.

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A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

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34

Patel, Dhruv, Adam Neale, Derek Wright, and Manoj Sachdev. "Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 8 (2021): 3265–78. http://dx.doi.org/10.1109/tcsi.2021.3081917.

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35

JIA, Song, Heqing XU, Fengfeng WU, and Yuan WANG. "A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs." IEICE Transactions on Electronics E96.C, no. 9 (2013): 1205–7. http://dx.doi.org/10.1587/transele.e96.c.1205.

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Anh-Tuan Do, Zhi-Hui Kong, and Kiat-Seng Yeo. "Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 1 (2010): 83–92. http://dx.doi.org/10.1109/tcsi.2009.2016182.

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Jeong, Hanwool, Taewon Kim, Kyoman Kang, et al. "Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 6 (2015): 1555–63. http://dx.doi.org/10.1109/tcsi.2015.2415171.

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Conte, A., G. L. Giudice, G. Palumbo, and A. Signorello. "A high-performance very low-voltage current sense amplifier for nonvolatile memories." IEEE Journal of Solid-State Circuits 40, no. 2 (2005): 507–14. http://dx.doi.org/10.1109/jssc.2004.840985.

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Zhu, Wenyi, Jianwei Jiang, Haineng Zhang, et al. "A Wide-Range-Supply-Voltage Sense Amplifier Circuit for Embedded Flash Memory." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 8 (2020): 1454–58. http://dx.doi.org/10.1109/tcsii.2019.2939160.

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Lee, Myoung Jin. "A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage Applications." IEEE Journal of Solid-State Circuits 46, no. 3 (2011): 690–94. http://dx.doi.org/10.1109/jssc.2010.2102570.

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Guo, Jiarong, and Feng Ran. "A new low-voltage and high-speed sense amplifier for flash memory." Journal of Semiconductors 32, no. 12 (2011): 125003. http://dx.doi.org/10.1088/1674-4926/32/12/125003.

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Hu, Wei, Hangze Zhang, Rongshan Wei, and Qunchao Chen. "A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits." Electronics 13, no. 2 (2024): 356. http://dx.doi.org/10.3390/electronics13020356.

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Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings.

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Greene, Alexander E. "Sensitive High-Vacuum Monitoring for Philips Electron Microscopes Which Employ ION Getter Pumping." Proceedings, annual meeting, Electron Microscopy Society of America 48, no. 1 (1990): 188–89. http://dx.doi.org/10.1017/s0424820100179695.

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A very sensitive vacuum monitor may be easily and inexpensively added to any Philips CM or 400 series electron microscope. This digital, auto-ranging volt meter will also operate as an excellent leak detector.The newer Philips computerized transmission electron microscopes have no separate high vacuum gauge and sense high vacuum the same way as it is done on the 400 series instruments. The high vacuum monitoring technique for these microscopes is accomplished by relating the electrical current required by the Ion Getter Pump to the quality of the vacuum (i.e. the better the vacuum, the lower the current). The system for vacuum monitoring measures the voltage across a low value resistor which is placed in series with the Getter Pump and the pump power supply and is usually located near ground or earth potential. The power supply delivers about 7000 V.D.C. to the pump and the voltage across the low value resistor is proportional to the current being drawn by the pump. This voltage is measured, amplified and then compressed by a logarithmic amplifier so one meter scale or a simple digital-to-analog converter can provide a reading equivalent to the high vacuum value. Because of the logarithmic amplifier, small changes cannot be seen; only the general vacuum quality can be monitored.

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K, ,. KomalShrivastavaa, Parul Garg, Avireni Srinivasulu, and Jyoti Sharma. "A Sense Amplifier Based Modified Low Voltage Two Stage Flip-Flop with CNTFETs." ECS Transactions 107, no. 1 (2022): 19517–27. http://dx.doi.org/10.1149/10701.19517ecst.

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The transformation from the event of enabling technology to the assembly of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the merchandise as implicit precursors. The Carbon Nanotube Field Effect Transistors (CNTFETs) are nowadays popular emerging technology. The paper proposes the sense amplifier-based two-stage flip-flop working within the sub-threshold region. the primary stage produces full swing conditional inputs for the latch stage. The proposed circuit has been designed using 16 CNTFETs. This circuit contains a significantly low clock load which reduces the power consumption. An improvement in the propagation delay and power delay product has also been achieved. Comparisons with other flip-flop designs manifest the robustness of the proposed circuit. The HSPICE software is used for simulating and verifying the theoretical results.

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Deng, Xiaoying, and Yanyan Mo. "Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range." Electronics Letters 51, no. 9 (2015): 680–82. http://dx.doi.org/10.1049/el.2014.3845.

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Jeong, Hanwool, Tae Woo Oh, Seung Chul Song, and Seong-Ook Jung. "Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 4 (2018): 609–20. http://dx.doi.org/10.1109/tvlsi.2017.2777788.

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Agbo, Innocent, Mottaqiallah Taouil, Daniël Kraak, et al. "Sense amplifier offset voltage analysis for both time-zero and time-dependent variability." Microelectronics Reliability 99 (August 2019): 52–61. http://dx.doi.org/10.1016/j.microrel.2019.03.009.

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Apoorva, Reddy Proddutoori. "High Impact of Low Voltage Controlling SoC Power." European Journal of Advances in Engineering and Technology 7, no. 12 (2020): 89–92. https://doi.org/10.5281/zenodo.12771134.

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The scaling of CMOS technology significantly increases the mismatch and fluctuations of transistor threshold voltage, causing bias voltage in SoC designs. A large offset voltage increases clock line jitter and negatively affects dynamic power consumption during reading, detecting the correct speed and operating speed. All MOS transistors used in the low-order dropout (LDO) regulator are low voltage (LV) MOSFETs, saving the manufacturing cost of high voltage devices for the conventional design. Two low voltage transistors are cascaded in the power transmission, creating multiple voltage domains. The main voltage level is used to generate a VDD voltage to the power transistors and as the main error gain to ensure safe operation. The center rail regulator uses stackable transistors to control the high supply voltage. In addition, adaptive biasing is used to achieve good stability and fast transient response. This paper presents a low voltage-based power sense amplifier for offset compensation on integrated CMOS low-order dropout (LDO) with quicker transient response for SoC power management.

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Na, Taehui. "Robust Offset-Cancellation Sense Amplifier for an Offset-Canceling Dual-Stage Sensing Circuit in Resistive Nonvolatile Memories." Electronics 9, no. 9 (2020): 1403. http://dx.doi.org/10.3390/electronics9091403.

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With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16.

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You, Heng, Jia Yuan, Weidi Tang, Zenghui Yu, and Shushan Qiao. "A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS." Electronics 9, no. 5 (2020): 802. http://dx.doi.org/10.3390/electronics9050802.

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In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

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