Dissertations / Theses on the topic 'Voltage-to-current converter'

Breathing Stabilization System is a new idea and method. The purpose of this system is to produce a device to control a patient's breathing for gated radiotherapy. This thesis focuses on building a simple Breathing Stabilization System that includes five solenoids, a power supply and five force sensors to build up the whole system. Significantly, this thesis will introduce the modeling of solenoids in detail that include how to build a mathematical model of the solenoids. The simulation of the electromagnetic in professional multi-physics software COMSOL will also be explained. To drive the solenoid system, a voltage-to-current converter is used. This part will be introduced as well as the operational amplifier circuit used by the force sensors.

Thesis (MEng)--Stellenbosch University, 2014.
ENGLISH ABSTRACT: The development of fast and efficient processors, programmable devices and high power semiconductors has led to the increased use of semiconductors directly in the power supply path in order to achieve strict power quality standards. New and advanced algorithms are used in the process and calculated on-line to bring about the required fast response to voltage variations. Losses in high voltage semiconductors increase with increased operating frequencies. A balance between semiconductor power losses and power quality is achieved through control of power semiconductor switching frequencies. A predictive control algorithm to achieve high power quality and limit the power losses in the high power semiconductor switches through switching frequency control is discussed for a tap switched voltage regulator. The quality of power, voltage regulator topology and the control algorithm are discussed. Simulation results of output voltage and current are shown when the control algorithm is used to control the regulator. These results are verified by practical measurements on a synchronous buck converter.
AFRIKAANSE OPSOMMING: Die ontwikkeling van vinnige en doeltreffende verwerkers, programmeerbare toestelle en hoëdrywings halfgeleiers het gelei tot 'n groter gebruik van halfgeleiers direk in die kragtoevoer pad om streng elektriese toevoer kwaliteit standaarde te bereik. Nuwe en gevorderde algoritmes word gebruik in die proses en word aan-lyn bereken om die nodige vinnige reaksie tot spanningswisselinge te gee. Verliese in hoë-spannings halfgeleiers verhoog met hoër skakel frekwensies. 'n Balans tussen die halfgeleier drywingsverliese en spanningskwalteit is behaal deur die skakel frekwensie in ag te neem in die beheer. 'n Voorspellinde-beheer algoritme om ‘n hoë toevoerkwaliteit te bereik en die drywingsverliese in die hoëdrywingshalfgeleier te beperk, deur skakel frekwensie te beheer, is bespreek vir 'n tap-geskakelde spanning reguleerder. Die toevoerkwaliteit, spanningsreguleerder topologie en die beheer algoritme word bespreek. Simulasie resultate van die uittree-spanning en stroom word getoon wanneer die beheer algoritme gebruik word om die omsetter te beheer. Hierdie resultate is deur praktiese metings op 'n sinkrone afkapper.

The objective of the research is to develop a cost-effective high-power bi-directional dc/dc converter with low total-device ratings, reduced system parasitic effects, and a wide input/output range. Additional objectives of the research are to develop a small-signal model and control methods, and to present performance characterizations. Device stresses in the proposed topology are controlled to maintain minimal levels by varying the duty ratio and phase-shift angle between the primary and the secondary bridges, which results in a low total-device rating, when compared to conventional bi-directional dc/dc topologies. In the proposed topology, soft switching, which reduces power loss, can be realized under specific operating conditions. When the condition that causes minimal device stress is satisfied, zero-voltage switching (ZVS) can be obtained. In the research, ZVS capability is explored for a wide range of voltage conditions as well as for the minimal device-stress condition. The performance characterization includes verifying the soft-switching regions and power-loss estimation. Another part of the thesis is the controller design of the converter. Small-signal models and feedback controllers are developed, and the controllers are experimentally validated. Because in the isolated high-frequency converters, transformer saturation is an important issue, a method to prevent transformer saturation is proposed and experimentally validated.

The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.

This report is an outcome of a master degree project at Linköpings University in co-operation with Micronic Laser Systems AB.

The purpose with this master degree project was to investigate how to implement a receiver in a data transfer system. The system consists of several data channels, where every channel consists of three parts: driver, transmission lines and receiver. The driver send low amplitude differential signals via the transmission lines to the receiver that amplifies and converts it to a single-ended signal. The receiver has to be fast and be able to feed an output signal with high voltage swing. It is also needed for the receivers to have low power consumption since they are close to the load, which is sensitive to heat.

Different amplifier architectures were investigated to find a suitable circuit for the given prerequisites. In this report the advantages and disadvantages of voltage and current feedback are discussed.

The conclusions of this work are that in a system with an amplifier as a receiver with differential transmission lines, a single operational amplifier cannot be used. An input stage is needed to isolate the feedback net from the inputs of the operational amplifier. When fast rise time and large output swing are wanted the best amplifier architecture is current feedback amplifiers. A current feedback amplifier in CMOS with the required high voltages and slew rate is hard to realize without very high power consumption.

The research work described in this thesis is concerned with the analysis and design of low distortion voltage-to-current (V-I) converter bipolar junction transistor circuits. In this thesis, various voltage-to-current converter circuits published in the past have been reviewed by the author in order to understand the different techniques employed to improve the linear operating range, total harmonic distortion and transconductance. Throughout this research, the emphasis has been to improve the above mentioned parameters. All the V-I converter circuits reported have been simulated using PSpice and the results compared with the values obtained by theoretical analysis. The majority of the results of this work have been reported by the author; see Chapter 10 at the end of this thesis where all 5 publications by the author can be found in full. It was necessary to obtain precise values for certain parameters, in particular, transition frequency (fT), Early voltage (VA) and current gain (P) of the transistor to facilitate the design process. This was done using an extensive set of simulations for the transistor operating at different collector current levels. A commonly encountered requirement of the V-I circuits is an accurate non-integer ratio of current biasing. Several published such biasing schemes were studied and three new designs were conceived and evaluated. In the next part of the work several V-I converter circuits were reviewed to understand the various existing techniques and their limitations. These can be conveniently classified into three main classes of technique, namely (i) boosted-gm (ii) cross-coupled, and (iii) multi-tanh. Of these, the boosted-gm technique showed the most promise for further exploitation and development. New circuits were then developed using the boosted-gm technique with different types of feedback, classified as collector-base feedback, collector-emitter feedback and global feedback. In terms of the preferred circuit performance, these were assessed by an arbitrary but convenient, figure-of-merit (FOM) which is defined as (THDRxBW)/PD where THDR, in dB is the total harmonic distortion .reduction, BW is the 3dB bandwidth and PD is the power dissipation. On this basis, the best value of FOM (2421.24 dBMHz/mW) was achieved with the circuit called Type 2B in this thesis, which is based on collector-emitter feedback.

Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible. Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy. The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived.

Thesis (MScEng)--University of Stellenbosch, 2003.
ENGLISH ABSTRACT: This thesis discusses the analysis and design of a voltage regulator based on an AC-to-AC converter. A background study was performed on the best topology for the purpose. The chosen topology was analysed and the converter was designed in detail. A voltage sign-detector and an over-current detector were designed and built. They were used for control and protection. Three methods of control were investigated. The first was a slow but reliable method of computing the RMS value of the input voltage and then using that value and the RMS value of the desired output voltage to compute the duty ratio of the converter. The second method was fast and is an open-loop control method, where the measured input voltage and a reference value of the desired output voltage are used to compute the duty ratio. The third method is a closed-loop control method in which the input voltage, output voltage and the same reference values used in the second method are used to compute the duty ratio. All of these methods were implemented and tested.
AFRIKAANSE OPSOMMING: Hierdie tesis bespreek die analise en die ontwerp van 'n spannings reguleerder wat gebaseer is op 'n WS-na-WS omsetter. 'n Ondersoek was ingestelom die beste topologie te vind vir die doel. Die topologie wat gekies is, is toe geanaliseer en die omsetter is in detailontwerp. 'n Spannings-tekendetektor baan as ook 'n oorstroombeskermings baan was ontwerp en is gebou. Hierdie bane word gebruik vir die beheer en die beveiliging van die stelsel. Daar is drie metodes van beheer wat ondersoek is. Die eerste metode is stadig, maar betroubaar. Die metode bereken die WGK waarde van die intree spanning en gebruik dan die waarde en die WGK van die gewenste uittree spanning om die diens siklus van die omsetter uit te werk. Die tweede metode van beheer is vinnig en is 'n oop-lus metode van beheer. Hierdie metode maak gebruik van die gemete intreespanning en 'n verwysing van die gewensde uittree spanning om die dienssiklus uit te werk. Die derde metode is 'n geslote-lus beheer wat van die gamete intreespanning, die gemete uittreespanning en die verwysing soos die in die tweede beheermetode gebruik maak on die diens siklus uit te werk. AI die metodes was geimplementeer en getoets.

Les convertisseurs de forte puissance sont des éléments critiques des futurs réseaux HVDC. À ce titre, leur fiabilité et leur endurance sont primordiales. La défaillance d’un composant se produit soit en circuit ouvert, ou en court-circuit. Le composant défaillant en circuit ouvert est inadmissible pour les convertisseurs utilisant une topologie de mise en série. En particulier, dans certaines applications HVDC, les modules doivent être conçus de telle sorte que lorsqu'une défaillance se produit, le module défaillant doit se comporter comme un court-circuit et supporter ainsi le courant nominal qui le traverse. Un tel comportement est appelé “défaillance en court-circuit” ou “failure-to-short-circuit”. Actuellement, tous les modules de puissance ayant un mode de défaillance en court-circuit disponibles dans le commerce utilisent des semi-conducteurs en silicium. Les potentialités des semi-conducteurs en carbure de silicium (SiC) poussent, aujourd’hui, les industriels et les chercheurs à mener des investigations pour développer des modules Fail-to-short à base des puces SiC. C’est dans ce contexte que se situe ce travail de thèse, visant à concevoir un module à base de puces SiC offrant un mode de défaillance de court-circuit. Pour cela nous présentons d’abord une étude de l’énergie de défaillance des puces SiC, afin de définir les plages d’activation du mécanisme Fail-to-short. Ensuite, nous démontrons la nécessité de remplacer les interconnexions classiques (fils de bonding) par des contacts massifs sur la puce. Enfin, une mise en œuvre est présentée au travers d’un module “demi pont” à deux transistors MOSFET
The reliability and endurance of high power converters are paramount for future HVDC networks. Generally, module’s failure behavior can be classified as open-circuit failure and short-circuit failure. A module which fails to an open circuit is considered as fatal for applications requiring series connection. Especially, in some HVDC application, modules must be designed such that when a failure occurs, the failed module still able to carry the load current by the formation of a stable short circuit. Such operation is referred to as short circuit failure mode operation. Currently, all commercially available power modules which offer a short circuit failure mode use silicon semiconductors. The benefits of SiC semiconductors prompts today the manufacturers and researchers to carry out investigations to develop power modules with Fail-to-short-circuit capability based on SiC dies. This represents a real challenge to replace silicon power module for high voltage applications in the future. The work presented in this thesis aims to design a SiC power module with failure to short-circuit failure mode capability. The first challenge of the research work is to define the energy leading to the failure of the SiC dies in order to define the activation range of the Fail-to-short mechanism. Then, we demonstrate the need of replacing the conventional interconnections (wire bonds) by massive contacts. Finally, an implementation is presented through a "half bridge" module with two MOSFETs

Increased awareness concerning our energy consumption and its environmentaleffects, has led to a high demand for renewable energies. Hydropower providesaround 40 percent of the electric energy consumed in Sweden today. If energyefficiency and production time were to increase only by some percent in thehydropower plants, vast amounts of additional renewable energy could besupplied to the electric grid. The Hydropower group at Uppsala University usesa hydropower generator to localize and decrease some of the power losses andthe wearing in the generator. New equipment is being tested and evaluated onthe generator. By measuring static and dynamic forces in the generator broaderinsight can be reached during these tests. This thesis describes the development of a system measuring forces on ahydropower generator using strain gages. Each sensor node is equipped withfour strain gages and a signal conditioning circuit. The system measures strain inthe generator, converts it to a voltage signal, amplifies it, filters and transmits it.After calibration of the nodes, forces can be extracted indirectly. This thesisdescribes considerations made during design of the system as well as its differentparts and configurations.

The diplomma thesis is dealing with possibilities of Signal to noise ratio measurement by method, which is based on direct measurement. It is chosen the most suitable method – signal and noise separation to two different parallel signal branches, where is measured signal strength in one branch and root mean square value in the other. The thesis is consisted of a concept of detail block scheme of Signal to noise ratio meter, which was designed in terms of theoretical knowledge. Particular functional blocks were circuit-designed, the active and passive parts were chosen and their function were described. There were made simulation and displayed input and output time flows. There is designed the whole connection of engineered Signal to noise ratio meter in the last part of my thesis. The double-sided board of printed circuit is contained too. It was created simple programme for supervisor micro-processor. Thereby were constructed complete bases for realization.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2009.
ENGLISH ABSTRACT: The purpose of a solid state transformer (SST) is to use power electronic converters to mimic the operation of the conventional distribution transformer. These power electronic converters are proposed to overcome the disadvantages of the conventional distribution transformer. The advantages of a SST include near perfect voltage regulation and harmonic isolation between the primary and secondary windings of the transformer. This thesis discusses the design and development of the different converters in a solid state transformer (SST). A prototype modular back-to-back converter is developed for the input and isolation stage of the SST. The isolation stage consists of a high voltage DC-DC converter, which transfers power across the isolation barrier of the SST. This stage is evaluated in the laboratory with special attention being paid to the efficiency of the converter. The second aspect that this thesis addresses is the output stage of the SST, namely a three phase inverter. The discussion of the output stage focuses on the losses occurring in the inverter. The switching device losses are calculated by means of an adapted numerical method as opposed to using conventional analytical methods. The presented numerical method is compared to the existing analytical method and the findings are discussed. A double loop control strategy is implemented for the output stage inverter. The inner current loop utilizes a predictive control strategy. The control analysis of the double loop controller is discussed and evaluated in the laboratory. All the converters that are discussed in this thesis are evaluated in the laboratory and the relevant measurements are included.
AFRIKAANSE OPSOMMING: Die doel van ’n drywingselektroniese transformator (DET) is om drywingselektroniese omsetters te gebruik om die werking van die konvensionele distribusietransformator na te boots. Hierdie drywingselektroniese omsetters word voorgestel ten einde die nadele van die konvensionele distribusietransformator te bowe te kom. Die voordele van ’n DET sluit in: feitlik perfekte regulering van spanning en harmoniese isolasie tussen die primˆere en sekondˆere windings van die transformator. Hierdie tesis bespreek die ontwerp en ontwikkeling van die verskillende omsetters in ’n drywingselektroniese transformator (DET). ’n Prototipe modulˆere rug-aan-rug-omsetter word ontwikkel vir die intree- en isolasiefase van die DET. Die isolasiefase bestaan uit ’n hoogspanning- GS-GS omsetter, wat drywing oor die isolasiegrens van die DET heen oordra. Hierdie omsetter word in die laboratorium ge¨evalueer met besondere aandag aan die doeltreffendheid van die omsetter. Die tweede aspek waarna in hierdie tesis gekyk word, is die uittreefase van die DET, naamlik ’n driefaseomsetter. Die bespreking van die uittreefase fokus egter op die verliese wat in die omsetter voorkom. Die verliese van die skakelaars word bereken deur middel van ’n aangepaste numeriese metode teenoor die gebruik van konvensionele analitiese metodes. Die numeriese metode wat aangebied word, word vergelyk met die bestaande analitiese metode en die bevindings word bespreek. ’n Dubbellus-beheerstrategie word vir die uittreefase-omsetter ge¨ımplementeer. Die binneste stroomlus word ge¨ımplementeer deur van ’n voorspelbare beheerstrategie gebruik te maak. Die beheeranalise van die dubbellusbeheerder word bespreek en in die laboratorium ge¨evalueer. Al die omsetters wat in hierdie tesis bespreek word, word in die laboratorium ge¨evalueer en die relevante metings word ingesluit.

La sophistication grandissante des dispositifs intelligents ultra-portatifs, tels que les smartphones ou les tablettes,crée un besoin d'amélioration des performances des organes de conversion de puissance.La tendance des technologies d'acheminement de puissance évolue progressivement vers une fréquence plus élevée, une meilleure densité d'intégration et une plus grande flexibilité dans les schémas d'asservissement. La modulation dynamique de tension est utilisée dans les circuits intégrés de gestion de puissances(DVS PMICs)des transmetteurs RF alors que la modulation DVFS est utilisée dans les PMICs dédiées au CPUs et GPUs. Des DCDC flexibles et fonctionnant à haute fréquence constituent aujourd'hui la solution principale en conjonction avec des régulateurs à faible marge de tension (LDO).L'évolution vers des solutions à base de HFDCDC de faibles dimensions pose un défi sérieux en matière de 1)stabilité des boucles d'asservissement,2)de complexité des architectures de contrôle imbriquant des machines d'état asynchrones pour gérer une large dynamique de puissance de sortie et 3)de portabilité de la solutions d'une technologie à une autre.Les solutions les plus courantes atteignent aujourd'hui une gamme de 2 à 6 Mhz de fréquence de découpage grâce à l'usage de contrôleurs à hystérésis qui souffrent de la difficulté à contenir la fréquence de découpage lors des variations de la tension ou du courant en charge.Nous avons voulu dans ce travail étendre l'usage des méthodes de conception et de modélisation conventionnelles comme le modèle petit signal moyen, dans une perspective de simplification et de création de modèles paramétriques. L'objectif étant de rendre la technique de compensation flexible et robuste aux variations de procédés de fabrication ou bien aux signaux parasités inhérents à la commutation de puissance.Certes, le modèle moyen petit signal, au demeurant bien traité dans la littérature, réponds amplement à la problématique de compensation des DCDCs notamment quand la stabilité s'appuie sur le zéro naturel à haute fréquence inhérent à la résistance série ESR de la capacité de sortie, mais les HFDCDC actuels utilisent des capacités MLCC ayant une très faible ESR et font appel à des techniques de compensation paramétriques imbriquant le schéma de compensation dans la génération même du rapport cyclique. La littérature existante sur le fonctionnement de la machine d'état, se contente d'une description simpliste de convertisseurs PWM/PFM mais ne donne que très peu d'éléments sur la gestion des opérations synchrones/asynchrones alternant PWM,PFM,écrêtage de courant, démarrage ou détection de défaillance. Dans ce travail, notre études est axée sur les deux aspects suivants:1)La modélisation paramétrique et la compensation de la boucle d'asservissement de HFDCDC et 2)la portabilité de la conception de la machine d'états du contrôleur notamment lorsqu'elle intègre des transitions complexes entre les modes.Dans la première section, nous avons développé un modèle petit signal moyen d'un convertisseur Buck asservi en mode courant-tension et nous l'avons analysé pour faire apparaitre les contributions proportionnelle, intégrale et dérivé dans la boucle. Nous avons démontré la possibilité d'utiliser le retour en courant pour assurer l'amortissement nécessaire et la stabilité de la boucle pour une large dynamique de variations des conditions de charge.Dans la seconde section, nous avons développé une architecture de machine d'états sophistiquée basé sur la méthode d'Huffman avec un effort substantiel d'abstraction que nous a permis de la concevoir en description RTL pour une gestion fiable du fonctionnement asynchrone et temps réel.Notre contribution théorique a fait l'objet d'une réalisation d'un PMIC de test comportant deux convertisseurs Buck cadencés à 12MHz en technologie BiCMOS 0.5um/0.18um. Les performances clefs obtenues sont:une surtension de 50mV pendant 2us suite à l'application d'un échelon de courant de 300mA
The continuous sophistication of smart handheld devices such as smartphones and tablets creates an incremental need for improving the performances of the power conversion devices. The trend in power delivery migrates progressively to higher frequency, higher density of integration and flexibility of the control scheme. Dynamic Voltage Scaling Power Management ICs (DVS PMIC) are now systematically used for powering RF Transmitters and DVFS PMICS using Voltage and Frequency scaling are used for CPUs and GPUs. Flexible High frequency (HF) DC/DC converters in conjunction with low dropout LDOs constitute the main solution largely employed for such purposes. The migration toward high frequency/small size DCDC solutions creates serious challenges which are: 1) the stability of the feedback loop across a wide range of loading voltage and current conditions 2) The complexity of the control and often-non-synchronous state machine managing ultra large dynamics and bridging low power and high power operating modes, 3) The portability of the proposed solution across technology processes.The main stream solutions have so far reached the range of 2 to 6 MHz operation by employing systematically sliding mode or hysteretic converters that suffer from their variable operating frequency which creates EMI interferences and lead to integration problems relative to on-chip cross-talk between converters.In this work we aim at extend the use of traditional design and modeling techniques of power converters especially the average modeling technique by putting a particular care on the simplification of the theory and adjunction of flexible compensation techniques that don't require external components and that are less sensitive to process spread, or to high frequency substrate and supply noise conditions.The Small Signal Average Models, widely treated in the existing literature, might address most needs for system modeling and external compensation snubber design, especially when aiming on the high frequency natural zero of the output capacitor. However, HFDCDC converters today use small size MLCC capacitors with a very low ESR which require using alternative techniques mixing the compensation scheme with the duty cycle generation itself. The literature often provides a simplistic state machine description such as PWM/PFM operations but doesn't cover combined architectures of synchronous / non synchronous mode operations such as PWM, PFM, Current Limit, Boundary Clamp, Start, Transitional and finally Fault or Protection modes.In our work, we have focused our study on two main axes: 1) The parametric modeling and the loop compensation of HFDCDC and 2) the scalability of the control state machine and mode inter-operation. In the first part, we provided a detailed small signal averaged model of the “voltage and current mode buck converter” and we depicted it to emphasize and optimize the contributions of the Proportional, Integral and Derivative feedback loops. We demonstrated the ability to use the current feedback to damp and stabilize the converter with a wide variety of loading conditions (resistive or capacitive). In the second part, we provided architecture of the mode control state machine with different modes like the PWM, PFM, soft-start, current limit,… .The technique we have used is inspired by Huffman machine with a significant effort to make it abstract and scalable. The state machine is implemented using RTL coding based on a generic and scalable approach.The theoretical effort has been implemented inside a real PMIC test-chip carrying two 12MHz buck converters, each employing a voltage and current mode feedback loop. The chip has been realized in a 0.5um / 0.18um BiCMOS technology and tested through a dedicate Silicon validation platform able to test the analog, digital and power sections. The key performance obtained is a 50mV load transient undershoot / overshoot during 2us following a load step of 300mA (slope 0.3A/ns)

碩士
國立雲林科技大學
電子與資訊工程研究所
93
An improved CMOS voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the non-linear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically the substrate-bias effect of the MOS transistor is treated more thoroughly in our design. Consequently, the non-linearity of the large-signal transresistance of the converter, caused mainly by the body effect of a NMOS transistor in a previously published converter, is greatly minimized. In order to compensate the resultant voltage inversion created by the switching from NMOS transistors to PMOS transistors in the resistor-replacement and voltage-level shifting in the proposed circuit, a voltage-inversion sub-circuit is devised and employed in our converter. The voltage-to-current converter is designed and fabricated in a 0.35μm CMOS technology. The fabricated circuit occupies an area of 267μm×197μm（~0.053mm2） and dissipates less than 3.92mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 input voltage, the total harmonic distortion (THD) of the output current is less than 1.5%.

碩士
國立雲林科技大學
電子與資訊工程研究所
97
This dissertation proposes a design of wide band linear voltage-to-current converter, which promotes the PSRR (Power Supply Rejection Ratio) of the circuit by implementing the input and output stages with NMOS transistors, as well as decreases the non-linear effect due to mobility degradation with the current sum of two transistors, which operate in the linear and saturation regions respectively. In addition, by using circuit architecture of feedback, the zero and pole can be moved to the higher frequency, which results in that circuit can be applied in the wider band. This work is implemented by TSMC 0.35um 2P4M 3.3V CMOS process. When the output is loaded by 5pf in 3.3V CMOS process, we enable the operational range, transconductance and wide band to reach to 1.2V, 0.983~1.007 normalized value and 85.5MHz respectively, while the power dissipation is 4.58mW in 1.6V. The realistic measurement of the work shows a transconductance with 0.975~1.032 normalized value.

碩士
逢甲大學
電子工程所
91
An improved CMOS voltage-to-current converter is presented. The resistors of a conventional voltage-to-current converter is replaced by two PMOS transistors, operating in the triode region and saturation region, respectively, and combine their drain current through a current mirror to generate an output current which is a linear function of the applied input voltage. Because PMOS transistors are employed in the resistor-replacement and voltage level shifting, the non-linearity of the large-signal transresistance of the improved converter, caused mainly by the body effect of a NMOS transistor in a previously published converter, is greatly minimized. To accurately annihilate the non-linear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically the substrate-bias effect of the MOS transistor is treated more thoroughly in our design. In order to compensate the resultant voltage inversion created by the switching from NMOS transistors to PMOS transistors in the resistor-replacement and voltage level shifting in the proposed converter, a voltage-inversion sub-circuit is devised and included. Our study shows that the proposed circuit shows substantial improvement in the linearity of the large-signal transresistance.

碩士
雲林科技大學
電子與資訊工程研究所
96
This work presents a design of ultra-linear voltage-to-current converter with mobility degradation and threshold-voltage compensations. For mobility degradation in deep submicron processes, the proposed compensation method can effectively decrease the high order nonlinear items within relationship between voltage and current. In addition, through modifying the configuration of current source, the proposed design is insensitive to variation of threshold voltage and also leads to higher power rejection ratio. According to experiment results, we enable a wide operational range and almost constant transconductance that reach to 0.9V and 0.946~1.025 normalized value in 3.3V COMS process respectively. Moreover, the experiment result also shows the proposed design can decrease the variation error less than 3% caused by variation of threshold-voltage which under 3%. The theoretical development and design flow of proposed method are derived completely and this work is implemented by TSMC 0.35um 2P4M 3.3V CMOS process.

碩士
國立成功大學
電機工程學系碩博士班
91
This thesis presents an investigation of the design, analysis, and implementation of 10-bit dual-mode current-steering DAC. The DAC is divided into a digital part and an analog part. In the digital part, the 6-bit MSB is converted into thermometer code and the binary weighted 4-bit LSB is used to get a better DNL error and guarantee monotonicity. In the analog part, the current cell that can provide of different currents is proposed. Thus, the current need to perform the voltage-mode or current-mode operation can be obtained. Besides, the area of current source is properly chosen to overcome mismatch error due to the process variation. A transimpedance amplifier is designed to convert current into voltage through resistor in voltage mode. The current mode DAC directly drives an external resistor. In addition, a high speed and low crossing point switch driver is designed to minimize glitch error during dynamic switching transition. This DAC is fabricated with 0.25μm single-poly, five-metal process. The active area is 0.15 mm2 which is the smallest compared until those published up to now. The post-layout simulation shows that it can achieve 59/56 dB SNDR under a 100 MHz update rate with 7.8MHz/12.3MHz signal frequencies, respectively at voltage-mode operation. At the current-mode operation, the DAC can achieve 58.6/58 dB SNDR under the same condition with voltage mode.

碩士
國立中山大學
電機工程學系研究所
91
The first topic of this thesis is to propose a novel voltage-to-frequency converter (VFC) to provide high sensitivity. The VFC circuit is composed of one current mirror, one current multiplier, and voltage window comparators. The proposed VFC tracks the variations of the stored charge of a built-in capacitor. The voltage window comparator monitors the voltage of the capacitor to determine whether the output is pulled high or pulled down. The worth-case linear range of the output frequency of the proposed VFC is 0 to 55 MHz provided that the input voltage is 0 to 0.9 V. The error is less than 9% while the power dissipation is 0.218 mW. The second topic is to carry out a novel CMOS current-mode high- speed sense amplifier (SA). The proposed SA is composed by cascading a current-mode sense amplifier and a voltage-mode sense amplifier. The small input impedance of the current-mode amplifier alleviates the loading effect on the bitlines of SRAM cells such that the sensing speed is enhanced. The voltage-mode amplifier is responsible for boosting the logic levels to full swing. The worst access time of the proposed design is found to be less than 1.26 ns with a 1 pF load on outputs. The power dissipation is merely 0.835 mW at 793 MHz.

碩士
國立成功大學
電機工程學系
105
This thesis presents the stability-analysis results of a system composed of two offshore wind farms (OWFs) connected to two onshore power grids through a multi-infeed high-voltage direct-current (MI-HVDC) system. The OWFs are based on doubly-fed induction generators (DFIGs), and the MI-HVDC system is based on voltage-source converters (VSCs). With the focus laid on the influence of the common tie line in the MI-HVDC system, small-signal stability and transient stability are analyzed by utilizing system eigenvalues and time-domain simulations, respectively. The simulation results show that a VSC-based MI-HVDC system can be more stable than two VSC-based HVDC links which operate independently from each other. In addition, the stability of the studied VSC-based MI-HVDC link can be significantly influenced by the electrical parameters of the common tie line.

碩士
國立交通大學
電機學院電機與控制學程
100
In recent years, vehicle manufacturers produce many electric vehicles (EV) and hybrid electric vehicles (HEV) for environmental protection. Calculating the State of Charge (SOC) is an important technology in battery management system (BMS). Today, the BMS widely uses coulomb-accumulation method to estimate the SOC. In this thesis, a precise linear voltage-to-current (LVC) converter with an adjust output current function is proposed first. Due to high precision converter, a LiFePO4 battery pack is set up to instantly calculate the charge/discharge power for generating a voltage to the BMS to accurately predict the SOC. The LVC converter consisting of only three MOSFETs is designed to contain the advantages of wide input voltage and output linear current ranges. Simulation results got by HSPICE in 0.25-μm CMOS process demonstrate the error percentage of the LVC converter is smaller than 0.1% , the Total Harmonic Distortion (THD) achives -60dB, and the minimum power consumption is only about 10μW. The proposed LVC converter outputs linear current in various rates by an additional P-type MOSFET. The function of the LVC is similar to a fix resistance that can substitute internal resistors of integrated circuit, which dramatically reduce the demanding area of polysilicon. The output current can be adjusted by two parallel structures that would be more suitable for real demands. The proposed LVC converter combines a linear voltage-to-resistance circuit, a battery charge/discharge determined circuit, and a timing circuit to form a battery pack real-time charge/discharge power calculation circuit to output a voltage that represent the battery pack real-time charge/discharge power. The determination power value is directed to the microprocessor or DSP in the BMS to calculate the actual accumulation power in the battery pack without sampling, A/D converter, and multiplication operation, which may increase load of the microprocessor or DSP. The output voltage error from process differences is able to be corrected by an additional precise resistor. In frequent charge/discharge current range, simulation results of battery pack power in 0.25-μm CMOS process show the prediction error in battery pack power value is smaller than 2.5% compared to the correct value.

Nesta dissertação de mestrado foi desenvolvido um sensor de temperatura com saída digital implementado em circuito integrado, para utilização em sensores de imagem CMOS. O projeto foi executado utilizando a tecnologia DongBu 130nm. Este projeto permite obter uma saída digital relacionada com a temperatura de uma forma linear sendo possível saber a temperatura na qual o sistema se encontra inserido. O sensor de temperatura digital assenta em duas partes principais: o sensor de temperatura com saída analógica e um conversor de analógico para digital. Assim foi iniciado o projeto com o estudo do princípio de funcionamento de detetores de temperatura (sensor de temperatura), e o efeito que ocorre nos dispositivos com a variação da mesma. Após o estudo foi implementado o esquemático e o layout referente ao sensor de temperatura analógico, fazendo as simulações e testando assim o seu correto funcionamento. Na segunda parte foram analisadas quais os ADC que melhor se adaptavam ao pretendido. Novamente foi implementado o esquemático implementando circuitos de referência de tensão e de corrente necessários ao correto funcionamento do mesmo, e finalmente procedeu-se à implementação do layout referente à ADC. Numa última fase juntou-se o sensor de temperatura analógico à ADC formando assim o sensor de temperatura digital. Nesta última fase foram feitas verificações ao layout, nomeadamente, DRC, LVS e PEX garantindo que todo o sistema funciona como esperado. Os resultados obtidos na prática mostram que a solução implementada compre os requisitos impostos nos objetivos, garantindo uma boa linearidade do sensor de temperatura que juntamente com a ADC garantem um erro máximo de 0.5ºC ocupando uma área de 0.016mm2.
In this master thesis, an on chip digital temperature sensor for CMOS image sensors is developed. The project was implemented using DongBu 130nm technology. This project allows us to obtain a digital output linearly related with the temperature in which the system is placed. The digital temperature sensor relies on two main parts: the temperature sensor with an analog output and an analog-to-digital converter. Thus, the project was started with the study of different temperature sensing principles (temperature sensor), and the effect that occurs in devices with temperature variation. After that study, the schematic and layout of the analogue temperature sensor were implemented and simulated using a spice level simulator. In the second part, the ADCs were analysed, choosing which ones were better adapted for this project. Again, the schematic was implemented joining the current and voltage reference circuits necessary for the correct operation, and finally the ADC layout was implemented. In the last phase the analogue temperature sensor was added to the ADC, forming the digital temperature sensor. In this last phase we made some layout verification, and post layout simulation (DRC, LVS and PEX) ensuring that the whole system works as expected. The results obtained in practice show that the implemented solution fulfils the requirements imposed in the objectives, guaranteeing a good linearity of the temperature sensor that together with the ADC guarantee a maximum error of 0.5ºC, occupying an area of 0.016mm2 for the whole system, including the reference circuits.

Indiana University-Purdue University Indianapolis (IUPUI)
The substantial increase demand for electrical energy requires high efficient apparatus dealing with energy conversion. Several technologies have been suggested to implement power supplies with higher efficiency, such as multilevel and interleaved converters. This thesis proposes an energy conversion unit with an optimized number of output voltage levels per number of switches nL=nS. The proposed five-level four-switch per phase converter has nL=nS=5/4 which is by far the best relationship among the converters presented in technical literature. A comprehensive literature review on existing five-level converter topologies is done to compare the proposed topology with conventional multilevel converters. The most important characteristics of the proposed configuration are: (i) reduced number of semiconductor devices, while keeping a high number of levels at the output converter side, (ii) only one DC source without any need to balance capacitor voltages, (iii) high efficiency, (iv) there is no dead-time requirement for the converters operation, (v) leg isolation procedure with lower stress for the DC-link capacitor. Single-phase and three-phase version of the proposed converter is presented in this thesis. Details regarding the operation of the configuration and modulation strategy are presented, as well as the comparison between the proposed converter and the conventional ones. Simulated results are presented to validate the theoretical expectations. In addition a fault tolerant converter based on proposed topology for micro-grid systems is presented. A hybrid pulse-width-modulation for the pre-fault operation and transition from the pre-fault to post-fault operation will be discussed. Selected steady-state and transient results are demonstrated to validate the theoretical modeling.

Indiana University-Purdue University Indianapolis (IUPUI)
This thesis presents a converter topology for photovoltaic panels. This topology minimizes the number of switching devices used, thereby reducing power losses that arise from high frequency switching operations. The control strategy is implemented using a simple micro-controller that implements the proportional plus integral control. All the control loops are closed feedback loops hence minimizing error instantaneously and adjusting efficiently to system variations. The energy management between three components, namely, the photovoltaic panel, a battery and a DC link for a microgrid, is shown distributed over three modes. These modes are dependent on the irradiance from the sunlight. All three modes are simulated. The maximum power point tracking of the system plays a crucial role in this configuration, as it is one of the main challenges tackled by the control system. Various methods of MPPT are discussed, and the Perturb and Observe method is employed and is described in detail. Experimental results are shown for the maximum power point tracking of this system with a scaled down version of the panel's actual capability.

Indiana University-Purdue University Indianapolis (IUPUI)
The inner structural characteristics of non-minimum phase DC-DC converters pose a severe limitation in direct regulation of voltage when addressed from a control perspective. This constraint is reflected by the presence of right half plane zeros or the unstable zero dynamics of the output voltage of these converters. The existing controllers make use of one-to-one correspondence between the voltage and current equilibriums of the non-minimum phase converters and exploit the property that when the average output of these converters is the inductor current, the system dynamics are stable and hence they indirectly regulate the voltage. As a result, the system performance is susceptible to circuit parameter and load variation and require additional controllers, which in turn increase the system complexity. In this thesis, a novel approach to this problem is proposed for second order non-minimum phase converters such as Boost and Buck-Boost Converter. Different solutions have been suggested to the problem based on whether the converter is modeled as a linear system or as a nonlinear system. For the converter modeled as a linear system, the non-minimum phase part of the system is decoupled and its transfer function is converted to minimum phase using a parallel compensator. Then the control action is achieved by using a simple proportional gain controller. This method accelerates the transient response of the converter, reduces the initial undershoot in the response, and considerably reduces the oscillations in the transient response. Simulation results demonstrate the effectiveness of the proposed approach. When the converter is modeled as a bilinear system, it preserves the stabilizing nonlinearities of the system. Hence, a more effective control approach is adopted by using Passivity properties. In this approach, the non-minimum phase converter system is viewed from an energy-based perspective and the property of passivity is used to achieve stable zero dynamics of the output voltage. A system is passive if its rate of energy storage is less than the supply rate i.e. the system dissipates more energy than stores. As a result, the energy storage function of the system is less than the supply rate function. Non-minimum phase systems are not passive, and passivation of non-minimum phase power converters is an attractive solution to the posed problem. Stability of non-minimum phase systems can also be investigated by defining the passivity indices. This research approaches the problem by characterizing the degree of passivity i.e. the amount of damping in the system, from passivity indices. Thus, the problem is viewed from a system level rather than from a circuit level description. This method uses feed-forward passivation to compensate for the shortage of passivity in the non-minimum phase converter and makes use of a parallel interconnection to the open-loop system to attain exponentially stable zero dynamics of the output voltage. Detailed analytical analysis regarding the control structure and passivation process is performed on a buck-boost converter. Simulation and experimental results carried out on the test bed validate the effectiveness of the proposed method.

Indiana University-Purdue University Indianapolis (IUPUI)
This research introduces a new design of a converter modified from SEPIC converter (Single end primary inductive converter), capable of generating desired voltage levels and polarities. The new switching converter topology allows for boost and buck of the input voltage theoretically achieving infinite positive and negative voltage levels. The proposed topology utilizes single high frequency switch to perform the power conversion which simplifies the design of the gate driver, but meanwhile, it still retains the ability to provide a wide range of output voltage. Mathematical modeling of the converter and computer simulations are validated by experimental data. To verify its performance a prototype was designed and built. It is experimentally proven that the circuit can generate a desired voltage in the range of voltages up to ±170 V, delivering 480 Watts of power to a resistive load.

Experimental research on high-power converters, particularly in an academic environment, faces severe infrastructural constraints. Usually, power source and loads of required ratings are not available. Further, more importantly, the energy consumption is huge. One possibility is to establish an experimental research platform, comprising of a network of high-power converters, through which power is circulated and which draws only the losses from the mains. This work deals with the establishment of a circulating power test set-up, comprising of two line-side PWM converters, inclusive of control and modulation methods for the two converters. Two types of circulating power test setups are developed. In the first setup, the converters are connected in parallel, on ac as well as dc sides, such that real and/or reactive power is circulated between them. In the second test setup, the dc buses of the converters are separated; hence, only reactive power circulation is possible. These setups are used to conduct heat-run tests with low energy expenditure on the PWM converters at various operating conditions up to power levels of 150 kVA. Further, these are used to validate analytically-evaluated thermal characteristics of high-power PWM converters. A safe thermal limit is derived for such converters in terms of apparent power (kVA) handled, power factor and switching frequency. The effects of voltage sag and of unequal current sharing between parallel IGBT modules on the safe thermal limit are studied. While the power drawn by the circulating-power setup from the grid is much lower than the ratings of the individual converters, the harmonic injection into the mains by the setup could be significant since the harmonics drawn by both converters tend to add up. This thesis investigates carrier interleaving to improve the waveform quality of grid current, drawn by the circulating-power test setup. The study of carrier interleaving is quite general and covers various applications of parallel-connected converters such as unity power factor rectification, static reactive power compensation and grid-connected renewable energy systems. In literature, carrier interleaving has been employed mainly for unity power factor rectifiers, sharing a common dc load equally. In such case, the fundamental components of the terminal voltages of the parallel converters are equal. However, when the power sharing between the two converters is unequal, or when power is circulated between the two converters, the terminal voltages of the two converters are not equal. A method to estimate rms grid current ripple, drawn by parallel-connected converters with equal and/or unequal terminal voltages, in a synchronous reference frame is presented. Further, the influence of carrier interleaving on the rms grid current ripple is studied. The optimum interleaving angle, which minimizes the rms grid current ripple under various applications, is investigated. This angle is found to be a function of modulation index of the converters in the equal terminal voltages case. In the unequal terminal voltages case, the optimum interleaving angle is shown to be a function of the average modulation index of the two parallel converters. The effect of carrier interleaving is experimentally studied on the reactive power circulation setup at different values of kVA and different dc bus voltages. The grid current ripple is measured for different values of interleaving angle. It is found experimentally that the optimum interleaving angle reduces the rms grid current ripple by between 37% and 48%, as compared without interleaving, at various operating conditions. Further, the reactive power circulation test set-up is used to evaluate and compare power conversion losses corresponding to different PWM techniques such as conventional space-vector PWM (CSVPWM), bus-clamping PWM (BCPWM) and advanced bus-clamping PWM methods for static reactive power compensator (STATCOM) application at high power levels. It is demonstrated theoretically as well as experimentally that an advanced bus-clamping PWM method, termed minimum switching loss PWM (MSLPWM), leads to significantly lower power conversion loss than CSVPWM and BCPWM techniques at a given average switching frequency.