Relevant bibliographies by topics / Wafer level packaging for MEMS

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  2. Dissertations / Theses
  3. Books
  4. Book chapters
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Academic literature on the topic 'Wafer level packaging for MEMS'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Wafer level packaging for MEMS"

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Esashi, Masayoshi. "Wafer level packaging of MEMS." Journal of Micromechanics and Microengineering 18, no. 7 (2008): 073001. http://dx.doi.org/10.1088/0960-1317/18/7/073001.

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Gooch, Roland, and Thomas Schimert. "Low-Cost Wafer-Level Vacuum Packaging for MEMS." MRS Bulletin 28, no. 1 (2003): 55–59. http://dx.doi.org/10.1557/mrs2003.18.

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AbstractVacuum packaging of high-performance surface-micromachined uncooled microbolometer detectors and focal-plane arrays (FPAs) for infrared imaging and nonimaging applications, inertial MEMS (microelectromechanical systems) accelerometers and gyroscopes, and rf MEMS resonators is a key issue in the technology development path to low-cost, high-volume MEMS production. In this article, two approaches to vacuum packaging for MEMS will be discussed. The first is component-level vacuum packaging, a die-level approach that involves packaging individual die in a ceramic package using either a sil
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LEE, CHENGKUO. "Progress in Wafer Level MEMS Packaging." Journal of Japan Institute of Electronics Packaging 10, no. 1 (2007): 42–51. http://dx.doi.org/10.5104/jiep.10.42.

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Gooch, R., T. Schimert, W. McCardel, B. Ritchey, D. Gilmour, and W. Koziarz. "Wafer-level vacuum packaging for MEMS." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 17, no. 4 (1999): 2295–99. http://dx.doi.org/10.1116/1.581763.

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Mohri, Mamoru, Masayoshi Esashi, and Shuji Tanaka. "MEMS Wafer-level Packaging Technology Using LTCC Wafer." IEEJ Transactions on Sensors and Micromachines 132, no. 8 (2012): 246–53. http://dx.doi.org/10.1541/ieejsmas.132.246.

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Mohri, Mamoru, Masayoshi Esashi, and Shuji Tanaka. "MEMS Wafer-Level Packaging Technology Using LTCC Wafer." Electronics and Communications in Japan 97, no. 9 (2014): 42–51. http://dx.doi.org/10.1002/ecj.11720.

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Tian, J., S. Sosin, J. Iannacci, R. Gaddi, and M. Bartek. "RF–MEMS wafer-level packaging using through-wafer interconnect." Sensors and Actuators A: Physical 142, no. 1 (2008): 442–51. http://dx.doi.org/10.1016/j.sna.2007.09.004.

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Zoschke, Kai, and Klaus-Dieter Lang. "Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 000698–725. http://dx.doi.org/10.4071/2015dpc-tp31.

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Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packagi
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Wipf, Selin Tolunay, Alexander Göritz, Matthias Wietstruck, et al. "Effect of wafer-level silicon cap packaging on BiCMOS embedded RF-MEMS switch performance." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, NOR (2017): 1–4. http://dx.doi.org/10.4071/2017-nor-wipf.

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Abstract In this paper, the effect of silicon (Si) cap packaging on the BiCMOS embedded RF-MEMS switch performance is studied. The RF-MEMS switches are designed and fabricated in a 0.25μm SiGe BiCMOS technology for K-band (18 – 27 GHz) applications. The packaging is done based on a wafer-to-wafer bonding technique and the RF-MEMS switches are electrically characterized before and after the Si cap packaging. The experimental data shows the effect of the wafer-level Si cap package on the C-V and S-parameter measurements. The performed 3D FEM simulations prove that the low resistive Si cap, speci
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Saha, Rajarshi, Nathan Fritz, Sue Ann Bidstrup-Allen, and Paul A. Kohl. "Packaging-compatible wafer level capping of MEMS devices." Microelectronic Engineering 104 (April 2013): 75–84. http://dx.doi.org/10.1016/j.mee.2012.11.010.

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Dissertations / Theses on the topic "Wafer level packaging for MEMS"

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Torunbalci, Mert Mustafa. "Wafer Level Vacuum Packaging Of Mems Sensors And Resonators." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613015/index.pdf.

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This thesis presents the development of wafer level vacuum packaging processes using Au-Si eutectic and glass frit bonding contributing to the improvement of packaging concepts for a variety of MEMS devices. In the first phase of this research, micromachined resonators and pirani vacuum gauges are designed for the evaluation of the vacuum package performance. These designs are verified using MATLAB and Coventorware finite element modeling tool. Designed resonators and pirani vacuum gauges and previously developed gyroscopes with lateral feedthroughs are fabricated with a newly developed Silico
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Collins, Gustina B. "Design, Fabrication and Testing of Conformal, Localized Wafer-level Packaging for RF MEMS Devices." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29673.

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A low-cost, low-temperature packaging concept is proposed for localized sealing and control of the ambient of a device cavity appropriate for Radio-Frequency (RF) Micro- Electro-Mechanical (MEMS) devices, such as resonators and switches. These devices require application specific packaging to facilitate their integration, provide protection from the environment, and control interactions with other circuitry. In order to inte- grate these devices into standard integrated circuit (IC) process flows and minimize damage due to post-fabrication steps, packaging is performed at the wafer level. In
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Neysmith, Jordan M. "A modular, direct chip attach, wafer level MEMS package : architecture and processing." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17559.

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Lemoine, Dominique. "Vacuum packaging at the wafer level for monolithic integration of MEMS and CMOS." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=94920.

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A novel vacuum (< 20 mTorr) encapsulation technology for the packaging of micro-electromechanical systems (MEMS) at the wafer level is presented. Because of its low temperature budget (< 350°C), as well as material and chemical compatibility, it supports monolithic integration with CMOS electronics for system-on-chip (SoC) designs. The packaging flow is also suitable for a large range of surface micromachining processes. Hermetic device encapsulation is performed by anodic wafer bonding, while bulk-etched transverse through-wafer vias are used to connect electrically with the encapsulated syst
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Braun, Stefan. "Wafer-level heterogeneous integration of MEMS actuators." Doctoral thesis, Stockholm : Skolan för elektro- och systemteknik, Kungliga Tekniska högskolan, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-11833.

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Tenchine, Lionel. "Effet getter de multicouches métalliques pour des applications MEMS. Etude de la relation Elaboration - Microstructure - Comportement." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00609077.

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L'objectif de cette thèse est d'établir les liens entre élaboration, microstructure et comportement des getters non-évaporables (NEG) en couches minces, en vue de leur utilisation dans le cadre du packaging collectif des MEMS sous vide ou sous atmosphère contrôlée. Après une étude bibliographique sur l'herméticité des MEMS et l'effet getter, la modification du comportement de piégeage de gaz par les NEG couches minces, engendré par l'ajout de sous-couches métalliques, est mise en évidence. Afin d'expliquer cette influence, la microstructure des couches minces est étudiée, notamment sa dépendan
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Iannacci, Jacopo <1977&gt. "Mixed-domain simulation and hybrid wafer-level packaging of RF-MEMS devices for wireless applications." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/464/.

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In questa tesi verranno trattati sia il problema della creazione di un ambiente di simulazione a domini fisici misti per dispositivi RF-MEMS, che la definizione di un processo di fabbricazione ad-hoc per il packaging e l’integrazione degli stessi. Riguardo al primo argomento, sarà mostrato nel dettaglio lo sviluppo di una libreria di modelli MEMS all’interno dell’ambiente di simulazione per circuiti integrati Cadence c . L’approccio scelto per la definizione del comportamento elettromeccanico dei MEMS è basato sul concetto di modellazione compatta (compact modeling). Questo significa che il co
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Hofmann, Lutz. "3D-Wafer Level Packaging approaches for MEMS by using Cu-based High Aspect Ratio Through Silicon Vias." Doctoral thesis, Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-231412.

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For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (T
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Antelius, Mikael. "Wafer-scale Vacuum and Liquid Packaging Concepts for an Optical Thin-film Gas Sensor." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-119839.

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This thesis treats the development of packaging and integration methods for the cost-efficient encapsulation and packaging of microelectromechanical (MEMS) devices. The packaging of MEMS devices is often more costly than the device itself, partly because the packaging can be crucial for the performance of the device. For devices which contain liquids or needs to be enclosed in a vacuum, the packaging can account for up to 80% of the total cost of the device. The first part of this thesis presents the integration scheme for an optical dye thin film NO2-gas sensor, designed using cost-efficient
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Hofmann, Lutz [Verfasser], Stefan E. [Akademischer Betreuer] Schulz, Stefan E. [Gutachter] Schulz, and Gerald [Gutachter] Gerlach. "3D-Wafer Level Packaging approaches for MEMS by using Cu-based High Aspect Ratio Through Silicon Vias / Lutz Hofmann ; Gutachter: Stefan E. Schulz, Gerald Gerlach ; Betreuer: Stefan E. Schulz." Chemnitz : Universitätsbibliothek Chemnitz, 2017. http://d-nb.info/1214649386/34.

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Books on the topic "Wafer level packaging for MEMS"

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Lau, John H. Fan-Out Wafer-Level Packaging. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8884-1.

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Qu, Shichun, and Yong Liu. Wafer-Level Chip-Scale Packaging. Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4939-1556-9.

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International, TechSearch. Flip chip and wafer level packaging trends and market forecasts. TechSearch International, 2004.

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Lau, John H. Fan-Out Wafer-Level Packaging. Springer, 2018.

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Lau, John H. Fan-Out Wafer-Level Packaging. Springer, 2018.

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Yong, Liu, and Shichun Qu. Wafer-Level Chip-Scale Packaging: Analog and Power Semiconductor Applications. Springer, 2014.

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Yong, Liu, and Shichun Qu. Wafer-Level Chip-Scale Packaging: Analog and Power Semiconductor Applications. Springer, 2016.

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Kroehnert, Steffen, and Beth Keser. Advances in Embedded and Fan-Out Wafer Level Packaging Technologies. Wiley & Sons, Incorporated, John, 2019.

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Kroehnert, Steffen, and Beth Keser. Advances in Embedded and Fan-Out Wafer Level Packaging Technologies. Wiley & Sons, Incorporated, John, 2019.

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Keser, Beth, and Steffen Kroehnert, eds. Advances in Embedded and Fan‐Out Wafer‐Level Packaging Technologies. Wiley, 2019. http://dx.doi.org/10.1002/9781119313991.

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Book chapters on the topic "Wafer level packaging for MEMS"

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Choa, Sung Hoon. "Experimental Studies of Through-Wafer Copper Interconnect in Wafer Level MEMS Packaging." In Fracture and Damage Mechanics V. Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-413-8.231.

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Park, Gil Soo, Ji Hyuk Yu, Sang Won Seo, et al. "Wafer Level Hermetic Packaging for RF-MEMS Devices Using Electroplated Gold Layers." In Experimental Mechanics in Nano and Biotechnology. Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-415-4.617.

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Wang, Qian, Sung Hoon Choa, Woon Bae Kim, Jun Sik Hwang, Suk Jin Ham, and Chang Youl Moon. "Reliability of Hermetic RF MEMS Wafer Level Packaging Using Au-Sn Eutectic Bonding." In Experimental Mechanics in Nano and Biotechnology. Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-415-4.609.

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Spearing, S. Mark. "Materials, Structures and Packaging." In Multi-Wafer Rotating MEMS Machines. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-77747-4_3.

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Lau, John H. "Embedded Chip Packaging." In Fan-Out Wafer-Level Packaging. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8884-1_4.

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Töpper, Michael. "Wafer Level Chip Scale Packaging." In Materials for Advanced Packaging. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-45098-8_15.

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Töpper, Michael. "Wafer Level Chip Scale Packaging." In Materials for Advanced Packaging. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-78219-5_16.

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Lau, John H. "Fan-Out Wafer/Panel-Level Packaging." In Semiconductor Advanced Packaging. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1376-0_4.

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Fan, Xuejun. "Thermal Stresses in Wafer-Level Packaging." In Encyclopedia of Thermal Stresses. Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-007-2739-7_935.

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Qu, Shichun, and Yong Liu. "Demand and Challenges for Wafer-Level Chip-Scale Analog and Power Packaging." In Wafer-Level Chip-Scale Packaging. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-1556-9_1.

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Conference papers on the topic "Wafer level packaging for MEMS"

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Esashi, E. "Wafer level packaging of MEMS." In TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference. IEEE, 2009. http://dx.doi.org/10.1109/sensor.2009.5285574.

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Lee, Sang-Hyun, Jay Mitchell, Warren Welch, Sangwoo Lee, and Khalil Najafi. "Wafer-level vacuum/hermetic packaging technologies for MEMS." In MOEMS-MEMS, edited by Richard C. Kullberg and Rajeshuni Ramesham. SPIE, 2010. http://dx.doi.org/10.1117/12.843831.

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Heck, John M., Leonel R. Arana, Bill Read, and Thomas S. Dory. "Ceramic Via Wafer-Level Packaging for MEMS." In ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73369.

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We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection
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Nicolas, S., S. Caplet, F. Greco, M. Audoin, X. Baillin, and S. Fanget. "3D MEMS high vacuum wafer level packaging." In 2012 IEEE 62nd Electronic Components and Technology Conference (ECTC). IEEE, 2012. http://dx.doi.org/10.1109/ectc.2012.6248857.

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Miyamoto, Asei, Taichi Hashimoto, Kenichi Makimura, Kensuke Kanda, Takayuki Fujita, and Kazusuke Maenaka. "Wafer Level Packaging for MEMS Geiger Counter." In 2012 5th International Conference on Emerging Trends in Engineering and Technology (ICETET). IEEE, 2012. http://dx.doi.org/10.1109/icetet.2012.20.

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Caplet, Stephane, Nicolas Sillon, Marie-Therese Delaye, and Pascale Berruyer. "Vacuum wafer-level packaging for MEMS applications." In Micromachining and Microfabrication, edited by John A. Yasaitis, Mary Ann Perez-Maher, and Jean Michel Karam. SPIE, 2003. http://dx.doi.org/10.1117/12.478249.

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Ferguson, A., M. Gaukroger, D. Karnakis, et al. "Recent Breakthroughs in Tight Pitch Laser Microdrilling for Mems Guide Plates." In 2019 International Wafer Level Packaging Conference (IWLPC). IEEE, 2019. http://dx.doi.org/10.23919/iwlpc.2019.8913883.

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Lellouchi, Djemel, Jérémie Dhennin, Xavier Lafontan, et al. "A new method for hermeticity testing of wafer-level packaging." In MOEMS-MEMS, edited by Richard C. Kullberg and Rajeshuni Ramesham. SPIE, 2010. http://dx.doi.org/10.1117/12.839860.

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Tian, J., J. Iannacci, S. Sosin, R. Gaddi, and M. Bartek. "RF-MEMS wafer-level packaging using through-wafer via technology." In 2006 8th Electronics Packaging Technology Conference. IEEE, 2006. http://dx.doi.org/10.1109/eptc.2006.342755.

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Yun, C. H., J. R. Martin, T. Chen, and D. Davis. "MEMS Wafer-Level Packaging with Conductive Vias and Wafer Bonding." In TRANSDUCERS 2007 - 2007 International Solid-State Sensors, Actuators and Microsystems Conference. IEEE, 2007. http://dx.doi.org/10.1109/sensor.2007.4300577.

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Reports on the topic "Wafer level packaging for MEMS"

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Forehand, David I., and Charles L. Goldsmith. Wafer Level Micropackaging for RF MEMS Switches. Defense Technical Information Center, 2005. http://dx.doi.org/10.21236/ada433802.

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