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1
Torunbalci, Mert Mustafa. "Wafer Level Vacuum Packaging Of Mems Sensors And Resonators." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613015/index.pdf.
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This thesis presents the development of wafer level vacuum packaging processes using Au-Si eutectic and glass frit bonding contributing to the improvement of packaging concepts for a variety of MEMS devices. In the first phase of this research, micromachined resonators and pirani vacuum gauges are designed for the evaluation of the vacuum package performance. These designs are verified using MATLAB and Coventorware finite element modeling tool. Designed resonators and pirani vacuum gauges and previously developed gyroscopes with lateral feedthroughs are fabricated with a newly developed Silicon-On-Glass (SOG) process. In addition to these, a process for the fabrication of similar devices with vertical feedthroughs is initiated for achieving simplified packaging process and lower parasitic capacitances. Cap wafers for both types of devices with lateral and vertical feedthroughs are designed and fabricated. The optimization of Au-Si eutectic bonding is carried out on both planar and non-planar surfaces. The bonding quality is evaluated using the deflection test, which is based on the deflection of a thinned diaphragm due to the pressure difference between inside and outside the package. A 100% yield bonding on planar surfaces is achieved at 390º<br>C with a
v
holding time and bond force of 60 min and 1500 N, respectively. On the other hand, bonding on surfaces where 0.15&mu<br>m feedthrough lines exist can be done at 420º<br>C with a 100% yield using same holding time and bond force. Furthermore, glass frit bonding on glass wafers with lateral feedthroughs is performed at temperatures between 435-450º<br>C using different holding periods and bond forces. The yield is varied from %33 to %99.4 depending on the process parameters. The fabricated devices are wafer level vacuum packaged using the optimized glass frit and Au-Si eutectic bonding recipes. The performances of wafer level packages are evaluated using the integrated gyroscopes, resonators, and pirani vacuum gauges. Pressures ranging from 10 mTorr to 60 mTorr and 0.1 Torr to 0.7 Torr are observed in the glass frit packages, satisfying the requirements of various MEMS devices in the literature. It is also optically verified that Au-Si eutectic packages result in vacuum cavities, and further study is needed to quantify the vacuum level with vacuum sensors based on the resonating structures and pirani vacuum gauges.
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Collins, Gustina B. "Design, Fabrication and Testing of Conformal, Localized Wafer-level Packaging for RF MEMS Devices." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29673.
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A low-cost, low-temperature packaging concept is proposed for localized sealing and
control of the ambient of a device cavity appropriate for Radio-Frequency (RF) Micro-
Electro-Mechanical (MEMS) devices, such as resonators and switches. These devices
require application specific packaging to facilitate their integration, provide protection
from the environment, and control interactions with other circuitry. In order to inte-
grate these devices into standard integrated circuit (IC) process flows and minimize
damage due to post-fabrication steps, packaging is performed at the wafer level.
In this work Indium and Silver are used to seal a monolithic localized hermetic pack-
age. The cavity protecting the device is formed using standard lithography-based
processing techniques. Metal walls are built up from the substrate and encapsulated
by a glass or silicon lid to create a monolithic micro-hermetic package surrounding a
predefined RF microsystem. The bond for the seal is then formed by rapid alloying
of Indium and Silver using a temperature greater than that of the melting point of
Indium. This ensures that the seal formed can subsequently function at tempera-
tures higher than the melting temperature of pure Indium. This method offers a
low-temperature bonding technique with thermal robustness suitable for wafer-level
process integration. The ultimate goal is to create a seal in a vacuum environment.
In this dissertation, design trade-offs made in wafer-level packaging are explained
using thermo-mechanical stress and electrical performance simulations. Prototype
passive microwave circuits are packaged using the developed packaging process and
the performance of the fabricated circuits before and after packaging is analyzed. The
effect of the package on coplanar waveguide structures are characterized by measur-
ing scattering parameters and models are developed as a design tool for wafer-level
package integration. The small scale of the localized package is expected to provide
greater reliability over conventional full chip packages.<br>Ph. D.
3
Neysmith, Jordan M. "A modular, direct chip attach, wafer level MEMS package : architecture and processing." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17559.
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Lemoine, Dominique. "Vacuum packaging at the wafer level for monolithic integration of MEMS and CMOS." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=94920.
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A novel vacuum (< 20 mTorr) encapsulation technology for the packaging of micro-electromechanical systems (MEMS) at the wafer level is presented. Because of its low temperature budget (< 350°C), as well as material and chemical compatibility, it supports monolithic integration with CMOS electronics for system-on-chip (SoC) designs. The packaging flow is also suitable for a large range of surface micromachining processes. Hermetic device encapsulation is performed by anodic wafer bonding, while bulk-etched transverse through-wafer vias are used to connect electrically with the encapsulated system. Silicon carbide (SiC) is successfully utilized as a means to membrane stress cancellation and hermeticity improvement. Experimental results are presented, and the versatility of the technology proposed in this work is illustrated through a comparison with various other state-of-the-art wafer-level packaging technologies. Other applications of the technology beyond packaging, i.e. film bulk acoustic resonators (FBAR) and pressure sensors, are also discussed.<br>Une nouvelle technologie sous vide (< 20 mTorr) au niveau de la tranche pour l'encapsulation de systèmes microélectromécaniques (MEMS) est présentée. Grâce à son faible budget thermique (< 350°C), ainsi que sa compatibilité tant au niveau chimique que des matériaux, elle convient pour l'intégration monolithique avec de l'électronique de type CMOS, afin de réaliser des systèmes mono-puce (SoC). La séquence d'encapsulation est compatible avec une grande variété de procédés de micromachinage en surface. L'encapsulation hermétique des dispositifs est accomplie par collage anodique de tranches, alors qu'on utilise la gravure en profondeur pour la création de vias à travers la tranche, afin d'établir un contact électrique. Du carbure de silicium (SiC) est utilisé avec succès pour minimiser les contraintes mécaniques des membranes et améliorer leur herméticité. On présente les résultats expérimentaux, tout en soulignant l'utilité de la technologie développée lors de ce travail en la comparant avec d'autres technologies récentes pour l'encapsulation au niveau de la tranche. D'autres applications de la technologie au delà de l'encapsulation sont également présentées, soit le FBAR et le capteur de pression.
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Braun, Stefan. "Wafer-level heterogeneous integration of MEMS actuators." Doctoral thesis, Stockholm : Skolan för elektro- och systemteknik, Kungliga Tekniska högskolan, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-11833.
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Tenchine, Lionel. "Effet getter de multicouches métalliques pour des applications MEMS. Etude de la relation Elaboration - Microstructure - Comportement." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00609077.
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L'objectif de cette thèse est d'établir les liens entre élaboration, microstructure et comportement des getters non-évaporables (NEG) en couches minces, en vue de leur utilisation dans le cadre du packaging collectif des MEMS sous vide ou sous atmosphère contrôlée. Après une étude bibliographique sur l'herméticité des MEMS et l'effet getter, la modification du comportement de piégeage de gaz par les NEG couches minces, engendré par l'ajout de sous-couches métalliques, est mise en évidence. Afin d'expliquer cette influence, la microstructure des couches minces est étudiée, notamment sa dépendance aux paramètres d'élaboration et aux traitements thermiques. Ensuite, le comportement macroscopique de piégeage de l'azote est caractérisé, de même que les mécanismes microscopiques d'activation et de pompage. Ces derniers permettent finalement d'élaborer quelques recommandations pour l'intégration des NEG couches minces dans les MEMS.
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Iannacci, Jacopo <1977>. "Mixed-domain simulation and hybrid wafer-level packaging of RF-MEMS devices for wireless applications." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/464/.
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In questa tesi verranno trattati sia il problema della creazione di un ambiente di simulazione a domini fisici misti per dispositivi RF-MEMS, che la definizione di un processo di fabbricazione ad-hoc per il packaging e l’integrazione degli stessi. Riguardo al primo argomento, sarà mostrato nel dettaglio lo sviluppo di una libreria di modelli MEMS all’interno dell’ambiente di simulazione per circuiti integrati Cadence c . L’approccio scelto per la definizione del comportamento elettromeccanico dei MEMS è basato sul concetto di modellazione compatta (compact modeling). Questo significa che il comportamento fisico di ogni componente elementare della libreria è descritto per mezzo di un insieme limitato di punti (nodi) di interconnessione verso il mondo esterno. La libreria comprende componenti elementari, come travi flessibili, piatti rigidi sospesi e punti di ancoraggio, la cui opportuna interconnessione porta alla realizzazione di interi dispositivi (come interruttori e capacità variabili) da simulare in Cadence c . Tutti i modelli MEMS sono implementati per mezzo del linguaggio VerilogA c di tipo HDL (Hardware Description Language) che è supportato dal simulatore circuitale Spectre c . Sia il linguaggio VerilogA
c che il simulatore Spectre c sono disponibili in ambiente Cadence c . L’ambiente di simulazione multidominio (ovvero elettromeccanico) così ottenuto permette di interfacciare i
dispositivi MEMS con le librerie di componenti CMOS standard e di conseguenza la simulazione di blocchi funzionali misti RF-MEMS/CMOS. Come esempio, un VCO (Voltage Controlled Oscillator) in cui l’LC-tank è realizzato in tecnologia MEMS mentre la parte attiva con transistor MOS di libreria sarà
simulato in Spectre c . Inoltre, nelle pagine successive verrà mostrata una soluzione tecnologica per la fabbricazione di un substrato protettivo (package) da applicare a dispositivi RF-MEMS basata su vie di interconnessione elettrica attraverso un wafer di Silicio. La soluzione di packaging prescelta rende possibili alcune tecniche per l’integrazione ibrida delle parti RF-MEMS e CMOS (hybrid packaging). Verranno inoltre messe in luce questioni riguardanti gli effetti parassiti (accoppiamenti
capacitivi ed induttivi) introdotti dal package che influenzano le prestazioni RF dei dispositivi MEMS incapsulati. Nel dettaglio, tutti i gradi di libertà del processo tecnologico per l’ottenimento del package saranno ottimizzati per mezzo di un simulatore elettromagnetico (Ansoft HFSSTM) al fine di ridurre gli effetti parassiti introdotti dal substrato protettivo. Inoltre, risultati sperimentali raccolti da misure di strutture di test incapsulate verranno mostrati per validare, da un lato, il simulatore Ansoft HFSSTM e per dimostrate, dall’altro, la fattibilit`a della soluzione di packaging proposta. Aldilà dell’apparente debole legame tra i due argomenti sopra menzionati è possibile identificare un unico obiettivo. Da un lato questo è da ricercarsi nello sviluppo di un ambiente di simulazione unificato all’interno del quale il comportamento elettromeccanico dei dispositivi RF-MEMS possa essere studiato ed analizzato. All’interno di tale ambiente, l’influenza del package sul comportamento elettromagnetico degli RF-MEMS può essere tenuta in conto per mezzo di modelli a parametri concentrati (lumped elements) estratti da misure sperimentali e simulazioni agli Elementi Finiti (FEM) della parte di package. Infine, la possibilità offerta dall’ambiente Cadence c relativamente alla simulazione di dipositivi RF-MEMS interfacciati alla parte CMOS rende
possibile l’analisi di blocchi funzionali ibridi RF-MEMS/CMOS completi.
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Hofmann, Lutz. "3D-Wafer Level Packaging approaches for MEMS by using Cu-based High Aspect Ratio Through Silicon Vias." Doctoral thesis, Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-231412.
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For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters<br>Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter
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Antelius, Mikael. "Wafer-scale Vacuum and Liquid Packaging Concepts for an Optical Thin-film Gas Sensor." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-119839.
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This thesis treats the development of packaging and integration methods for the cost-efficient encapsulation and packaging of microelectromechanical (MEMS) devices. The packaging of MEMS devices is often more costly than the device itself, partly because the packaging can be crucial for the performance of the device. For devices which contain liquids or needs to be enclosed in a vacuum, the packaging can account for up to 80% of the total cost of the device. The first part of this thesis presents the integration scheme for an optical dye thin film NO2-gas sensor, designed using cost-efficient implementations of wafer-scale methods. This work includes design and fabrication of photonic subcomponents in addition to the main effort of integration and packaging of the dye-film. A specific proof of concept target was for NO2 monitoring in a car tunnel. The second part of this thesis deals with the wafer-scale packaging methods developed for the sensing device. The developed packaging method, based on low-temperature plastic deformation of gold sealing structures, is further demonstrated as a generic method for other hermetic liquid and vacuum packaging applications. In the developed packaging methods, the mechanically squeezed gold sealing material is both electroplated microstruc- tures and wire bonded stud bumps. The electroplated rings act like a more hermetic version of rubber sealing rings while compressed in conjunction with a cavity forming wafer bonding process. The stud bump sealing processes is on the other hand applied on completed cavities with narrow access ports, to seal either a vacuum or liquid inside the cavities at room temperature. Additionally, the resulting hermeticity of primarily the vacuum sealing methods is thoroughly investigated. Two of the sealing methods presented require permanent mechanical fixation in order to complete the packaging process. Two solutions to this problem are presented in this thesis. First, a more traditional wafer bonding method using tin-soldering is demonstrated. Second, a novel full-wafer epoxy underfill-process using a microfluidic distribution network is demonstrated using a room temperature process.<br><p>QC 20130325</p>
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Hofmann, Lutz [Verfasser], Stefan E. [Akademischer Betreuer] Schulz, Stefan E. [Gutachter] Schulz, and Gerald [Gutachter] Gerlach. "3D-Wafer Level Packaging approaches for MEMS by using Cu-based High Aspect Ratio Through Silicon Vias / Lutz Hofmann ; Gutachter: Stefan E. Schulz, Gerald Gerlach ; Betreuer: Stefan E. Schulz." Chemnitz : Universitätsbibliothek Chemnitz, 2017. http://d-nb.info/1214649386/34.
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Reuter, Danny. "Entwicklung einer Dünnschichtverkappungstechnologie für oberflächennahe Mikrostrukturen." Doctoral thesis, Universitätsbibliothek Chemnitz, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200800721.
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In der vorliegenden Arbeit wird ein neues Verfahren zur Dünnschichtverkappung von oberflächennahen Mikrostrukturen vorgestellt. Ausgehend von den speziellen Anforderungen an die Verkappung oberflächennaher Mikrostrukturen, insbesondere von Strukturen mit hohem Aspektverhältnis, wurden die Verwendung eines Fluor-Kohlenstoff-Polymers als Opferschichtmaterial und die Eignung unterschiedlicher Schichtstapel zur Realisierung der Dünnschichtkappe untersucht. Die resultierende Technologie ermöglicht eine durchgehend trockenchemische Prozessierung. Für die Abschätzung der notwendigen Schichtdicken und den geometrischen Entwurf der Kappenstrukturen, wurden auf Basis der Plattentheorie analytische und numerische Modelle erstellt. Verschiedene Materialkombinationen bestehend aus Siliziumoxid, Siliziumnitrid und Aluminium wurden hinsichtlich ihrer mechanischen und thermomechanischen Eigenschaften untersucht und bewertet. Ein weiterer Schwerpunkt lag auf der Entwicklung und Optimierung der Opferschichtprozesse, sowie deren Integration in die Gesamttechnologie. Die Eignung der plasmagestützten Prozesse zur Abscheidung und Strukturierung des Opferpolymers wurde durch die Fertigung von verkapselten Beschleunigungssensoren nachgewiesen. Ein ausreichender hermetischer Verschluss der Dünnschichtkappe konnte durch die Messung der viskosen Dämpfung an Feder-Masse-Schwingern bestätigt werden.
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Thacker, Hiren Dilipkumar. "Probe Modules for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11597.
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The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future high-performance gigascale chip-based systems. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale chips having electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment. A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. In this work, two candidate probe modules were devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The first probe module consists of compliant electrical probes (10^3 probes/cm^2) fabricated alongside grating-in-waveguide optical probes. The second module consists of micro-opto-electro-mechanical-systems (MOEMS)-based microsocket probes (10^4 probes/cm^2) to interface a chip with polymer pillar-based electrical and optical I/Os. High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication are described and numerous possible redistribution schemes are explicated. Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.
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Fischer, Andreas C. "Integration and Fabrication Techniques for 3D Micro- and Nanodevices." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-107125.
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The development of micro and nano-electromechanical systems (MEMS and NEMS) with entirely new or improved functionalities is typically based on novel or improved designs, materials and fabrication methods. However, today’s micro- and nano-fabrication is restrained by manufacturing paradigms that have been established by the integrated circuit (IC) industry over the past few decades. The exclusive use of IC manufacturing technologies leads to limited material choices, limited design flexibility and consequently to sub-optimal MEMS and NEMS devices. The work presented in this thesis breaks new ground with a multitude of novel approaches for the integration of non-standard materials that enable the fabrication of 3D micro and nanoelectromechanical systems. The objective of this thesis is to highlight methods that make use of non-standard materials with superior characteristics or methods that use standard materials and fabrication techniques in a novel context. The overall goal is to propose suitable and cost-efficient fabrication and integration methods, which can easily be made available to the industry. The first part of the thesis deals with the integration of bulk wire materials. A novel approach for the integration of at least partly ferromagnetic bulk wire materials has been implemented for the fabrication of high aspect ratio through silicon vias. Standard wire bonding technology, a very mature back-end technology, has been adapted for yet another through silicon via fabrication method and applications including liquid and vacuum packaging as well as microactuators based on shape memory alloy wires. As this thesis reveals, wire bonding, as a versatile and highly efficient technology, can be utilized for applications far beyond traditional interconnections in electronics packaging. The second part presents two approaches for the 3D heterogeneous integration based on layer transfer. Highly efficient monocrystalline silicon/ germanium is integrated on wafer-level for the fabrication of uncooled thermal image sensors and monolayer-graphene is integrated on chip-level for the use in diaphragm-based pressure sensors. The last part introduces a novel additive fabrication method for layer-bylayer printing of 3D silicon micro- and nano-structures. This method combines existing technologies, including focused ion beam implantation and chemical vapor deposition of silicon, in order to establish a high-resolution fabrication process that is related to popular 3D printing techniques.<br><p>QC 20121207</p>
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Beix, Vincent. "Etudes des procédés d'encapsulation hermétique au niveau du substrat par la technologie de transfert de films." Phd thesis, Université Paris Sud - Paris XI, 2013. http://tel.archives-ouvertes.fr/tel-01037897.
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Les micro-dispositifs comportant des structures libérées et mobiles sont d'une part très sensibles aux variations de leur environnement de travail, et d'autre part très fragiles mécaniquement. L'étape de découpe du substrat en plusieurs puces est extrêmement agressive et peut entrainer la destruction totale des micro-dispositifs. L'encapsulation avant la découpe va alors prémunir les micro-composants lors de cette étape critique et continuer à garantir leur bon fonctionnement tout au long de leur utilisation en conservant la stabilité et la fiabilité de leur performance. Le conditionnement doit en outre interfacer les micro-dispositifs encapsulés avec le monde macroscopique en vue de leur utilisation. De nombreux procédés de fabrication ont déjà été développés pour l'élaboration d'un conditionnement. C'est le cas de l'encapsulation puce par puce, substrat - substrat, par couche sacrificielle par exemple. Ils sont toutefois très contraignants (encombrement, compatibilité, coût, ...). Nous avons étudié, au cours de cette thèse, un procédé innovant de conditionnement hermétique par transfert de film utilisant une couche à adhésion contrôlée. Cette technologie consiste à élaborer des capots protecteurs sur le substrat moule puis à les reporter collectivement pour encapsuler les micro-dispositifs. Ce procédé est totalement compatible avec un interfaçage électrique de composant qui traverse les cordons de scellement ou le capot. Ce procédé nécessite la maîtrise de la croissance de divers films (C, CxFy, Ni, AlN, parylène, BCB, Au-In) et permet d'obtenir des boitiers étanches, hermétiques et robustes qui devraient très rapidement pouvoir être utilisés pour le conditionnement de MEMS.
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Patel, Chirag Suryakant. "Compliant Wafer Level Package (CWLP)." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13518.
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Gatty, Hithesh K. "MEMS-based electrochemical gas sensors and wafer-level methods." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-172955.
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This thesis describes novel microel ectromechanical system (MEMS) based electrochemical gas sensors and methods of fabrication. This thesis presents the research in two parts. In the first part, a method to handle a thin silicon wafer using an electrochemically active adhesive is described. Handling of a thin silicon wafer is an important issue in 3D-IC manufacturing where through silicon vias (TSVs) is an enabling technology. Thin silicon wafers are flexible and fragile, therefore difficult to handle. In addressing the need for a reliable solution, a method based on an electrochemically active adhesive was developed. In this method, an electrochemically active adhesive was diluted and spin coated on a 100 mm diameter silicon wafer (carrier wafer) on which another silicon wafer (device wafer) was bonded. Device wafer was subjected to post processing fabrication technique such as wafer thinning. Successful debonding of the device wafer was achieved by applying a voltage between the two wafers. In another part of the research, a fabrication process for developing a functional nanoporous material using atomic layer deposition is presented. In order to realize a nanoporous electrode, a nanoporous anodized aluminum oxide (AAO) substrate was used, which was functionalized with very thin layers (~ 10 nm) of platinum (Pt) and aluminum oxide (Al2O3) using atomic layer deposition. Nanoporous material when used as an electrode delivers high sensitivity due to the inherent high surface area and is potentially applicable in fuel cells and in electrochemical sensing. The second part of the thesis addresses the need for a high performance gas sensor that is applicable for asthma monitoring. Asthma is a disease related to the inflammation in the airways of the lungs and is characterized by the presence of nitric oxide gas in the exhaled breath. The gas concentration of above approximately 50 parts-per-billion indicates a likely presence of asthma. A MEMS based electrochemical gas sensor was successfully designed and developed to meet the stringent requirements needed for asthma detection. Furthermore, to enable a hand held asthma measuring instrument, a miniaturized sensor with integrated electrodes and liquid electrolyte was developed. The electrodes were assembled at a wafer-level to demonstrate the feasibility towards a high volume fabrication of the gas sensors. In addition, the designed amperometric gas sensor was successfully tested for hydrogen sulphide concentration, which is a bio marker for bad breath.<br><p>QC 20150907</p>
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Monadgemi, Pezhman. "Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11473.
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This thesis reports on a new low-cost wafer-level packaging technology for microelectromechanical systems (MEMS). The MEMS process is based on a revised version of High Aspect Ratio Polysilicon and Single Crystal Silicon (HARPSS) technology. The packaging technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat followed by metal coating to create resizable MEMS packages. The sacrificial polymer is created on top of the active component including beams, seismic mass, and electrodes by photodefining, dispensing, etching, or molding. The low loss polymer overcoat is patterned by photodefinition to provide access to the bond pads. The sacrificial polymer decomposes at temperatures around 200-280aC and the volatile products permeate through the overcoat polymer leaving an embedded air-cavity. For MEMS devices that do not need hermetic packaging, the encapsulated device can then be handled and packaged like an integrated circuit. For devices that are sensitive to humidity or need vacuum environment, hermiticity is obtained by deposition and patterning thin-film metals such as aluminum, chromium, copper, or gold.
To demonstrate the potential of this technology, different types of capacitive MEMS devices have been designed, fabricated, packaged, and characterized. These includes beam resonators, RF tunable capacitors, accelerometers, and gyroscopes. The MEMS design includes mechanical, thermal, and electromagnetic analysis. The device performance, before and after packaging is compared and the correlation to the model is presented.
The following is a summary of the main contributions of this work to the extensive research focused on MEMS and their packaging:
1)A new low-cost wafer-level packaging method for bulk or surface micromachined devices including resonators, RF passives and mechanical sensors is reported. This technique utilizes thermal decomposition of a sacrificial polymer through an overcoat polymer to create buried channels on top of the resonant/movable parts of the micromachined device. It provides small interconnections together with resizable package dimensions. We report MEMS package thicknesses in the range of 10 mm to 1 mm, and package size from 0.0001 mm to 1 mm.
2)A revised version of the HARPSS technology is presented to implement high aspect ratio silicon capacitors, resonators and inertial sensors in the smallest area.
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Ok, Seong Joon. "High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/18227.
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Zhang, Rong. "Wafer level LED packaging with integrated DRIE trenches for encapsulation /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?MECH%202008%20ZHANGR.
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Comart, Ilker. "Zero-level Packaging Of Microwave And Millimeter-wave Mems Components." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612420/index.pdf.
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This thesis presents realization of two shunt, capacitive contact RF MEMS switches and two RF MEMS SPDT switches for microwave and millimeter-wave applications, two zero-level package structures for RF MEMS switches and development trials of a BCB based zero level packaging process cycle.
Two shunt, capacitive contact RF MEMS switches for 26 GHz and 12 GHz operating frequencies are designed, fabricated and consistencies between fabricated devices and designs are shown through RF measurements. For the switch design at 26 GHz and at the operating frequency, return loss in the upstate is measured to be 27.61 dB, insertion loss and isolation in the downstate is measured to be 0.21 dB and 27.16 dB, respectively. For the switch design at 12 GHz and at the operating frequency, return loss in the upstate is measured to be 38.69 dB, insertion loss and isolation in the downstate is measured to be 0.05 dB and 25.84 dB, respectively. Quite accurate circuit models have been obtained for both of the RF MEMS switches. Two RF MEMS SPDT switches, which utilize the shunt, capacitive contact switches as building blocks are designed through circuit simulations. These two designs are fabricated and their RF measurements have been completed. It is shown from circuit model simulations that, the performances of the fabricated devices and desired responses corresponded to each other. For the SPDT switch design at 26 GHz, return loss at the input port is measured to be 12 dB and insertion loss is measured to be 1.24 dB. For the SPDT switch design at 12 GHz, return loss at the input port is measured to be 5.6 dB and insertion loss is measured to be 0.49 dB. The reason behind the unexpectedly bad performances has been investigated and discovered. The bad performances were due to a common mistake in the layouts of both SPDT switches. These mistakes are corrected in the circuit models and expected performances are obtained.
Two different zero-level package structures which use high-resistive Si wafers have been suggested and required design changes have been made on the RF MEMS shunt, capacitive contact switches and SPDT switches in order to minimize the package effects. For this purpose polygonal CPW transitions have been designed and integrated into the designs, followed by the necessary tunings in the switch structures for which EM and circuit simulations are utilized.
For the suggested package structures to be produced, two possible process cycles have been studied. One of the process flows was based on KOH anisotropic Si etching and the other one was based on DRIE (Deep Reactive Ion Etching). Great progress has been achieved in the latter process cycle, however this process cycle still needs some more study and it could not be completed in the time required for this thesis study.
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Prabhakumar, Ananth. "System based material design for wafer level underfills :." Diss., Online access via UMI:, 2004.
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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Systems Science Dept., 2004<br>Only abstract available. "At the request of the author, this graduate work is not available for purchase." Includes bibliographical references.
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Lapisa, Martin. "Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-125913.
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This thesis describes the development of wafer-level fabrication and packaging methods for micro-electromechanical (MEMS) devices, based on wafer-bonding. The first part of the thesis is addressing the development of a wafer-level technology that allows the use of high performance materials, such as monocrystalline silicon, for MEMS devices that are closely integrated on top of sensitive integrated circuits substrates. Monocrystalline silicon has excellent mechanical properties that are hard to achieve otherwise, and therefore it fits well in devices for adaptive optics and maskwriting applications where nanometer precision deflection requirements call for mechanically stable materials. However, the temperature sensitivity of the integrated circuits prohibits the use of monocrystalline silicon with conventional deposition and surface micromachining techniques. Here, heterogeneous 3-D integration by adhesive wafer-bonding is used to fabricate three different types of spatial light modulators, based on micromirror arrays made of monocrystalline silicon; micromirror arrays with vertically moving “piston-type” mirrors and with tilting mirrors made of one functional monocrystalline silicon layer, and vertically moving hidden-hinge micromirror arrays made of two functional monocrystalline silicon layers. The second part of the thesis addresses the need for room-temperature packaging methods that allow the packaging of liquids or in general heat sensitive devices on wafer-level. A packaging method was developed that is based on a hybrid wafer-bonding approach, combining the compression bonding of gold gaskets with adhesive bonding. The packaging method is first demonstrated for the wafer-level encapsulation of liquids in reservoirs and then applied to packaging a dye-based photonic gas sensor.<br><p>QC 20130816</p>
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Rais-Zadeh, Mina. "Wafer-level encapsulated high-performance mems tunable passives and bandpass filters." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29626.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Farrokh Ayazi; Committee Member: James D. Meindl; Committee Member: Joy Laskar; Committee Member: Mark G. Allen; Committee Member: Paul A. Kohl. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Huan, Junjun. "Wafer-Level Vacuum-Encapsulated Ultra-Low Voltage Tuning Fork MEMS Resonator." University of Dayton / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493253273171541.
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Joung, Yeun-Ho. "Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04052004-180025/unrestricted/joung%5Fyeun-ho%5F200312%5Fphd.pdf.
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Deeds, Michael Andrew. "Qualification of metallized optical fiber connections for chip-level MEMS packaging." College Park, Md. : University of Maryland, 2004. http://hdl.handle.net/1903/1941.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2004.<br>Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Kay, Robert William. "Novel micro-engineered stencils for flip-chip bonding and wafer level packaging." Thesis, Heriot-Watt University, 2008. http://hdl.handle.net/10399/2193.
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Busch, Stephen Christopher. "Evaluation and process development of wafer-level-applied underfill material systems for flip chip assembly." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/18192.
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Oberhammer, Joachim. "Novel RF MEMS Switch and Packaging Concepts." Doctoral thesis, KTH, Signaler, sensorer och system, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3817.
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Radio-frequency microelectromechanical systems (RF~MEMS) are highly miniaturized devices intended to switch, modulate, filter or tune electrical signals from DC to microwave frequencies. The micromachining techniques used to fabricate these components are based on the standard clean-room manufacturing processes for high-volume integrated semiconductor circuits. RF~MEMS switches are characterized by their high isolation, low insertion loss, large bandwidth and by their unparalleled signal linearity. They are relatively simple to control, are very small and have almost zero power consumption. Despite these benefits, RF~MEMS switches are not yet seen in commercial products because of reliability issues, limits in signal power handling and questions in packaging and integration. Also, the actuation voltages are typically too high for electronics applications and require additional drive circuitry. This thesis presents a novel MEMS switch concept based on an S-shaped film actuator, which consists of a thin and flexible membrane rolling between a top and a bottom electrode. The special design makes it possible to have high RF isolation due to the large contact distance in the off-state, while maintaining low operation voltages due to the zipper-like movement of the electrostatic dual-actuator. The switch comprises two separately fabricated parts which allows simple integration even with RF circuits incompatible with certain MEMS fabrication processes. The two parts are assembled by chip or wafer bonding which results in an encapsulated, ready-to-dice package. The thesis discusses the concept of the switch and reports on the successful fabrication and evaluation of prototype devices. Furthermore, this thesis presents research results in wafer-level packaging of (RF) MEMS devices by full-wafer bonding with an adhesive intermediate layer, which is structured before bonding to create defined cavities for housing MEMS devices. This technique has the advantage of simple, robust and low temperature fabrication, and is highly tolerant to surface non-uniformities and particles in the bonding interface. It allows cavities with a height of up to many tens of micrometers to be created directly in the bonding interface. In contrast to conventional wafer-level packaging methods with individual chip-capping, the encapsulation is done using a single wafer-bonding step. The thesis investigates the process parameters for patterned adhesive wafer bonding with benzocyclobutene, describes the fabrication of glass lid packages based on this technique, and introduces a method to create through-wafer electrical interconnections in glass substrates by a two-step etch technique, involving powder-blasting and chemical etching. Also, it discusses a technique of improving the hermetic properties of adhesive bonded structures by additional passivation layers. Finally, it presents a method to substantially improve the bond strength of patterned adhesive bonding by using the solid/liquid phase combination of a patterned polymer layer with a contact-printed thin adhesive film.<br>QC 20100617
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Le, Neal Jean-François. "Impact du packaging sur le comportement d'un capteur de pression piézorésistif pour application aéronautique." Thesis, Toulouse, INSA, 2011. http://www.theses.fr/2011ISAT0035.
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La protection de nombreux capteurs de pression en milieux hostiles se résume souvent en un boitier métallique hermétique rempli d’huile enveloppant la puce. La pression agit alors sur une membrane métallique qui agit sur la puce par l’intermédiaire de l’huile jugée incompressible. Cette encapsulation présente des difficultés de réalisation non négligeables et surtout une limitation des capteurs en température. Les travaux réalisés au cours de cette thèse concernent une encapsulation au niveau wafer du capteur de pression. L’idée principale est d’intégrer la protection de la puce dans le processus de fabrication sur wafer. L’intérêt est alors d’obtenir une protection réalisée de manière collective, réduisant ainsi drastiquement les coûts de production. De plus, une encapsulation au niveau wafer offre la possibilité de réduire considérablement les dimensions du capteur tout en le gardant résistant. La suppression d’éléments intermédiaires telle que l’huile entre la pression et la puce en elle même permet enfin d’espérer des applications possibles à température plus élevée. Une fois l’encapsulation réalisée au niveau wafer, il est nécessaire de réaliser le packaging de premier niveau. Le packaging de premier niveau offre un support à la puce, ce qui la rend manipulable et testable, tant par ses dimensions que par la présence de connexions électriques. L’assemblage au niveau wafer et de premier niveau constituent donc les deux niveaux de packaging qui peuvent avoir une influence directe sur le comportement de la puce.Au niveau de l’encapsulation de niveau wafer, trois techniques d’assemblage (wafer bonding) ont été analysées : le scellement anodique, le scellement eutectique et le scellement direct. Le scellement anodique est la technique la plus éprouvée pour assembler un wafer de verre sur un wafer de silicium. Le scellement eutectique représente une technique moins commune mais offrant l’intérêt d’utiliser deux wafers silicium, limitant la différence de dilatation thermique entre les deux wafers et permettant d’usiner plus facilement le wafer d’encapsulation. Enfin la technique du direct bonding donne l’opportunité d’éviter d’utiliser une couche intermédiaire métallique entre les deux wafers, à condition d’avoir deux surfaces à assembler très propres et de très bonne qualité. La technique de soudure anodique a permis de livrer les capteurs qui ont pu confirmer l’intérêt des capteurs WLP pour des applications hautes températures. Les techniques silicium-silicium ont été évaluées mais n’ont pas donné lieu à des capteurs WLP testables.Au niveau de l’encapsulation de niveau un, la technique de Flip-Chip à été utilisée pour reporter la puce sur son support. Cette technique consiste à retourner la puce et l’assembler par thermocompression. Les plots de connexions de la puce pour cet assemblage ont pu être réalisés par ball bumping. Des cycles en température (-55°C à +125°C ou 150°C) ont pu être réalisés sur les puces scellées par scellement anodique. L’erreur totale en précision de ces capteurs WLP est du même ordre que les capteurs Auxitrol actuels avec une compensation numérique. Le principal atout des capteurs WLP est une non-linéarité de l’offset en température divisée par deux. Cette caractéristique est importante dans le cas où l’on utilise une compensation analogique qui peut résister à des températures plus élevées que la compensation numérique. Les capteurs WLP offre donc l’opportunité d’avoir des applications au-delà de 200°C, chose alors jusqu’alors prohibée par l’utilisation de l’huile<br>Protection of most of the pressure sensors working in harsh environment consist in oil filled metallic unit including the sensor die. In that case, pressure is applied on a metallic membrane moving the silicon membrane of the die across an incompressible fluid. The main drawbacks of the standard encapsulation are a complex fabrication process and most of all a sensor limitation in high temperatures. The topic of this PhD thesis is about wafer-level packaging (WLP) of the pressure sensor. The main idea is to integrate the die protection in the fabrication process at wafer level. Advantage is to obtain a collective protection fabrication reducing production costs. Moreover, a wafer-level encapsulation allows a possible reduction of sensor dimensions keeping it reliable. Removing intermediary elements allows also high temperature applications. Once encapsulation realised on the wafer, it is necessary to build the first-level packaging. First-level packaging makes the die usable in terms of electrical connection and dimensions. Wafer and first-levels are both packaging levels with important impact on the die behaviour.At wafer-level packaging, three wafer bonding technologies have been investigated: anodic bonding, Au-Si eutectic bonding and direct bonding. Anodic bonding is the most known technology to assemble a glass wafer with a silicon wafer. Eutectic bonding represents a promising technique to bond two silicon wafers allowing less CTE mismatch between wafers material and an easier micromachining of silicon instead of glass material. Direct bonding is also interesting to bond two silicon wafers, without using intermediary metallic layer but needing really clean surfaces to assemble. Anodic bonding process gave us the opportunity to deliver WLP sensors showing interest for high temperature applications. Silicon-Silicon technologies have been evaluated but did not give representative WLP sensors.At first-level packaging, the Flip-chip technology have been used for die attach. This technique consists in flipping the die and making the die attach by thermocompression with stud bumps on the die connection pads.Temperature cycling (-55°C to +125°C or more) have been realised on anodic WLP sensors. Accuracy total error of these WLP sensors is in the same order than standard Auxitrol sensors with digital compensation. the main advantage of the WLP sensors is a offset non-linearity in temperature divided by two. This characteristic is important in the case of analogical compensation that can resist to higher temperatures than digital compensation elements. In definitive, WLP sensors offer a good opportunity to have application over 200°C, prohibited at present with the presence of oil for standard Auxitrol sensor
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McCrone, Tim M. "The Creation of an Anodic Bonding Device Setup and Characterization of the Bond Interface Through the use of the Plaza Test." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/695.
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Recently there has been an increased focus on the use of microfluidics for the synthesis of different products. One of the products proposed for synthesis is quantum dots. Microfluidics often uses Polydimethylsiloxane for structure in microfluidic chips, but quantum dots use octadecene in several synthesis steps. The purpose of this work was to create a lab setup capable of anodically bonding 4” diameter wafers, and to characterize the bond formed using the Plaza test chip so that microfluidic devices using glass and silicon as substrates could be created.
Two stainless steel electrodes placed on top of a hot plate were attached to a high power voltage supply to perform anodic bonding. A Plaza test mask was created and used to pattern P type silicon wafers. The channels etched were between 300 and 500nm deep and ranged between 1000µm and 50µm. These wafers were then anodically bonded to Corning 7740 glass wafers. Bonding stopped once the entire surface of the wafer was bonded, determined by visual inspection. All bonds were formed at 400°C and the bond strength and toughness between wafers bonded at 400V and 700V was compared.
A beam model was used to predict the interfacial fracture toughness, and the stress at the bond was calculated with a parallel spring model. By measuring the crack length of the test structures under a light microscope the load conditions of the beam could be found. It was concluded that the electrostatic forces between the wafers give the best indication of what the bond quality will be. This was seen by the large difference in crack length between samples that were bonded using a thick glass wafer (1 mm) and a thin glass wafer (500µm). The observed crack lengths for the thick glass wafers were between 40 and 60µm. Thin glass wafers had a crack length between 20 and 40µm. The fracture toughness was calculated using the beam model approximation. Fracture toughness of the thin glass wafers was 7MPa m1/2, and of the thick glass wafers was 30 MPa m1/2. The fracture toughness of the thick glass wafers agreed with results found through the use of the double cantilever beam samples in literature. The maximum observed interfacial stress was 70 MPa.
Finally, to measure the change in the size of the sodium depletion zone formed during bonding, samples were placed under a scanning electron microscope (SEM). Depletion zones were found to be between 1.1 and 1.4µm for thin glass samples that were bonded at 400 and 700 volts. This difference was not found to have a significant effect on the strength or fracture toughness observed. Thicker glass samples could not have their depletion zone measured due to SEM chuck size.
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Kim, Woopoung. "Development of Measurement-based Time-domain Models and its Application to Wafer Level Packaging." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5012.
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In today's semiconductor-based computer and communication technology, system performance is determined primarily by two factors, namely on-chip and off-chip operating frequency. In this dissertation, time-domain measurement-based methods that enable gigabit data transmission in both the IC and package have been proposed using Time-Domain Reflectometry (TDR) equipment. For the evaluation of the time-domain measurement-based method, a wafer level package test vehicle was designed, fabricated and characterized using the proposed measurement-based methods. Electrical issues associated with gigabit data transmission using the wafer-level package test vehicle were investigated. The test vehicle consisted of two board transmission lines, one silicon transmission line, and solder bumps with 50um diameter and 100um pitch. In this dissertation, 1) the frequency-dependent characteristic impedance and propagation constant of the transmission lines were extracted from TDR measurements. 2) Non-physical RLGC models for transmission lines were developed from the transient behavior for the simulation of the extracted characteristic impedance and propagation constant. 3) the solder bumps with 50um diameter and 100um pitch were analytically modeled. Then, the effect of the assembled wafer-level package, silicon substrate and board material, and material interfaces on gigabit data transmission were discussed using the wafer-level package test vehicle. Finally, design recommendations for the wafer-level package on integrated board were proposed for gigabit data transmission in both the IC and package.
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Bouchoucha, Mohamed. "Remplissage en polymère des via traversant (TSV) pour des applications 3D-Wafer Level Packaging." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4373/document.
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Les technologies d'empilement vertical de circuits intégrés, plus connues sous le terme « intégration 3D », ont connu un développement important durant les six dernières années, dans l'optique de proposer une alternative aux approches bidimensionnelles traditionnelles comme les Systems on Chip (SoC). Cette nouvelle architecture a été adaptée au domaine du packaging des circuits intégrés à travers le packaging en 3D réalisé à l'échelle de la plaque ou 3D-WLP pour 3D-Wafer Level Packaging. L'intégration 3D-WLP permet une diminution des tailles des dispositifs finaux, une augmentation de la densité des interconnexions ainsi qu'une réduction des coûts de fabrication. La maîtrise de la réalisation des via traversant, ou TSV pour Through Silicon Via, est une étape clé qui permet d'assurer une connexion électrique entre les différents niveaux empilés. On s'intéresse dans ces travaux de thèse au TSV dans son approche via-last, c'est-à-dire fabriqué en face arrière du dispositif, après les transistors et les niveaux de métallisation de la face avant, et plus particulièrement à l'étape de passivation organique des TSV. En effet, ce via traversant est d'un diamètre trop important pour être complètement rempli avec sa métallisation en cuivre. L'étude concerne donc une solution incluant un remplissage en polymère afin d'améliorer la solution existante en termes de fiabilité et de compatibilité avec des empilements verticaux supplémentaires<br>3D integration technologies for integrated circuits have been widely developed during the six last years in order to propose an alternative to bi-dimensional approaches such as the Systems on Chip (SoC). This new architecture is also used for integrated circuits packaging through 3D-Wafer Level Packaging (3D-WLP). Thus, vertical stacking allows smaller package footprint, higher interconnection density and lower fabrication costs. Through silicon via (TSV) is a key technology that insures vertical electrical interconnection between the stacked levels. This thesis deals with the via-last approach which consists in realizing the TSV at the back-side of the wafer, after the Front End Of the Line (FEOL) and the Back End Of the Line (BEOL), both located at the front-side. During the metallization steps, only a copper liner is electroplated in the TSV since its diameter is too large to achieve a complete metal filling. This study focuses on the TSV polymer insulation step and more specifically, a solution including a TSV polymer filling in order to improve the existing configuration in terms of reliability and compatibility with further 3D stacking
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Zhang, Zhuqing. "Study on the curing process of no-flow and wafer level underfill for flip-chip applications." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180247/unrestricted/zhang%5Fzhuqing%5F200312%5Fphd.pdf.
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Kelleher, Hollie Anne. "Air-Gaps via Thermally Decomposable Polymers and Their Application to Compliant Wafer Level Packaging (CWLP)." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6987.
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A method was proposed for the fabrication of air-gaps embedded in dielectric layers using thermally decomposable sacrificial polymers. The research had two main objectives: (1) the development and characterization of air-gap fabrication for use in a wide spectrum of applications; and (2) the integration of air-gaps into a specific application: air-gaps in an integrated circuit compliant wafer level packaging technology, Sea of Leads.
Polynorbornene and polycarbonate sacrificial materials were used to form air-gaps at temperatures of 200, 300, and 400oC. Fabrication results of air-gaps encapsulated by both inorganic and organic dielectric materials indicated that the thermal and mechanical properties of the dielectric materials at the decomposition temperature of the sacrificial material resulted in success or failure of the process. Multi-layered encapsulating materials enabled the use of a dielectric material which does not successfully form air-gaps on its own.
Thermal decomposition of the sacrificial materials with alteration in the polymer chemistry was studied. Polynorbornene containing 90 mol% butyl and 10 mol% triethoxysilyl side groups was selected as an optimum 400oC decomposition temperature material. The decomposition of this polynobornene composition in an open nitrogen atmosphere was contrasted to decomposition of the polynorbornene while completely encapsulated in a dielectric material. Thermogravimetric analysis and examination of residual surfaces following the decomposition, combined with comparison of the overall kinetic parameters of the decomposition reaction, indicated differences in the two overall processes.
The design concept of Sea of Leads three-dimensionally compliant packaging technology with embedded air-gaps is presented. The critical issues resulting from the addition of air-gaps into the process are the compatibility of materials, lithography on topographical features, and yield and uniformity. Factors influencing the z-axis mechanical performance of the air-gap were determined to be the air-gap shape and size, the encapsulating material dielectric properties and thickness, and the decomposition conditions. Model calculations combined with the known limitations of fabrication provided a design space for maximum out-of-plane mechanical movement and compliance of the air-gaps. The results demonstrated that the incorporation of an embedded air-gap in Sea of Leads technology can achieve the necessary z-axis compliance goals for future applications.
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Oba, Masatoshi. "STUDIES ON THE FABRICATION OF VERTICAL INTEGRATED MEMS DEVICES." 京都大学 (Kyoto University), 2010. http://hdl.handle.net/2433/126817.
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Uppalapati, Balaadithya. "Design and Analysis of Wafer-Level Vacuum-Encapsulated Disk Resonator Gyroscope Using a Commercial MEMS Process." University of Dayton / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1510764485530995.
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Veyrié, David. "Approche alternative de l'évaluation de l'herméticité des micro cavités : application au packaging des MEMS." Bordeaux 1, 2007. http://www.theses.fr/2007BOR13348.
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Les MEMS, qui comportent des structures libérées et mobiles, sont particulièrement sensibles aux variations de leur environnement de travail. L'herméticité du packaging et la détection des phénomènes de fuites sont donc des points clés pour la fiabilité de ces composants. Or, avec l'apparition des techniques d'encapsulation niveau wafer et la miniaturisation des boîtiers, l'herméticité est de plus en plus difficile à contrôler. Les techniques de détection de fuite utilisées classiquement pour les composants électroniques ne sont plus applicables. Les travaux réalisés dans le cadre de cette thèse visent à améliorer l'approche actuelle de ces problèmes de test et d'évaluation de l'herméticité des micro boîtiers utilisés pour l'encapsulation des MEMS. Pour y parvenir, nous nous sommes efforcés dans un premier temps de mieux comprendre les phénomènes de fuite mis en jeu pour ce type de micro boîtiers. Il a ensuite été possible de développer des moyens plus adaptés pour évaluer le degré d'herméticité des micro boîtiers MEMS, à la fois d'un point de vue théorique en modélisant la diffusion du gaz à travers les colles organiques, et d'un point de vue expérimental en développant une technique alternative de détection de fuite par spectroscopie infrarouge pour les micro boîtiers silicium
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Alt, Marie Theresa [Verfasser]. "Glass on Silicon for Thick Waveguides and Hermetic Miniaturized Laser Diode Packaging on Wafer-Level / Marie Theresa Alt." München : Verlag Dr. Hut, 2021. http://d-nb.info/1232848115/34.
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Shaporin, Alexey. "Dynamic parameter identification techniques and test structures for microsystems characterization on wafer level." Doctoral thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200901902.
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In der vorliegenden Arbeit wird eine Methode zur Charakterisierung von Mikrosystemen mit beweglichen Komponenten dargestellt. Sie erlaubt, funktionsrelevante Parameter und deren Schwankungen produktionsbegleitend auf Waferlevel zu ermitteln. Dabei wird vorausgesetzt, dass die Sollform der Struktur und die Abweichungsarten bekannt sind. Die Methode beruht auf dem Vergleich von numerisch berechneten mit experimentell ermittelten Eigenfrequenzen der untersuchten Mikrosysteme. Dazu wird die Abhängigkeit verschiedener Eigenfrequenzen von den gesuchten Parametern mittels einer Parametervariationsanalyse berechnet und durch eine geeignete Funktion angenähert. Die Messung der dynamischen Eigenschaften erfolgt mit Hilfe eines Bewegungsanalysators, der auf einem Laser-Doppler-Vibrometer basiert. Im letzen Schritt werden die gesuchten Parameter berechnet. Kernpunkt der entwickelten Methode sind Messungen auf der Basis von speziellen Teststrukturen, die im Waferlayout neben den eigentlichen Nutzstrukturen platziert sind und parallel mit den Nutzstrukturen prozessiert werden. Es werden Algorithmen zur Generierung des Designs der Teststrukturen und ihrer Platzierung im Waferlayout entwickelt. Dabei werden das Design der Nutzstruktur und deren funktionsrelevante Parameter, der technologische Ablauf und materialspezifische Kennwerte berücksichtigt. Im Ergebnis liegt eine Bibliothek von Standard-Teststrukturen vor, die für produktionsbegleitende Messungen sowie für die Übertragbarkeit der Ergebnisse geeignet sind. Außerdem werden allgemeingültige Richtlinien zur Durchführung der Messungen an den Standard-Teststrukturen abgeleitet. Das Messverfahren wurde an unterschiedlichen Mikrosystemen mit beweglichen Komponenten überprüft und zu einer allgemeinen Messmethode für diese Klasse von Mikrosystemen erweitert<br>In this work a method for the characterization of microsystems with movable components is presented. The method allows to determine the relevant parameters and their variations on wafer level if the nominal shape of the structure and the type of deviations are known. The method is based on a comparison of the numerically calculated and experimentally measured Eigenfrequencies of the microsystems. For that purpose, the relationships between various Eigenfrequencies and the searched parameters are calculated by parameter variation analysis and the results of this analysis are approximated with appropriate functions. A Laser Doppler vibrometer based motion analyzer is used to determine the frequency response function of the micromechanical structure and extract Eigenfrequencies. The comparison of the measured and the calculated frequencies provides values for the searched parameters. The key element of the developed method is the measurement on special test structures that are placed in the wafer layout next to the actual microsystems and processed in the same technological process parallel to the actual microsystems. Algorithms for designing the test structures and their placement in the wafer layout are shown, taking into account the design of the actual microsystems and the function parameters of the technological process as well as material characteristics. As a result, a library of standard test structures for function relevant parameters is available. A general guideline for the measurement on the test structures is presented. The presented method is verified on various microsystems and extended to a whole class of microsystems with movable components
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Al, attar Sari. "Conception et mise au point d'un procédé d'assemblage (Packaging) 3D ultra-compact de puces silicium amincies, empilées et interconnectées par des via électriques traversant latéralement les résines polymères d'enrobage." Thesis, Toulouse, INSA, 2012. http://www.theses.fr/2012ISAT0008/document.
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Ce travail de thèse vise la définition et la mise au point de technologies pour l'empilement depuces microélectroniques dans un polymère et connectées électriquement par des viastraversants. Il explore deux voies : l’une de caractère industriel, utilisant une résine époxychargée en billes de silice E2517, l'autre, plus exploratoire, est basée sur l'utilisation de laSU8.Nous avons travaillé sur la mise au point des différentes étapes permettant d'empiler 4niveaux de puces amincies à 80 microns (enrobées) et empilées sur des épaisseurs de l'ordredu millimètre. Le problème du perçage des vias a été abordé et étudié à travers la mise aupoint de procédés d'usinage au laser des résines de type industriel. La métallisation encouches minces de ces trous de facteur de forme élevée (20) a été menée de sorte à atteindredes valeurs de résistance d'accès les plus faibles possibles.Un comparatif des deux voies utilisant la SU8 et la résine E2517 a été effectué et ses résultatscommentés en termes de faisabilité techniques et ses projections dans le domaine industriel.Des tests de fiabilité thermomécaniques ont été menés de concert avec une modélisation paréléments fini afin de valider les résultats des expérimentations réalisées dans le cadre de cetteétude<br>The subject of this thesis is the definition and development of TPV (Through Polymer Via)technology to stacking chips. The principal objective is to increase the potentialities of thevertical staking (complex IC; multiple I/O...) of Si chips without loss of performance or yield.The technique used consists to surround the IC chips by using particular resin and to fill (withmetallic films) the vertical holes drilled in this material. It explores two ways: one of anindustrial character, using an epoxy resin filled with silica beads E2517, other, moreexploratory, is based on the use of SU8.We worked on the development of different stages to stack four levels of chips thinned to 80microns (coated) and stacked on the thickness of one millimeter. The problem of drilling viashas been discussed and studied through the development of laser drilling processes ofindustrial resins. The thin-film metallization of the holes of high aspect ratio (20) wasconducted in order to reach values of access resistance as low as possible.A comparison of the two channels using SU8 resin and E2517 was carried out and the resultsdiscussed in terms of technical feasibility and its projections in the industrial field.Thermomechanical reliability tests were conducted in conjuction with finite element modelingto validate the results of experiments conducted in this study
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Specht, Hendrik. "MEMS-Laser-Display-System." Doctoral thesis, Universitätsbibliothek Chemnitz, 2011. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-71334.
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In der vorliegenden Arbeit werden die im Zusammenhang mit der Strahlablenkung stehenden Systemaspekte der auf MEMS-Scanner basierenden Laser-Display-Technologie theoretisch analysiert und aus den Ergebnissen die praktische Implementierung eines Laser-Display-Systems als Testplattform vorgenommen. Dabei werden mit einem Ansatz auf Basis zweier 1D-Scanner und einem weiteren Ansatz mit einem 2D-Scanner zwei Varianten realisiert. Darüber hinaus erfolgt die Entwicklung eines bildbasierten Multiparametertestverfahrens, welches sowohl für den Test komplettierter Strahlablenkeinheiten bzw. Projektionsmodule als auch zum umfassenden und zeiteffizienten Test von MEMS-Scannern auf Wafer-Level geeignet ist. Mit diesem Verfahren erfolgt eine Charakterisierung der zwei realisierten Varianten des Laser-Displays.
Ausgehend von den Eigenschaften des menschlichen visuellen Systems und den daraus resultierenden Anforderungen an das Bild sowie einer systemtheoretischen Betrachtung des mechanischen Verhaltens von MEMS-Scannern bildet die Ansteuersignalerzeugung für den resonanten Betrieb der schnellen und den quasistatischen Betrieb der langsamen Achse einen Schwerpunkt. Neben dem reinen digitalen Regler- bzw. Filterentwurf sowie mehreren Linearisierungsmaßnahmen beinhaltet dieser auch die Herleitung einer FPGA-basierten Videosignalverarbeitung zur Konvertierung von Scannpattern, Zeitregime und Auflösung mit einer entsprechenden Synchronisierung von Strahlablenkung und Lasermodulation. Auf Grundlage der daraus resultierenden Erkenntnisse über den Zusammenhang zwischen Scanner-/Systemparametern und Bildparametern werden Testbild-Bildverarbeitungsalgorithmus-Kombinationen entwickelt und diese, angeordnet in einer Sequenz, mit einem Kalibrierverfahren zu einem Testverfahren für MEMS-Scanner vervollständigt.
Die Ergebnisse dieser Arbeit entstanden im Rahmen von industriell beauftragten F&E-Projekten und fließen in die andauernde Fortführung des Themas beim Auftraggeber ein.
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Shaporin, Alexey. "Dynamic parameter identification techniques and test structures for microsystems characterization on wafer level." Doctoral thesis, Chemnitz Univ.-Verl, 2009. http://d-nb.info/1000815250/04.
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Kacker, Karan. "Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26464.
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Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Dr. Suresh K. Sitaraman; Committee Member: Dr. F. Levent Degertekin; Committee Member: Dr. Ioannis Papapolymerou; Committee Member: Dr. Madhavan Swaminathan; Committee Member: Dr. Nazanin Bassiri-Gharb. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Calayir, Enes. "Heterogeneous Integration of AlN MEMS Contour-Mode Resonators and CMOS Circuits." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1084.
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The increasing demand for high performance and miniature high frequency electronics has motivated the development of Micro-electro Mechanical Systems (MEMS) resonators, some of which have already become a commercial success for the making of filters, duplexers and oscillators used in radio frequency (RF) front-end systems for portable electronic devices. These MEMS components not only enable size, power and cost reduction with respect to their existing counterparts, but also open exciting opportunities for implementing new functionalities when used in large arrays. Almost all MEMS resonators require interfacing with one or more Complementary Metal Oxide Semiconductor (CMOS) integrated circuit components or modules in processing raw signals from individual MEMS devices. Hence, these devices should be integrated with CMOS circuits in an efficient and robust way in order to facilitate their deployment in large arrays with minimal parasitics, delay and power losses due to signal routing and CMOS-MEMS interconnects. Among the MEMS resonators developed to date, Aluminum Nitride (AlN) MEMS Contour-Mode Resonators (CMRs) offer high electro-mechanical coupling coefficient (𝑘𝑡2) and quality factor (Q), and a center frequency (f0) that can be set lithographically by varying the device in-plane dimensions. Also, AlN MEMS CMRs can be fabricated using state-of-the-art CMOS processes and micromachining techniques. These properties allow the synthesis of multi-frequency band-pass filters (BPFs) on a single chip with a low insertion loss and the capability of direct matching to 50 Ω systems. All these advantages, along with a sufficiently mature fabrication process, make AlN CMRs one of the ideal candidates for pursuing their integration with CMOS technology and implement high performance filters with programming capability. In this work we develop for the first time a three-dimensional (3D) heterogeneously integrated AlN MEMS-CMOS platform that enables the realization of such systems as self- healing filters for RF front-ends and programmable filter arrays for cognitive radios. We collaborated with the A*STAR, Institute of Microelectronics (IME), Singapore in the development of AlN MEMS platform on an 8" silicon (Si) wafer; on the other hand, CMOS chips were fabricated in 65 nm International Business Machines Corporation (IBM) and 28 nm Samsung processes. Solder bumps were placed on CMOS chips by Tag and Label Manufacturers Institute (TLMI) under the supervision of Metal Oxide Semiconductor Implementation Service (MOSIS). We demonstrated 3D integrated chip stacks with primary RF signal routing on MEMS and on CMOS for self-healing filters, and showcased the other system via wire-bonding to off-the-shelf CMOS components on a printed circuit board (PCB) because of the inability to continue to have access to the CMOS wafers and bumping processes over the last two years of the project.
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Specht, Hendrik. "MEMS-Laser-Display-System: Analyse, Implementierung und Testverfahrenentwicklung." Doctoral thesis, Universitätsverlag der Technischen Universität Chemnitz, 2010. https://monarch.qucosa.de/id/qucosa%3A19558.
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In der vorliegenden Arbeit werden die im Zusammenhang mit der Strahlablenkung stehenden Systemaspekte der auf MEMS-Scanner basierenden Laser-Display-Technologie theoretisch analysiert und aus den Ergebnissen die praktische Implementierung eines Laser-Display-Systems als Testplattform vorgenommen. Dabei werden mit einem Ansatz auf Basis zweier 1D-Scanner und einem weiteren Ansatz mit einem 2D-Scanner zwei Varianten realisiert. Darüber hinaus erfolgt die Entwicklung eines bildbasierten Multiparametertestverfahrens, welches sowohl für den Test komplettierter Strahlablenkeinheiten bzw. Projektionsmodule als auch zum umfassenden und zeiteffizienten Test von MEMS-Scannern auf Wafer-Level geeignet ist. Mit diesem Verfahren erfolgt eine Charakterisierung der zwei realisierten Varianten des Laser-Displays.
Ausgehend von den Eigenschaften des menschlichen visuellen Systems und den daraus resultierenden Anforderungen an das Bild sowie einer systemtheoretischen Betrachtung des mechanischen Verhaltens von MEMS-Scannern bildet die Ansteuersignalerzeugung für den resonanten Betrieb der schnellen und den quasistatischen Betrieb der langsamen Achse einen Schwerpunkt. Neben dem reinen digitalen Regler- bzw. Filterentwurf sowie mehreren Linearisierungsmaßnahmen beinhaltet dieser auch die Herleitung einer FPGA-basierten Videosignalverarbeitung zur Konvertierung von Scannpattern, Zeitregime und Auflösung mit einer entsprechenden Synchronisierung von Strahlablenkung und Lasermodulation. Auf Grundlage der daraus resultierenden Erkenntnisse über den Zusammenhang zwischen Scanner-/Systemparametern und Bildparametern werden Testbild-Bildverarbeitungsalgorithmus-Kombinationen entwickelt und diese, angeordnet in einer Sequenz, mit einem Kalibrierverfahren zu einem Testverfahren für MEMS-Scanner vervollständigt.
Die Ergebnisse dieser Arbeit entstanden im Rahmen von industriell beauftragten F&E-Projekten und fließen in die andauernde Fortführung des Themas beim Auftraggeber ein.
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Bleiker, Simon J. "Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-207185.
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Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.<br>Tredimensionell (3D) integration av mikro- och nano-elektromekaniska system (MEMS/NEMS) med integrerade kretsar (ICs) är en ny teknik som erbjuder stora fördelar jämfört med konventionell mikroelektronik. MEMS och NEMS används oftast som sensorer och aktuatorer då de möjliggör många funktioner som inte kan uppnås med vanliga ICs.3D-integration av NEMS och ICs bidrar även till mindre dimensioner, ökade prestanda och mindre energiförbrukning av elektriska komponenter. Den nuvarande tekniken för complementary metal-oxide-semicondictor (CMOS) närmar sig de fundamentala gränserna vilket drastiskt begränsar utvecklingsmöjligheten för mikroelektronik och medför slutet på Moores lag. Därför har 3D-integration identifierats som en lovande teknik för att kunna driva vidare utvecklingen för framtidens elektriska komponenter.I denna avhandling framläggs en omfattande fabrikationsmetodik för heterogen 3D-integration av NEMS ovanpå CMOS-kretsar. Heterogen integration betyder att både NEMS- och CMOS-komponenter byggs på separata substrat för att sedan förenas på ett enda substrat. Denna teknik tillåter full processfrihet för tillverkning av NEMS-komponenter och garanterar kompatibilitet med standardiserade CMOS-fabrikationsprocesser.I den första delen av avhandlingen beskrivs en metod för att sammanfoga två halvledarskivor med en extremt tunn adhesiv polymer. Denna metod demonstreras för 3D-integration av NEMS- och CMOS-komponenter. Den andra delen introducerar ett nytt koncept för NEM-switchar och dess användning i NEM-switch-baserade mikrodatorchip. Den tredje delen presenterar två olika inkapslingsmetoder för MEMS och NEMS. Den ena metoden fokuserar på hermetisk vakuuminkapsling medan den andra metoden beskriver en lågkostnadsstrategi för inkapsling av optiska komponenter. Slutligen i den fjärde delen presenteras en ny fabrikationsteknik för så kallade ”through silicon vias” (TSVs) baserad på magnetisk självmontering av nickeltråd på mikrometerskala.<br><p>20170519</p>
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Letowski, Bastien. "Intégration technologique alternative pour l'élaboration de modules électroniques de puissance." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT114.
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Les performances, l’encombrement, l’efficacité et la fiabilité des dispositifs sont parmi les enjeux majeurs de l’électronique de puissance. Ils se traduisent sur la conception, la fabrication et le packaging des semiconducteurs. Aujourd’hui, le packaging 3D apporte des réponses concrètes à ces problématiques en regard de l’approche standard (2D). Malgré les excellentes propriétés de ces modules 3D au niveau de la réduction de la signature CEM et du refroidissement, la réalisation, notamment les interconnexions, est complexe. Une approche globale prenant en compte un maximum de paramètres a été développée dans cette thèse. L’ensemble de ce travail s’appuie sur deux propositions que sont la conception couplée entre les composants et le packaging ainsi qu’une fabrication collective à l’échelle de la plaque des modules de puissance. Elles se combinent par la mise en place d’une filière d’étapes technologiques appuyée sur une boite à outils de procédés génériques. Cette approche est concrétisée par la réalisation d’un module de puissance 3D performant et robuste adressant des convertisseurs polyphasés avec des gains aussi bien sur les procédés de fabrication que le module lui-même ainsi que sur le système final.Ce travail offre une nouvelle vision alternative pour l’élaboration des modules électroniques de puissance. Il ouvre également des opportunités pour une fabrication et un packaging plus performants pour les nouveaux semiconducteurs grand gap<br>Performances, efficiency and reliability are among the main issues in power electronics. Nowadays, 3D packaging solutions increase standard planar module (2D) performances, for instance EMC. However such integrations are based on complex manufacturing, especially concerning interconnections. Improvements require global and advanced solutions. This work depends on two proposed concepts: a coupled design of the power devices and their associated package and a collective wafer-level process fabrication. A technological offer is proposed based on an innovative power packaging toolbox. Our approach is materialized by the fabrication of a 3D polyphase power module which proved to be more efficient and reliable. The benefits are more precise process manufacturing, lower EMI generation and lower inductive interconnections.As a matter of fact, this work offers a new and advanced technological integration for future power electronics modules, perfectly suitable for the wide bandgap semiconductors
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Gradin, Henrik. "Heterogeneous Integration of Shape Memory Alloysfor High-Performance Microvalves." Doctoral thesis, KTH, Mikrosystemteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-94088.
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This thesis presents methods for fabricating MicroElectroMechanical System (MEMS) actuators and high-flow gas microvalves using wafer-level integration of Shape Memory Alloys (SMAs) in the form of wires and sheets. The work output per volume of SMA actuators exceeds that of other microactuation mechanisms, such as electrostatic, magnetic and piezoelectric actuation, by more than an order of magnitude, making SMA actuators highly promising for applications requiring high forces and large displacements. The use of SMAs in MEMS has so far been limited, partially due to a lack of cost efficient and reliable wafer-level integration approaches. This thesis presents new methods for wafer-level integration of nickel-titanium SMA sheets and wires. For SMA sheets, a technique for the integration of patterned SMA sheets to silicon wafers using gold-silicon eutectic bonding is demonstrated. A method for selective release of gold-silicon eutectically bonded microstructures by localized electrochemical etching, is also presented. For SMA wires, alignment and placement of NiTi wires is demonstrated forboth a manual approach, using specially built wire frame tools, and a semiautomatic approach, using a commercially available wire bonder. Methods for fixing wires to wafers using either polymers, nickel electroplating or mechanical silicon clamps are also shown. Nickel electroplating offers the most promising permanent fixing technique, since both a strong mechanical and good electrical connection to the wire is achieved during the same process step. Resistively heated microactuators are also fabricated by integrating prestrained SMA wires onto silicon cantilevers. These microactuators exhibit displacements that are among the highest yet reported. The actuators also feature a relatively low power consumption and high reliability during longterm cycling. New designs for gas microvalves are presented and valves using both SMA sheets and SMA wires for actuation are fabricated. The SMA-sheet microvalve exhibits a pneumatic performance per footprint area, three times higher than that of previous microvalves. The SMA-wire-actuated microvalve also allows control of high gas flows and in addition, offers benefits of lowvoltage actuation and low overall power consumption.<br>QC 20120514
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Forke, Roman. "Mikromechanisches kraftgekoppeltes Sensor-Aktuator-System für die resonante Detektion niederfrequenter Schwingungen." Doctoral thesis, Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-100498.
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Die vorliegende Arbeit beschreibt die Entwicklung und Charakterisierung eines mikromechanischen kraftgekoppelten Schwingsystems für die resonante Detektion niederfrequenter Schwingungen. Es wird ein neuartiges Prinzip vorgestellt, das es ermöglicht, niederfrequente Vibrationen frequenzselektiv zu erfassen. Mittels Amplitudenmodulation wird das niederfrequente Signal in einen höheren Frequenzbereich umgesetzt. Durch Ausnutzung der mechanischen Resonanzüberhöhung wird aus dem breitbandigen Signal ein schmales Band herausgefiltert, die anderen Frequenzbereiche werden unterdrückt. Auf diese Weise wird direkt die spektrale Information des niederfrequenten Signals gewonnen. Eine Fourier-Transformation ist hierbei nicht notwendig. Die Abstimmung des Sensors erfolgt über eine Wechselspannung und führt dadurch zu einer einfachen Auswertung. Die Schwerpunkte der Arbeit liegen in den theoretischen Untersuchungen zum neuartigen Sensorprinzip, in der Entwicklung einer mikromechanischen Sensorstruktur zum Einsatz des neuen Prinzips sowie in der Entwicklung und Charakterisierung eines Messsystems zur Detektion niederfrequenter mechanischer Schwingungen mit dem neuen Sensor<br>This thesis describes the development and characterization of a micromechanical force coupled oscillator system for the resonant detection of low frequency vibrations. It presents a novel working principle that enables spectral measurements of low frequency vibrations. The low frequency spectral content is converted into a higher frequency range by means of amplitude modulation. Due to the mechanical resonance a narrow band is filtered out of the wide band vibration signal. The remaining frequency content is suppressed. Hence, the spectral information is directly obtained with the sensor system without a fast Fourier transform. The tuning is done with an AC voltage resulting in a simple analysis. The main focuses of the work are the theoretical analysis of this novel sensor principle, the development of the micromechanical sensor structure for the use of the novel principle as well as the development and characterization of a measurement system for the spectral detection of low frequency mechanical vibrations with the developed sensor system