Journal articles: 'Wafer level packaging for MEMS'

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Esashi, Masayoshi. "Wafer level packaging of MEMS." Journal of Micromechanics and Microengineering 18, no. 7 (2008): 073001. http://dx.doi.org/10.1088/0960-1317/18/7/073001.

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Gooch, Roland, and Thomas Schimert. "Low-Cost Wafer-Level Vacuum Packaging for MEMS." MRS Bulletin 28, no. 1 (2003): 55–59. http://dx.doi.org/10.1557/mrs2003.18.

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AbstractVacuum packaging of high-performance surface-micromachined uncooled microbolometer detectors and focal-plane arrays (FPAs) for infrared imaging and nonimaging applications, inertial MEMS (microelectromechanical systems) accelerometers and gyroscopes, and rf MEMS resonators is a key issue in the technology development path to low-cost, high-volume MEMS production. In this article, two approaches to vacuum packaging for MEMS will be discussed. The first is component-level vacuum packaging, a die-level approach that involves packaging individual die in a ceramic package using either a silicon or germanium lid. The second approach is wafer-level vacuum packaging, in which the vacuum-packaging process is carried out at the wafer level prior to dicing the wafer into individual die. We focus the discussion of MEMS vacuum packaging on surface-micromachined uncooled amorphous silicon infrared microbolometer detectors and FPAs for which both component-level and wafer-level vacuum packaging have found widespread application and system insertion. We first discuss the requirement for vacuum packaging of uncooled a-Si microbolometers and FPAs. Second, we discuss the details of the component-level and wafer-level vacuum-packaging approaches. Finally, we discuss the system insertion of wafer-level vacuum packaging into the Raytheon 2000AS uncooled infrared imaging camera product line that employs a wafer-level-packaged 160 × 120 pixel a-Si infrared FPA.

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LEE, CHENGKUO. "Progress in Wafer Level MEMS Packaging." Journal of Japan Institute of Electronics Packaging 10, no. 1 (2007): 42–51. http://dx.doi.org/10.5104/jiep.10.42.

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Gooch, R., T. Schimert, W. McCardel, B. Ritchey, D. Gilmour, and W. Koziarz. "Wafer-level vacuum packaging for MEMS." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 17, no. 4 (1999): 2295–99. http://dx.doi.org/10.1116/1.581763.

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Mohri, Mamoru, Masayoshi Esashi, and Shuji Tanaka. "MEMS Wafer-level Packaging Technology Using LTCC Wafer." IEEJ Transactions on Sensors and Micromachines 132, no. 8 (2012): 246–53. http://dx.doi.org/10.1541/ieejsmas.132.246.

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Mohri, Mamoru, Masayoshi Esashi, and Shuji Tanaka. "MEMS Wafer-Level Packaging Technology Using LTCC Wafer." Electronics and Communications in Japan 97, no. 9 (2014): 42–51. http://dx.doi.org/10.1002/ecj.11720.

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Tian, J., S. Sosin, J. Iannacci, R. Gaddi, and M. Bartek. "RF–MEMS wafer-level packaging using through-wafer interconnect." Sensors and Actuators A: Physical 142, no. 1 (2008): 442–51. http://dx.doi.org/10.1016/j.sna.2007.09.004.

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Zoschke, Kai, and Klaus-Dieter Lang. "Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 000698–725. http://dx.doi.org/10.4071/2015dpc-tp31.

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Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

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Wipf, Selin Tolunay, Alexander Göritz, Matthias Wietstruck, et al. "Effect of wafer-level silicon cap packaging on BiCMOS embedded RF-MEMS switch performance." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, NOR (2017): 1–4. http://dx.doi.org/10.4071/2017-nor-wipf.

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Abstract In this paper, the effect of silicon (Si) cap packaging on the BiCMOS embedded RF-MEMS switch performance is studied. The RF-MEMS switches are designed and fabricated in a 0.25μm SiGe BiCMOS technology for K-band (18 – 27 GHz) applications. The packaging is done based on a wafer-to-wafer bonding technique and the RF-MEMS switches are electrically characterized before and after the Si cap packaging. The experimental data shows the effect of the wafer-level Si cap package on the C-V and S-parameter measurements. The performed 3D FEM simulations prove that the low resistive Si cap, specifically 1 Ω·cm, results in a significant RF performance degradation of the RF-MEMS switch in terms of insertion loss.

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Saha, Rajarshi, Nathan Fritz, Sue Ann Bidstrup-Allen, and Paul A. Kohl. "Packaging-compatible wafer level capping of MEMS devices." Microelectronic Engineering 104 (April 2013): 75–84. http://dx.doi.org/10.1016/j.mee.2012.11.010.

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WANG, Z. F., G. J. QI, J. WEI, P. C. LIM, Y. F. JIN, and C. K. WONG. "A NOVEL WAFER-LEVEL PACKAGING SOLUTION FOR MEMS." International Journal of Computational Engineering Science 04, no. 02 (2003): 339–42. http://dx.doi.org/10.1142/s1465876303001228.

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Yang, Fan, Guowei Han, Jian Yang, et al. "Research on Wafer-Level MEMS Packaging with Through-Glass Vias." Micromachines 10, no. 1 (2018): 15. http://dx.doi.org/10.3390/mi10010015.

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A MEMS fabrication process with through-glass vias (TGVs) by laser drilling was presented, and reliability concerns about MEMS packaging with TGV, likes debris and via metallization, were overcome. The via drilling process on Pyrex 7740 glasses was studied using a picosecond laser with a wavelength of 532 nm. TGVs were tapered, the minimum inlet diameter of via holes on 300 μm glasses was 90 μm, and the relative outlet diameter is 48 μm. It took about 9 h and 58 min for drilling 4874 via holes on a four-inch wafer. Debris in ablation was collected only on the laser inlet side, and the outlet side was clean enough for bonding. The glass with TGVs was anodically bonded to silicon structures of MEMS sensors for packaging, electron beam evaporated metal was used to cover the bottom, the side, and the surface of via holes for vertical electrical interconnections. The metal was directly contacted to silicon with low contact resistance. A MEMS gyroscope was made in this way, and the getter was used for vacuum maintenance. The vacuum degree maintained under 1 Pa for more than two years. The proposed MEMS fabrication flow with a simple process and low cost is very suitable for mass production in industry.

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Seetharaman, Krishnan, Bart van Velzen, Johannes van Wingerden, et al. "A Robust Thin-Film Wafer-Level Packaging Approach for MEMS Devices." Journal of Microelectronics and Electronic Packaging 7, no. 3 (2010): 175–80. http://dx.doi.org/10.4071/imaps.270.

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Micro-electromechanical systems (MEMS) devices are extremely sensitive to their environment, especially at the wafer level, until they are packaged in final form. The harsh back-end (BE) operations that the MEMS devices have to endure include dicing, pick-and-place, wire bonding, and molding. During these processing steps, the MEMS device is exposed to particles and contaminants. Therefore, protection at an early stage is a fundamental requirement. We describe a silicon nitride thin-film capping, which is processed using a sacrificial layer technique only with front-end technology. This approach is suitable for mass production of MEMS devices, owing to the fact that it is more cost-effective when compared to other approaches such as wafer-to-wafer bonding and die-to-wafer bonding. A bulk acoustic wave (BAW) resonator that finds application in the radio frequency (RF) front end, for example, in cell phones, is taken as a MEMS vehicle for our work. It is an example of an extremely sensitive MEMS device, because the resonance frequency shifts significantly when additional mass is accidentally deposited on its surface. The thickness of the silicon nitride capping that is required to withstand all the BE steps, in particular transfer molding, is estimated using simple analytical calculations and finite element model (FEM) simulations. The pressure acting on the thin film capping and the thermal load during molding are included in the FEM model. Using this, the minimum thickness required for the capping is determined. We prove that a BAW resonator capped with silicon nitride at the wafer level can be wafer-thinned, diced, wire bonded, and molded without major degradation in performance.

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ESASHI, MASAYOSHI. "RECENT PROGRESSES OF APPLICATION-ORIENTED MEMS THROUGH INDUSTRY-UNIVERSITY COLLABORATION." International Journal of High Speed Electronics and Systems 16, no. 02 (2006): 693–704. http://dx.doi.org/10.1142/s0129156406003941.

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MEMS research has been carried out through industry-university (Tohoku) collaboration for practical applications. Sophisticated devices such as electrostatically levitated rotational gyroscope, MEMS relay for wafer level packaging, array MEMS including multi-probe data storage and multi-column electron beam lithography system, small diameter fiber optic pressure sensor and SiC micro structure or glass press molding, have been developed. Electrical feedthroughs in glass play important role in the wafer level packaging and array MEMS. Materials such as conductive polymer for recording media, carbon nanotube for electron field emitter, SiC for harsh environment are used in these MEMS because of their unique features.

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Castillou, Paul, Roberto Gaddi, Rob van Kampen, Yaojian Lin, Babak Jamshidi, and Seung Wook Yoon. "Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor." International Symposium on Microelectronics 2016, no. 1 (2016): 000185–89. http://dx.doi.org/10.4071/isom-2016-wa33.

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Abstract The market for portable and mobile data access devices that are wirelessly connected to the cloud anytime and anywhere is exploding. The trend to access any network from anywhere is driving increased functional convergence in the radio, which translates into increased packaging complexity and sophistication. This is creating unprecedented demand for RF components providing more integration- in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as wafer level chip scale packaging (WLCSP) or fan-out wafer level packaging (FO-WLP) solutions such as embedded Wafer Level Ball Grid Array (eWLB) to meet these needs. One of the most promising solutions to enable the required RF performance levels in mobile and wearable devices is the use of RF MEMS Tuners. Mobile original equipment manufacturers (OEMs) are rapidly adopting antenna tuning solutions to be able to provide the required signal strength across the large number of LTE spectrum bands used globally. With RF MEMS technology now maturing, the biggest challenge to address the fast growing opportunity was to find a suitable packaging technology that can deliver RF MEMS tuners in the smallest possible form factor, while maintaining the excellent performance characteristics of the RF MEMS technology. After careful analysis, an eWLB/FO-WLP package was adopted and released to volume production in 2015. The commercial eWLB/FO-WLP RF MEMS tuners outperform traditional RF silicon-on-insulator (SOI) switch-based antenna tuning solutions, resulting in much higher data rates (up to 2×) and improved battery life (up to 40%). Redistribution layers (RDL) in eWLB are utilized for higher electrical performance and complex routing to meet electrical requirements. The ability to utilize embedded passives in a multi-layer eWLB structure provides a number of advantages including cost reduction, footprint reduction and increased reliability. Inductors in eWLB offer significantly better performance compared to inductors in standard on-chip technologies. In this paper, we examine the WLCSP and eWLB packaging assembly flow, solutions to RF design challenges as well as characterization of RF performance. Further improvement of the quality factor of the integrated inductor and capacitors by using low-loss thin-film dielectrics and molding compound in eWLB will be reported as well. Package level reliability test results will also be presented in this paper.

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Kim, Yong-Kook, Eun-Kyung Kim, Soo-Won Kim, and Byeong-Kwon Ju. "Low temperature epoxy bonding for wafer level MEMS packaging." Sensors and Actuators A: Physical 143, no. 2 (2008): 323–28. http://dx.doi.org/10.1016/j.sna.2007.10.048.

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Chingfu Tsou, Hungchung Li, and Hsing-Cheng Chang. "A Novel Wafer-Level Hermetic Packaging for MEMS Devices." IEEE Transactions on Advanced Packaging 30, no. 4 (2007): 616–21. http://dx.doi.org/10.1109/tadvp.2007.906236.

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Howlader, M. M. R., H. Okada, T. H. Kim, T. Itoh, and T. Suga. "Wafer Level Surface Activated Bonding Tool for MEMS Packaging." Journal of The Electrochemical Society 151, no. 7 (2004): G461. http://dx.doi.org/10.1149/1.1758723.

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Shang, Jin Tang, Jun Wen Liu, Di Zhang, et al. "Low Cost Fabrication of Micro Glass Cavities For MEMS Wafer Level and Hermetic Packaging." Key Engineering Materials 483 (June 2011): 23–33. http://dx.doi.org/10.4028/www.scientific.net/kem.483.23.

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Many MEMS devices including accelerometer and gyroscopes, having moving parts, requires hermetic and low cost packaging. In this paper we propose a low cost fabricating process to prepare micro glass cavity arrays for wafer-level and hermetic packaging of MEMS. First, the fundamental of the process was discussed. Then, the process for preparing cavity arrays in Pyrex7740 glass wafer was studied experimentally. After that, the defects of the fabrication were discussed. Results show that wafer-level packaged cavities were prepared, whose diameter was controllably between 200 microns and 2000 microns. It is also disclosed that the defects could be avoided by controlling the process parameters. Results also show that the leakage rate of the single packaged cavities is below 5Χ10-9 Pa.m/s which could meet the hermetic packaging standard.

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Wu, Jing, Shi Xing Jia, Yun Xiang Wang, and Jian Zhu. "Study on the Gold-Gold Thermocompression Bonding for Wafer-Level Packaging." Advanced Materials Research 60-61 (January 2009): 325–29. http://dx.doi.org/10.4028/www.scientific.net/amr.60-61.325.

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The study is performed to implement the Gold-Gold thermocompression bonding for the wafer-level packaging of MEMS chips. Numerous experimental attempts have been carried out to select the metal film adhesive to avoid the Au-Si melt together and optimize bonding processes to intensify the Au-Au eutectic bonding. Finally the results display that the eutectic bonding of the gold-gold are arrived as electrical as well as mechanical interconnection of the MEMS structure and as seal as well as bonding intension.

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Choa, Sung Hoon. "Experimental Studies of Through-Wafer Copper Interconnect in Wafer Level MEMS Packaging." Key Engineering Materials 324-325 (November 2006): 231–34. http://dx.doi.org/10.4028/www.scientific.net/kem.324-325.231.

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In this paper, mechanical reliability issues of copper through-wafer interconnection are investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Improvement methods are also suggested.

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Choa, Sung-Hoon. "Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect." Microsystem Technologies 15, no. 5 (2009): 677–86. http://dx.doi.org/10.1007/s00542-009-0788-3.

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Kroehnert, Steffen, André Cardoso, Steffen Kroehnert, Raquel Pinto, Elisabete Fernandes, and Isabel Barros. "Integration of MEMS in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–23. http://dx.doi.org/10.4071/2017dpc-tp2_presentation6.

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The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/Intel's eWLB technology, aiming to overcome the current limits for MEMS/Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.

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Liu, Yifang, Tingting Dai, Peiqin Xie, et al. "Shorting out bonding method for multi-stack anodic bonding and its application in wafer-level packaging." Modern Physics Letters B 34, no. 32 (2020): 2050369. http://dx.doi.org/10.1142/s0217984920503698.

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Silicon/glass anodic bonding is widely investigated during MEMS packaging of multi-stack structures. The electrical behavior of anode bonding can be described as the charging and discharging process of RC circuit. Here, we conduct the equivalent RC circuit model analysis and experimental investigation, and demonstrate that voltage division and electricity leakage are the dilemma for the conventional multi-stack anodic bonding. By using feedthrough, the feasibility and convenience of “shorting out bonding” is presented, which is exampled through the wafer-level packaging of the MEMS gyroscope. Result from the sensor’s vacuum characterization reveals that shorting out bonding for multi-stack silicon/glass structures is an effective method for wafer-level packaging due to long-term stability and low temperature property.‘

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Bogaerts, L., A. Phommahaxay, C. Gerets, et al. "TEMPORARY PROTECTIVE PACKAGING FOR OPTICAL MEMS." International Symposium on Microelectronics 2011, no. 1 (2011): 001052–57. http://dx.doi.org/10.4071/isom-2011-tha5-paper2.

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The fragility of MEM devices is one of the main concerns in case of standard packaging. Steps such as wafer dicing, die handling, assembly and wire bonding can seriously damage the device functionality if the MEM devices are not properly protected during the assembly processes. In this paper we report for the first time on bonding and removal of protective temporary caps used to ease the packaging of MEMS for optical applications. The package, based on a heat decomposable and photo-patternable polymer sealing ring, is gross leak tight, fulfills the MIL spec for shear testing and respects the thermal budget of Al-coated SiGe micro-mirrors. After release of the micro-mirrors at wafer level, a temporary cap with patterned Unity 2203P is bonded to the device wafer, enabling dicing, followed by assembly of the die to a PCB. This can be done by wire bonding and the cap will finally be removed by applying heat. The protective caps are assembled using a die to wafer approach on a flip-chip bonder. The caps are removed by thermal decomposition of the Unity film, leaving little residues in the patterned area. Debonding is done on the flip-chip tool, allowing a slow separation of the cap and MEMS wafer during heating. Several dies with released micro-mirrors were covered with temporary caps by using the optimized process. After dicing and debonding the mirrors were found to be unharmed. Optical and electrical measurements demonstrate the applicability of the process.

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Lee, Byeungleul, Seonho Seok, and Kukjin Chun. "A study on wafer level vacuum packaging for MEMS devices." Journal of Micromechanics and Microengineering 13, no. 5 (2003): 663–69. http://dx.doi.org/10.1088/0960-1317/13/5/318.

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Yang, Hsueh-An, Mingching Wu, and Weileun Fang. "Localized induction heating solder bonding for wafer level MEMS packaging." Journal of Micromechanics and Microengineering 15, no. 2 (2004): 394–99. http://dx.doi.org/10.1088/0960-1317/15/2/020.

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Monajemi, Pejman, Paul J. Joseph, Paul A. Kohl, and Farrokh Ayazi. "Wafer-level MEMS packaging via thermally released metal-organic membranes." Journal of Micromechanics and Microengineering 16, no. 4 (2006): 742–50. http://dx.doi.org/10.1088/0960-1317/16/4/010.

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Chidambaram, Vivek, Xie Ling, and Chen Bangtao. "Titanium-Based Getter Solution for Wafer-Level MEMS Vacuum Packaging." Journal of Electronic Materials 42, no. 3 (2012): 485–91. http://dx.doi.org/10.1007/s11664-012-2350-9.

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Park, Heung Woo, Seung Hun Han, Hyun Kee Lee, et al. "Low temperature wafer level packaging technology of bulk-micromachined MEMS device." International Symposium on Microelectronics 2010, no. 1 (2010): 000695–702. http://dx.doi.org/10.4071/isom-2010-wp5-paper2.

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New low temperature, low cost, small size packaging technology of novel bulk-micromachined MEMS sensor for mobile applications was developed. The sensor was fabricated with the bulk-micromachining process of SOI substrates and composed with a proof mass, membrane and electrodes for capacitance sensing. The sensor device was capped with very thin (130um-thickness) top and bottom silicon cap wafers which have a 80um-depth cavity. Top and bottom cap wafers were bonded with the sensor wafer with a low temperature curing polymer adhesive lower than 200°C. It is needed that the low temperature packaging technology and the passivation of top and bottom sides of the sensor for keeping the sensor performances and preventing stiction of the proof-mass during the molding processes. After bonding the three substrates, the top cap silicon was dry etched to expose bonding pads for the signal interconnection. The ASIC chip was polished to 75um-thickness, diced and bonded on a half-etched 200um-thick lead-frame with a DAF. The diced wafer-level-capped sensor was stacked on the ASIC, wire bonding was accomplished between the sensor and the ASIC, and the ASIC and the lead-frame and finally transfer molding process was done. The developed package is 24-leads QFN and the dimension is 4.0mm×4.0mm×1.1/1.2mm.

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Jung, Erik. "Packaging Options for MEMS Devices." MRS Bulletin 28, no. 1 (2003): 51–54. http://dx.doi.org/10.1557/mrs2003.17.

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AbstractMicroelectromechanical systems (MEMS) devices can be delicate structures sensitive to damage from handling or environmental influences. Their functionality may furthermore depend on sealing out the environment or being in direct contact with it. Stress, thermal load, and contaminants may change their characteristics. Here, packaging technology is challenged to extend from microelectronics toward MEMS and optoelectronic MEMS (MOEMS). Today's approaches rely on modified single-chip packages derived from the microelectronics industry, wafer-level capping to enable the device to be packaged like an integrated circuit, or highly specialized packages designed to complement the function of the MEMS device itself. Selecting the proper packaging method may tip the scale toward a product success or a product failure. Choosing the right technology, therefore, is a crucial part of the product design.

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Kranz, Michael, Mark Allen, and Tracy Hudson. "In-Situ Wafer-Level Polarization of Electret Films in MEMS Acoustic Sensor Arrays." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 001732–60. http://dx.doi.org/10.4071/2011dpc-wp24.

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MEMS-based electret and polymer piezoelectric transduction techniques have been reported for both acoustic sensors and energy harvesters. Common techniques employed in MEMS polymer polarization include corona discharge and backlighted thyratron. This paper reports a method for post-fabrication in-situ polarization of polymer films embedded within the MEMS device itself. The method utilizes microplasma discharges with self-aligned charging grids integrated within the device to charge fluoropolymer films in a fashion similar to the common corona discharge technique. This in-situ approach enables the integration of uncharged polymer films into MEMS and subsequent post-fabrication and post-packaging polarization, simultaneously enabling the formation of buried or encapsulated electrets as well as eliminating the need to restrict fabrication and packaging processes that might otherwise discharge pre-charged materials. CYTOP, a thermoplastic fluoropolymer encapsulant for electronics, is used as a polymer electret in the current process because it can be spin-cast, has a high resistivity, and is easily etched in oxygen plasma. A microscale charging grid structure is then fabricated and suspended a short distance above the polymer film. After fabrication of the charging grid, standard microfabrication steps are performed to build a single-chip array of MEMS capacitive acoustic sensors designed to capture and analyze waveforms from impacts. After completing the entire fabrication and packaging flow, the polarization process is performed. When energized by a high voltage, the sharp metal edges of the charging grid lead to high dielectric fields that ionize the air in the gap and force electric charge onto the polymer surface. Final sensor arrays have been demonstrated and applied in the classification of acoustic stress pulses generated during impacts of various materials.

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Pan, Kai Lin, Jing Liu, Jiao Pin Wang, and Jing Huang. "Through Silicon Vias (TSVs) Technology for MEMS Packaging." Advanced Materials Research 154-155 (October 2010): 1695–98. http://dx.doi.org/10.4028/www.scientific.net/amr.154-155.1695.

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Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

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Reddy, Jayaprakash, and Rudra Pratap. "Si-gold-glass hybrid wafer bond for 3D-MEMS and wafer level packaging." Journal of Micromechanics and Microengineering 27, no. 1 (2016): 015005. http://dx.doi.org/10.1088/0960-1317/27/1/015005.

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Lin, Chiung-Wen, Hsueh-An Yang, Wei Chung Wang, and Weileun Fang. "Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections." Journal of Micromechanics and Microengineering 17, no. 6 (2007): 1200–1205. http://dx.doi.org/10.1088/0960-1317/17/6/014.

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Hamedi, M., M. Vismeh, and P. Salimi. "A Novel Alignment Technique in Wafer-Level Packaging of MEMS Components." Advanced Materials Research 403-408 (November 2011): 4564–71. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.4564.

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In recent years, assembling and packaging methods of Micro Electro Mechanical System (MEMS) components have been profoundly studied. The focus of this paper is presenting a novel alignment technique in wafer-level packaging. In conventional wafer-level strategies, either an Alignment Template (AT) must have special receptor sites according to the microchip geometry and its material, or the microcomponents should be additionally featured by circular and cross pegs for shape recognition stage. In this article, we have developed electrothermal microclamps (ETMCs) to hold and locate six microchips of 360×360×20 micrometers in a microfixturing cell. This is to provide accurate preliminary positioning for final flip-chip bonding process of wafer-level packaging on a main assembly board (MAB). The new approach enjoys the advantages of omitting special AT with receptor sites and using identical ETMCs for diverse assembly configurations. Being applicable for different types of microcomponent materials, it does necessitate no surface treatment on microcomponents such as Semidry uniquely orienting self-organizing parallel assembly (Semi-DUO-SPASS) technique. Comparing nickel and polysilicon as fabrication materials, corresponding values of input voltage to reach 3 micrometers displacement of the ETMC arm are estimated via finite element analysis to ascertain positioning and holding of microchips. Nickel showed to be a better choice for fabrication due to requiring lower input voltage and lower maximum resulting temperature. The simulation results are verified with published experimental measurements.

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Park, Gil Soo, Ji Hyuk Yu, Sang Won Seo, et al. "Wafer Level Hermetic Packaging for RF-MEMS Devices Using Electroplated Gold Layers." Key Engineering Materials 326-328 (December 2006): 617–20. http://dx.doi.org/10.4028/www.scientific.net/kem.326-328.617.

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Thermocompression bonding of electroplated gold is a promising technique for achieving low temperature, wafer level hermetic bonding without the application of an electric field or high temperature. Silicon wafers were completely bonded at 320 at a pressure of 2.5. The interconnection between the packaged devices and external terminal did not need metal filling and was made by gold films deposited on the sidewall of the via-hole. In the hermeticity test, packaged wafers had the leak rate of 2.74 ± 0.61 × 10-11 Pa m3/s. In the result of application in packaging of FBAR filter, the insertion loss is increased from -0.75dB to -1.09dB at 1.9.

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Shiraishi, Akinori, Mitsutoshi Higashi, Kei Murayama, Yuichi Taguchi, and Kenichi Mori. "Wafer Level Package for MEMS with TSVs and Hermetic Seal." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 002314–35. http://dx.doi.org/10.4071/2011dpc-tha24.

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In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

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Wang, Qian, Sung Hoon Choa, Woon Bae Kim, Jun Sik Hwang, Suk Jin Ham, and Chang Youl Moon. "Reliability of Hermetic RF MEMS Wafer Level Packaging Using Au-Sn Eutectic Bonding." Key Engineering Materials 326-328 (December 2006): 609–12. http://dx.doi.org/10.4028/www.scientific.net/kem.326-328.609.

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In this paper, a low temperature hermetic wafer level packaging scheme for the RFMEMS devices is presented. For hermetic sealing, Au-Sn multilayer metallization with a square loop of 70 %m in width is performed. The size of the MEMS package is 1mm × 1mm × 700 %m. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. The total insertion loss for the packaging is 0.075 dB at 2 GHz.

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Fröhlich, Alexander, Christian Hofmann, Patrick Rochala, Jonas Kimme, Martin Kroll, and Verena Kräusel. "Selective induction heating of metallic microstructures for wafer-level MEMS packaging." International Journal of Applied Electromagnetics and Mechanics 63 (July 8, 2020): S13—S20. http://dx.doi.org/10.3233/jae-209121.

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CHEN De-yong, 陈德勇, 曹明威 CAO Ming-wei, 王军波 WANG Jun-bo, 焦海龙 JIAO Hai-long, and 张健 ZHANG Jian. "Fabrication and wafer-level vacuum packaging of MEMS resonant pressure sensor." Optics and Precision Engineering 22, no. 5 (2014): 1235–42. http://dx.doi.org/10.3788/ope.20142205.1235.

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Murillo, Gonzalo, Zachary J. Davis, Stephan Keller, et al. "Novel SU-8 based vacuum wafer-level packaging for MEMS devices." Microelectronic Engineering 87, no. 5-8 (2010): 1173–76. http://dx.doi.org/10.1016/j.mee.2009.12.048.

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Lee, Hai-Young, Young-Soo Kwon, Yo-Tak Song, and Jae-Young Park. "Microstrip Silicon-MEMS Package for Wafer-Level Chip-Scale Microwave Packaging." Japanese Journal of Applied Physics 42, Part 1, No. 9A (2003): 5531–35. http://dx.doi.org/10.1143/jjap.42.5531.

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Wu, Guoqiang, Dehui Xu, Bin Xiong, Yuchen Wang, Yuelin Wang, and Yinglei Ma. "Wafer-Level Vacuum Packaging for MEMS Resonators Using Glass Frit Bonding." Journal of Microelectromechanical Systems 21, no. 6 (2012): 1484–91. http://dx.doi.org/10.1109/jmems.2012.2211572.

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Zhang, Qing, Paul-Vahé Cicek, Frederic Nabki, and Mourad El-Gamal. "Thin-film encapsulation technology for above-IC MEMS wafer-level packaging." Journal of Micromechanics and Microengineering 23, no. 12 (2013): 125012. http://dx.doi.org/10.1088/0960-1317/23/12/125012.

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Choa, Sung Hoon, Moon Chul Lee, and Yong Chul Cho. "Effects of Packaging Induced Stress on MEMS Devices and Its Improvements." Key Engineering Materials 326-328 (December 2006): 529–32. http://dx.doi.org/10.4028/www.scientific.net/kem.326-328.529.

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In MEMS, packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. The conventional MEMS SOI (silicon-on-insulator) gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. Therefore we propose a packaged SiOG (Silicon On Glass) process technology and more robust spring design.

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Tessier, Ted. "Extending WLCSP Packaging Technology Capabilities to Enable Miniaturized Sensor and MEMS Packaging Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (2016): 000397–420. http://dx.doi.org/10.4071/2016dpc-ta23.

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WLCSP has been widely deployed in portable computing and communication devices for efficient die level packaging of integrated semiconductor and integrated passive applications. More recently with the proliferation of smart phone capabilities and applications as well as the emergence of Internet of Things and Wearable Electronics, MEMS and sensor devices in minimized package formats have become increasingly pervasive. These include image sensors, light sensors, finger print sensors as well as accelerometer, gyroscope and other MEMS motion sensing devices. It is predicted that the widespread adoption of WLCSP packaging for sensing applications will accelerate the proliferation of the incorporation of multiple sensor technologies within future communication devices. A number of these MEMS/Sensor applications have been able to leverage the existing WLCSP technology infrastructure and has led to opportunities to packaging and cost-effective standardization and miniaturization. On the other hand, some significant new changes to WLCSP process flows have also emerged that have had to be addressed. This paper will provide an overview of MEMS and Sensor applications that are currently or will use 2D, 2.5D or 3D wafer level packaging formats. Process enhancements including the ability to process thinner substrates with the adoption of temporary carrier technologies will also be highlighted.

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Esashi, Masayoshi, and Shuji Tanaka. "Integrated Microsystems." Advances in Science and Technology 81 (September 2012): 55–64. http://dx.doi.org/10.4028/www.scientific.net/ast.81.55.

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Technology called MEMS (Micro Electro Mechanical Systems) or microsystems are heterogeneous integration on silicon chips and play important roles as sensors. MEMS as switches and resonators fabricated on LSI are needed for future multi-band wireless systems. MEMS for safety systems as event driven tactile sensor network for nursing robot are developed. Wafer level packaging for MEMS and open collaboration to reduce the cost for the development are discussed.

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Sutanto, Jemmy, D. H. Kang, J. H. Yoon, et al. "CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 000916–36. http://dx.doi.org/10.4071/2013dpc-tp33.

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This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size &gt; 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

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Tanaka, Shuji. "Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues." Microelectronics Reliability 54, no. 5 (2014): 875–81. http://dx.doi.org/10.1016/j.microrel.2014.02.001.

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Journal articles on the topic 'Wafer level packaging for MEMS'

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