Relevant bibliographies by topics / Wet chemical semiconductor etching processes

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers
  5. Reports

Academic literature on the topic 'Wet chemical semiconductor etching processes'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Wet chemical semiconductor etching processes"

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VOSHCHENKOV, ALEXANDER M. "FUNDAMENTALS OF PLASMA ETCHING FOR SILICON TECHNOLOGY (PART 1)." International Journal of High Speed Electronics and Systems 01, no. 03n04 (September 1990): 303–45. http://dx.doi.org/10.1142/s0129156490000149.

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Over the past decade, as the rapid evolution of semiconductor technology has progressed towards submicron design rules, plasma (dry) etching has supplanted simple wet etching processes for the transfer of patterns. To understand the underlying need for development of plasma etching, a brief background of integrated semiconductor technology is presented. Along with a historical perspective of the evolution of plasma etching, the relationship of plasma etching to lithography needs, its basic characteristics and advantages over wet chemical processing are discussed. Following this, relevant concepts of plasma physics and chemistry, based on experience with plasma etching applications for silicon technology, which can be used as building blocks for technology development are described.
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Saito, Suguru, Yoshiya Hagimoto, Hayato Iwamoto, and Yusuke Muraki. "Mechanism of Plasma-Less Gaseous Etching Process for Damaged Oxides from the Ion Implantation Process." Solid State Phenomena 145-146 (January 2009): 227–30. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.227.

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Recently, plasma-less gaseous etching processes have attracted attention for their interesting etching properties. Previously, we reported on the etching properties of theses processes for various kinds of oxides and revealed that they reduce the etch rate of the chemical-vapor-deposited (CVD) oxides more than the conventional wet etching process does [1]. Our results also revealed that depressions called divots in the CVD oxide of the shallow trench isolation (STI) became smaller in size by substituting a plasma-less gaseous etching process for the conventional wet etching process. In semiconductor manufacturing, many processes are used to remove oxides damaged during ion implantation or reactive ion etching on the device surface. Therefore, it is very important to understand the etching properties of plasma-less gaseous etching processes for damaged oxides as well as those for other kinds of oxides. In this report, we evaluate the etching properties of one particular plasma-less gaseous etching process for oxide films damaged during the ion implantation process under various conditions and discuss the mechanism of interesting etching properties for the damaged oxides.
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Patzig, Sebastian, Gerhard Roewer, Edwin Kroke, and Ingo över. "NOHSO4/HF – A Novel Etching System for Crystalline Silicon." Zeitschrift für Naturforschung B 62, no. 11 (November 1, 2007): 1411–21. http://dx.doi.org/10.1515/znb-2007-1110.

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Solutions consisting of HF - NOHSO4 - H2SO4 exhibit a strong reactivity towards crystalline silicon which is controlled by the concentrations of the reactive species HF and NO+. Selective isotropic and anisotropic wet chemical etching with these solutions allows to generate a wide range of silicon surface morphology patterns. Traces of Ag+ ions stimulate the reactivity and lead to the formation of planarized (polished) silicon surfaces. Analyses of the silicon surface, the etching solution and the gas phase were performed with scanning electron microscopy (SEM), DR/FT-IR (diffusive reflection Fourier transform infra-red), FT-IR, Raman and NMR spectroscopy, respectively. It was found that the resulting silicon surface is hydrogen-terminated. The gas phase contains predominantly SiF4, NO and N2O. Furthermore, NH4+ is produced in solution. The study has confirmed the crucial role of nitrosyl ions for isotropic wet chemical etching processes. The novel etching system is proposed as an effective new way for selective surface texturing of multi- and monocrystalline silicon. A high etching bath service lifetime, besides a low contamination of the etching solution with reaction products, provides ecological and economical advantages for the semiconductor and solar industry.
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Dolah, Asban, Muhammad Azmi Abd Hamid, Mohamad Deraman, Ashaari Yusof, Nor Azhadi Ngah, and Norman Fadhil Idham Muhammad. "Ohmic Contact in P-HEMT Wafer Using Metallization with Ge/Au/Ni/Au." Advanced Materials Research 896 (February 2014): 351–53. http://dx.doi.org/10.4028/www.scientific.net/amr.896.351.

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In this study, Ohmic contact were fabricated on AlGaAs HEMTs structure. A good metal-semiconductor interface are essentially for achieving lower specific contact resistance. An AlGaAs epi wafer was supply by the vendor. AlGaAs substrate was cleaned using wet chemical etching. Electrodes were fabricated through a sequenced of lithography, cleaning, sputtering and lift-off processes. The electrodes were made with metal layers of Ge, Au and Ni. Parameters such as metal thickness, annealing temperatures (from 300°C to 400°C) and annealing time were varies during fabrication process. Electrical characterizations after annealing are carried out using transmission line method (TLM) to obtain the specific contact resistance. Annealing temperature between 340°C to 360°C produced contact resistance below 5 x 10ˉ³Ω/cm-2.
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PEARTON, S. J. "HYDROGEN IN CRYSTALLINE SEMICONDUCTORS: PART II–III–V COMPOUNDS." International Journal of Modern Physics B 08, no. 10 (April 30, 1994): 1247–342. http://dx.doi.org/10.1142/s0217979294000592.

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The properties of hydrogen in III–V semiconductors are reviewed. Atomic hydrogen is found to passivate the electrical activity of shallow donor and acceptor dopants in virtually all III–V materials, including GaAs, Alx Ga1−x As, InP, InGaAs, GaP, InAs, GaSb, InGaP, AlInAs and AlGaAsSb. The passivation is due to the formation of neutral dopant-hydrogen complexes, with hydrogen occupying a bond-centered position in p-type semiconductors and an anti-bonding site in n-type materials. The dopants are reactivated by annealing at ≤400° C. The neutral hydrogen-dopant complexes have characteristic vibrational bands, around 2000cm−1 for stretching modes and 800cm−1 for wagging modes. Deep levels such as EL2, DX and metallic impurities are also passivated by hydrogen. The diffusivity of hydrogen is high in III–V semiconductors and unintentional incorporation can occur during epitaxial growth, annealing in H2, dry etching, water boiling, wet etching or chemical vapor deposition processes, Surface passivation by (NH4)xS or NH3 plasma treatment is also effective in lowering surface recombination velocities in many III-V semiconductors.
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Zhang, Zhi Yu, Xu Yang, and Li Gong Zheng. "Fabrication of Computer Generated Hologram for Aspheric Surface Measurement." Advanced Materials Research 1136 (January 2016): 620–23. http://dx.doi.org/10.4028/www.scientific.net/amr.1136.620.

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High-precision aspheric surfaces are generally measured using interferometer with a computer-generated holograms (CGH), which has a wavy line pattern fabricated onto a glass substrate. CGH patterns are generally made using lithographic techniques that was developed for semiconductor industry. Patterns can be subsequently etched into glass substrate using reactive ion or chemical etching. The accuracy of the drawn pattern on a CGH decides the accuracy of the measurement. Draw pattern error mainly includes the line-width deviation and its position error. In this paper, the influences of defocus of drawing laser and the wet-etching processes on the line-width were firstly investigated. On the other hand, the position error under different line-width was obtained by analyzing the relationship of line-width error and the position error. Based on the above-obtained results, a CGH having a diameter of 80 mm and the minimum line-width of 1.8 μm was successfully fabricated. Testing results showed that the wavefront error was only 3.79 nm, significantly higher than the commercial-available ones. The fabricated CGH is expected to use in the high-precision measurement of asphercal surfaces.
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Choi, Geun Min. "Necessity of Cleaning and its Application in Future Memory Devices." Solid State Phenomena 219 (September 2014): 3–10. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.3.

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Concerning the processes of the semiconductor industry, device integration is increasing and cell structure is becoming more complicated, which brings many new kinds of challenges. The basic requirements for a future integration device are minimum feature size reduction with device integration and high-speed operation with sufficient cell capacitance. Many kinds of conventional films including electrode and dielectric materials should be altered to meet device requirements. Moreover, as the allowance level for contaminants on substrate surfaces becomes more stringent, the importance of removing them becomes even greater. Because of this, the semiconductor process for high quality device fabrication will never be realized without perfect cleaning on all surfaces. It is reported that the conventional cleaning solutions such as a NH4OH/H2O2/H2O (SC-1) solution (1:4:20, 80 °C), H2SO4/H2O2 (SPM) solution (4:1, 90 to 120°C), and HCl/H2O2/H2O (HPM) solution (1:1:6, 80 to 90°C) are not compatible with metal film exposed surfaces with very tiny patterns, due to the fast etching rate of metal films [1] . In 1995, at the base of the mechanism of the removal of the adhered contaminants such as metallic impurities, particles and organics, T. Ohmi proposed a total room temperature wet cleaning process (so called “UCT cleaning”) [2]. As a result of the continuous research on developed cleaning, the five steps process was revised to a four step room temperature wet cleaning for real device cleaning. The cleaning consists of 1) CO2 added O3-UPW cleaning for removing organic and metallic impurities, 2) NH3 added H2-UPW+MS cleaning for removing of particles, 3) HF/H2O2(FPM) cleaning for removing metallic impurities, and 4) H2-UPW+MS rinse for the removal of chemical residues, prevention of particle re-adhesion, suppression of native oxide growth, and enhancement of H-termination.
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Collins, George, and Donald J. Rej. "Plasma Processing of Advanced Materials." MRS Bulletin 21, no. 8 (August 1996): 26–31. http://dx.doi.org/10.1557/s0883769400035673.

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A plasma, commonly referred to as the “fourth state of matter,” is an ensemble of randomly moving charged particles with a sufficient particle density to remain, on average, electrically neutral. While their scientific study dates from the 19th century, plasmas are ubiquitous, comprising more than 99% of the known material universe. The term “plasma” was first coined in the 1920s by Irving Langmuir at the General Electric Company after the vague resemblance of a filamented glow discharge to a biological plasma.Plasmas are studied for many reasons. Physicists analyze the collective dynamics of ions and electron ensembles, utilizing principals of classical electromagnetics, and fluid and statistical mechanics, to better understand astrophysical, solar, and ionospheric phenomenon, and in applied problems such as thermonuclear fusion. Electrical engineers use plasmas to develop efficient lighting, and high-power electrical switchgear, and for magneto-hydrodynamic (MHD) power conversion. Aerospace engineers apply plasmas for attitude adjustment and electric propulsion of satellites. Chemists, chemical engineers, and materials scientists routinely use plasmas in reactive ion etching and sputter deposition. These methods are commonplace in microelec tronics since they allow synthesis of complex material structures with submicron feature sizes. A substantial portion of the multi-billion-dollar market for tooling used to manufacture semiconductors employs some form of plasma process. When compared with traditional wet-chemistry techniques, these dry processes result in minimal waste generation. Plasmas are also useful in bulk processing—for example as thermal sprays for melting materials.While the quest for controlled thermonuclear fusion dominated much of plasma research in the 1960s and 1970s, in the last 20 years it has been the application of plasmas to materials processing that has provided new challenges for many plasma practitioners. It is not surprising that the guest editors and several of the authors for this issue of MRS Bulletin come from a fusion plasma-physics background.
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Causier, Alexandre, Isabelle Gérard, Muriel Bouttemy, Pierre Tran-Van, and Arnaud Etcheberry. "Fundamentals of III-V Semiconductor Electrochemistry and Wet Etching Processes: Br2 Etching Properties onto InP." ECS Transactions 35, no. 8 (December 16, 2019): 61–66. http://dx.doi.org/10.1149/1.3567737.

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Ikossi‐Anastasiou, K., S. C. Binari, G. Kelner, J. B. Boos, C. S. Kyono, J. Mittereder, and G. L. Griffin. "Wet Chemical Etching with Lactic Acid Solutions for InP ‐ based Semiconductor Devices." Journal of The Electrochemical Society 142, no. 10 (October 1, 1995): 3558–64. http://dx.doi.org/10.1149/1.2050022.

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Dissertations / Theses on the topic "Wet chemical semiconductor etching processes"

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Patzig-Klein, Sebastian. "Untersuchungen zum Reaktionsverhalten kristalliner Siliziumoberflächen in HF-basierten Ätzlösungen." Doctoral thesis, TU Bergakademie Freiberg, 2009. https://tubaf.qucosa.de/id/qucosa%3A22706.

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Die vorliegende Arbeit befasst sich mit der grundlegenden Untersuchung von Reaktionsmustern kristalliner Si-Oberflächen in HF-basierten Lösungen. Ausgehend von den industriell genutzten HF-HNO3-H2O-Gemischen wurden wisher wenig untersuchte HF/HNO3-Konzentrationsverhältnisse, die durch gelöste Stickoxide bedingten Folgereaktionen sowie der PH-Wert als Steuerparameter zur Aufarbeitung feinkörniger Si-Rohstoffe (Korngröße ≤ 0,5 mm) identifiziert. Die in diesem Kontext zentrale Rolle der NO+-Ionen wurde durch Untersuchung der spezifischen Reaktionsmuster an kristallinen as-cut und hydrophobierten Si-Oberflächen sowie bei Umsetzungen mit Oligosilanen als Modellverbindungen bestätigt. Die aus den umfassenden analytischen Daten (FT-IR-, Raman-, NMR-Spektroskopie, IC, REM-EDX, AFM) gewonnenen Erkenntnisse liefern einen wichtigen Beitrag zum Verständnis nasschemischer Halbleiterätzprozesse und erschließen neue Anwendungsfelder.
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Patzig-Klein, Sebastian. "Untersuchungen zum Reaktionsverhalten kristalliner Siliziumoberflächen in HF-basierten Ätzlösungen." Doctoral thesis, Technische Universitaet Bergakademie Freiberg Universitaetsbibliothek "Georgius Agricola&quot, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:105-qucosa-27118.

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Die vorliegende Arbeit befasst sich mit der grundlegenden Untersuchung von Reaktionsmustern kristalliner Si-Oberflächen in HF-basierten Lösungen. Ausgehend von den industriell genutzten HF-HNO3-H2O-Gemischen wurden wisher wenig untersuchte HF/HNO3-Konzentrationsverhältnisse, die durch gelöste Stickoxide bedingten Folgereaktionen sowie der PH-Wert als Steuerparameter zur Aufarbeitung feinkörniger Si-Rohstoffe (Korngröße ≤ 0,5 mm) identifiziert. Die in diesem Kontext zentrale Rolle der NO+-Ionen wurde durch Untersuchung der spezifischen Reaktionsmuster an kristallinen as-cut und hydrophobierten Si-Oberflächen sowie bei Umsetzungen mit Oligosilanen als Modellverbindungen bestätigt. Die aus den umfassenden analytischen Daten (FT-IR-, Raman-, NMR-Spektroskopie, IC, REM-EDX, AFM) gewonnenen Erkenntnisse liefern einen wichtigen Beitrag zum Verständnis nasschemischer Halbleiterätzprozesse und erschließen neue Anwendungsfelder.
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Mistkawi, Nabil George. "Fundamental Studies in Selective Wet Etching and Corrosion Processes for High-Performance Semiconductor Devices." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/6.

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As multistep, multilayer processing in semiconductor industry becomes more complex, the role of cleaning solutions and etching chemistries are becoming important in enhancing yield and in reducing defects. This thesis demonstrates successful formulations that exhibit copper and tungsten compatibility, and are capable of Inter Layer Dielectric (ILD) cleaning and selective Ti etching. The corrosion behavior of electrochemically deposited copper thin films in deareated and non-dearated cleaning solution containing hydrofluoric acid (HF) has been investigated. Potentiodynamic polarization experiments were carried out to determine active, active-passive, passive, and transpassive regions. Corrosion rates were calculated from tafel slopes. ICP-MS and potentiodynamic methods yielded comparable Cu dissolution rates. Interestingly, the presence of hydrogen peroxide in the cleaning solution led to more than an order of magnitude suppression of copper dissolution rate. We ascribe this phenomenon to the formation of interfacial CuO which dissolves at slower rate in dilute HF. A kinetic scheme involving cathodic reduction of oxygen and anodic oxidation of Cu0 and Cu+1 is proposed. It was determined that the reaction order kinetics is first order with respect to both HF and oxygen concentrations. The learnings from copper corrosion studies were leveraged to develop a wet etch/clean formulation for selective titanium etching. The introduction of titanium hard-mask (HM) for dual damascene patterning of copper interconnects created a unique application in selective wet etch chemistry. A formulation that addresses the selectivity requirements was not available and was developed during the course of this dissertation. This chemical formulation selectively strips Ti HM film and removes post plasma etch polymer/residue while suppressing the etch rate of tungsten, copper, silicon oxide, silicon carbide, silicon nitride, and carbon doped silicon oxide. Ti etching selectivity exceeding three orders of magnitude was realized. Surprisingly, it exploits the use of HF, a chemical well known for its SiO2 etching ability, along with a silicon precursor to protect SiO2. The ability to selectively etch the Ti HM without impacting key transistor/interconnect components has enabled advanced process technology nodes of today and beyond. This environmentally friendly formulation is now employed in production of advanced high-performance microprocessors and produced in a 3000 gallon reactor.
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Jain, Rahul. "Formation of Aminosilane and Thiol Monolayers on Semiconductor Surfaces and Bulk Wet Etching of III--V Semiconductors." Diss., The University of Arizona, 2012. http://hdl.handle.net/10150/255196.

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Continuous scaling down of the dimensions of electronic devices has made present day computers more powerful. In the front end of line, the minimum lateral dimensions in a transistor have shrunk from 45 nm in 2007 to 22 nm currently, and the gate oxide film thickness is two to three monolayers. This reduction in dimensions makes surface preparation an increasingly important part of the device fabrication process. The atoms or molecules that terminate surfaces function as passivation layers, diffusion barriers, and nucleation layers. In the back end of line, metal layers are deposited to connect transistors. We demonstrate a reproducible process that deposits a monolayer of aminopropyltrimethoxysilane molecules less than one nanometer thick on a silicon dioxide surface. The monolayer contains a high density of amine groups that can be used to deposit Pd and Ni and subsequently Co and Cu to serve as the nucleation layer in an electroless metal deposition process. Because of the shrinking device dimensions, there is a need to find new transistor channel materials that have high electron mobilities along with narrow band gaps to reduce power consumption. Compound III--V channel materials are candidates to enable increased performance and reduced power consumption at the current scaled geometries. But many challenges remain for such high mobility materials to be realized in high volume manufacturing. For instance, low defect density (1E7 /cm²) III--V and Ge on Si is the most fundamental issue to overcome before high mobility materials become practical. Unlike Si, dry etching of III-V semiconductor surfaces is believed to be difficult and uncontrollable. Therefore, new wet etching chemistries are needed. Si has been known to passivate by etching in hydrofluoric acid, but similar treatments on III--Vs are known to temporarily hydrogen passivate the surfaces. However, any subsequent exposure to the ambient reoxidizes the surface, resulting in a chemically unstable and high defect density interface. This work compares old and new wet etching chemistries and investigates new methods of passivating the III--V semiconductors.
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Lippold, Marcus. "Beiträge zum Verständnis des sauren nasschemischen Ätzens von Silicium." Doctoral thesis, Technische Universitaet Bergakademie Freiberg Universitaetsbibliothek "Georgius Agricola", 2014. http://nbn-resolving.de/urn:nbn:de:bsz:105-qucosa-145077.

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Der Siliciumauflöseprozess in HF-HNO3-H2SO4/H2O-Lösungen unterscheidet sich vom Ätzprozess in HF-HNO3-H2O-Standardmischungen in Bezug auf die Reaktivität gegenüber Silicium, erzielte Oberflächenmorpholgien sowie die beim Ätzen entstehenden gelösten und gasförmigen Produkte. Durch die Behandlung in H2SO4-reichen HF-HNO3-H2SO4/H2O-Lösungen werden auf Siliciumwafern Texturen mit hoher Rauigkeit und geringer Reflexion erzeugt. mc-Si-Solarzellen texturiert durch eine H2SO4-reiche Ätzlösung weisen vergleichend zu Solarzellen mit Standardtexturen höhere Wirkungsgrade auf. In HF-HNO3-H2SO4/H2O-Lösungen mit hohen Schwefelsäurekonzentrationen (c(H2SO4) > c(H2O)) wirkt sowohl das Salpetersäuremolekül HNO3 als auch das Nitrylion NO2+ als Oxidationsmittel. Trifluorsilan HSiF3 und Hexafluordisiloxan F3SiOSiF3 wurden erstmalig als gasförmige Produkte des sauren nasschemischen Ätzens identifiziert. Anhand von Modellreaktionen zur Reaktivität von Nitrylionen wurde deren Reduktionssequenz im Siliciumätzprozess aufgeklärt.
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Chen, Jian-you, and 陳建佑. "Fabrication of Large-area Periodic Arrays of Single-crystalline Silicon Nanorods by Chemical Wet Etching Processes." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/45706381201509235121.

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碩士
國立中央大學
化學工程與材料工程研究所
97
In the present study, we have demonstrated that large-area, length-tunable arrays of vertically aligned Si nanorod arrays were successfully produced on (001)Si substrates by using the PS nanosphere lithography combined with the Au-assisted selective chemical etching process. The crystal structures, formation kinetics, surface wetting behaviors, and optical properties of the Si nanorods produced have been investigated. The SEM and TEM examinations revealed that the diameter of the Si nanorods produced was very uniform and observed to be approximately 126 nm, corresponding to that of RIE-reduced PS sphere mask used. Based on the analyses of the TEM image and the corresponding SAED pattern, it can be concluded that all the produced Si nanorods were single crystalline and the Si nanorods formed along the [001] direction. After a series of cross-sectional SEM examinations, the length variations of Si nanorods produced with etching time for various reaction temperatures were obtained. By measuring the formation rates of Si nanorods at different reaction temperatures, the activation energy for the linear formation of Si nanorods could be determined from an Arrhenius plot to be about 76.7 kJ/mole. The results of the water contact angle measurements indicated that the surfaces of HF-treated Si nanorod arrays exhibited strong hydrophobicity with water contact angle of 125°-150°. The hydrophobic behavior of the HF-treated Si nanorods was discussed in the context of the Cassie model. The UV-Vis analysis results indicated that Si substrate with Si nanorod arrays exhibited low reflection properties (﹤5％) over the visible light range (400-800 nm).
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Lin, Yao-hsing, and 林耀星. "Fabrication of Site- and Size-controllable Periodic Arrays 2D Well-ordered Si Nanostructures by Plasma Modified Nanosphere Lithography and Chemical Wet Etching Processes." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23119866571253488366.

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碩士
國立中央大學
化學工程與材料工程研究所
100
The present study has demonstrated the successful fabrication of density-, size- and shape-controllable Si nanostructure arrays on Si substrates of different orientation by using plasma modified nanosphere lithography and anisotropic wet etching process. The morphologies, crystal structures, compositions, optical and surface properties of the Si nanostructure arrays produced have been systematically investigated by SEM, AFM, TEM, SAED, EDS, XPS, UV-Vis and contact angle analyses. For the fabrication of periodic Si nanohole arrays, we take advantage of O2 plasma RIE treatment, which allows us simultaneously to adjust the diameter of PS nanospheres template and to form a passivation a-SiOx layer on Si serving as the etching mask. The shapes, sizes and positions of Si nanoholes that formed on Si substrates could be tuned by adjusting the diameters of the colloidal nanospheres and the KOH etching time. On the other hand, by combining the plasma modified nanosphere lithography, selective chemical etching process or metal silicide formation, large-area, size- and height-tunable Si nanocone arrays were also successfully fabricated on (001), (110) and (111)Si substrates in this study. From the water contact angle measurements, the surface of HF-treated Si nanohole and nanocone arrays exhibited hydrophobic characteristics. The hydrophobic behavior of Si nanostructures could be explained by the Cassie model. Furthermore, UV-Vis spectroscopic measurements revealed that the nanostructured Si surfaces exhibit strong antireflection properties.The enhanced antireflection properties can be attributed to the light trapping effect resulting from the nanostructure-arrayed Si surfaces.
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Book chapters on the topic "Wet chemical semiconductor etching processes"

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Horn, A., and G. Wachutka. "Three-Dimensional Simulation of Orientation-Dependent Wet Chemical Etching." In Simulation of Semiconductor Processes and Devices 2004, 133–36. Vienna: Springer Vienna, 2004. http://dx.doi.org/10.1007/978-3-7091-0624-2_32.

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Ombaba, Mathew, Salman B. Inayat, and M. Saif Islam. "Wet Chemical and Electrochemical Etching Processes." In Encyclopedia of Nanotechnology, 1–9. Dordrecht: Springer Netherlands, 2015. http://dx.doi.org/10.1007/978-94-007-6178-0_431-2.

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Ombaba, Mathew, Salman B. Inayat, and M. Saif Islam. "Wet Chemical and Electrochemical Etching Processes." In Encyclopedia of Nanotechnology, 4373–80. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-9780-1_431.

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Camon, H., Z. Moktadir, and M. Djafari-Rouhani. "New trends in atomic scale simulation of wet chemical etching of silicon with KOH." In C,H,N and O in Si and Characterization and Simulation of Materials and Processes, 142–45. Elsevier, 1996. http://dx.doi.org/10.1016/b978-0-444-82413-4.50094-9.

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Conference papers on the topic "Wet chemical semiconductor etching processes"

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Kaneko, Kimihisa, Tomoyoshi Noda, Masayoshi Sakata, and Tomomi Uchiyama. "Observation and Numerical Simulation for Wet Chemical Etching Process of Semiconductor." In ASME/JSME 2003 4th Joint Fluids Summer Engineering Conference. ASMEDC, 2003. http://dx.doi.org/10.1115/fedsm2003-45707.

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This paper concerns with the basic investigations on the wet chemical etching of semiconductors. First, a method to observe the etched cross-section of aluminum layer is developed. It is applied to the observation for the cross-section of a test piece etched in a quiescent etchant. The observation successfully makes clear the time variation for the geometry of the etched cross-section, and elucidates the effects of the resist width on the geometry. Secondly, the numerical simulation for the etching process is performed. The simulated geometry of the etched cross-section is confirmed to agree with the observed result, indicating that the present numerical simulation is effectively used to predict the geometry of the etched cross-section.
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Azeredo, Bruno, Keng Hsu, and Placid Ferreira. "Direct Electrochemical Imprinting of Sinusoidal Linear Gratings Into Silicon." In ASME 2016 11th International Manufacturing Science and Engineering Conference. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/msec2016-8835.

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Silicon is an excellent transparent material for building IR micro-optical elements such as holographic and blazed gratings, and curvilinear micro-lenses. Shaping this material in 3D with mirror quality finish and single-digit microscale resolution is challenging due to its brittleness and high-melting point. To achieve these patterning characteristics, electron-beam grayscale lithography is typically selected to pattern a 2.5D feature onto a resist thin-film. Subsequently, the film features are transferred into the underlying silicon substrate by deep-reactive ion etching (DRIE) [1]. Small variations in the resist thickness lead to large shape distortions and reduced patterning repeatability. Further, the direct-write nature of e-beam lithography provides for slow throughput. Developing an alternative, parallel and scalable method to nanopatterning silicon with 2.5D geometrical control may impact emerging areas such as the design of sub-wavelength photonic and micro-optic elements for silicon photonics applications. Micro and nanoscale patterning of inorganic semiconductors (e.g. Silicon) requires traditional micromachining processes such as plasma-assisted etching (e.g. DRIE) and wet-etching (e.g. KOH etching). Neither of the aforementioned processes offer the capability to control the geometry in 3D with resolution in the nanoscale range. Thus, it is desirable to develop a low-temperature, low-stress and ambient approach to nanostructuring silicon in 3D. Wet etching approaches are good candidates for achieving such goal because they bypass the need for high-temperature processing and stressing materials beyond the elastic limit. Yet, they still rely on lithographical steps and offer limited sidewall control, restricting the scope of features it can produce. In recent literature, catalyst-based wet etching processes such as metal-assisted chemical etching (MACE) have been shown to pattern high-aspect ratio structures in semiconductors [2–3]. Some researchers have achieved control over the etch profile and etching direction, generating a limited set of interesting 3D objects [4–6]. The degrees of freedom in MACE patterning are still highly constrained due to limited control of the catalyst motion. Additionally, thin-film based MACE relies on intermediate 2D masking steps to pattern the catalyst which are often lithographical. Thus, this indirect approach to patterning silicon increases lead time and processing costs. In this paper, Mac-imprint, a direct imprint configuration of MACE, is introduced to overcome these fundamental barriers. It relies on the use of a catalytic stamp immersed in the etchant and brought against a silicon chip to selectively dissolve it at contact points. Stamps can be reused multiple times to pattern substrates with lifetimes that are dependent solely on its chemical and mechanical degradation. This process is inherently non-lithographic and occurs at room temperature. As a demonstration of its high-resolution capabilities, silicon wafers were patterned with a sinusoidal wave whose pitch and amplitude were 1 μm and 250 nm, respectively. The patterned surface RMS error from the ideal surface was measured to be 13 nm. The key drawback of this approach is the generation of porous defects near the vicinity of the contact interface between stamp and substrate. Its spatial distribution is qualitatively discussed in the context of the diffusion model of MACE [7].
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3

Barbieri, Thomas J., and Jan Vandemeer. "Deprocessing of Integrated Sealing Structures from MEMS Devices for Failure Analysis." In ISTFA 2005. ASM International, 2005. http://dx.doi.org/10.31399/asm.cp.istfa2005p0416.

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Abstract Freescale Semiconductor is employing a new, multi-layer integrated seal (IS) on its next generation accelerometers. The IS, which encloses the moveable sensing element, consists of alternating layers of poly-Si and PSG. A technique needed to be developed to remove the integrated seal in order to permit failure analysis. Mechanical methods were attempted first, but these resulted in severe damage to the sensing element. Chemical deprocessing was considered, but eventually abandoned because there seemed to be no way to protect the sensing elements from the wet etchants that would be used on the IS. Eventually, Reactive Ion Etching (RIE) with an Inductively Coupled Plasma (ICP) source proved to be a successful means for removing the IS without impacting the sensing element. As the design of the integrated seal underwent multiple redesigns, the removal process was successfully modified multiple times to comply with these changes. By using the right gases in the correct order, a high level of selectivity was maintained, allowing for removal of successive layers of different materials (poly-Si, PSG) without harming the sensing element. After removal of some IS designs, a wispy residue was observed on the sensing element and remaining IS support pillars. Chemical analysis identified this material as a by-product of the RIE process, and methods were devised to eliminate it.
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Liu, Teren, Tao Fang, Karen Kavanagh, Hongyu Yu, and Guangrui Maggie Xia. "A new wet etching method for black phosphorus layer number engineering: experiment, modeling and DFT simulations." In 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2019. http://dx.doi.org/10.1109/sispad.2019.8870363.

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5

Sun, Shuang, Baotong Zhang, Yuancheng Yang, Xia An, Xiaoyan Xu, Ru Huang, and Ming Li. "Rectangular suspended single crystal Si nanowire with (001) planes and <001> direction developed via TMAH wet chemical etching." In 2020 China Semiconductor Technology International Conference (CSTIC). IEEE, 2020. http://dx.doi.org/10.1109/cstic49141.2020.9282559.

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de Buttet, Côme, Emilie Prevost, Alain Campo, Philippe Garnier, Stephane Zoll, Laurent Vallier, Gilles Cunge, Patrick Maury, Thomas Massin, and Sonarith Chhun. "Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes." In SPIE Advanced Lithography, edited by Sebastian U. Engelmann and Rich S. Wise. SPIE, 2017. http://dx.doi.org/10.1117/12.2257971.

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7

Rath, P., J. C. Chai, H. Y. Zheng, Y. C. Lam, and V. M. Murukeshan. "A Total-Concentration Fixed-Grid Method for Two-Dimensional Diffusion-Controlled Wet Chemical Etching." In ASME 2005 Summer Heat Transfer Conference collocated with the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems. ASMEDC, 2005. http://dx.doi.org/10.1115/ht2005-72186.

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This article presents a total concentration method for two-dimensional wet chemical etching. The proposed procedure is a fixed-grid approach. It is analogous to the enthalpy method used for modeling melting/solidification problems. The governing equation is formulated using the total concentration of the etchant. It includes the reacted and the unreacted concentrations of the etchant. The proposed governing equation includes the interface condition. The reacted concentration is used to capture the etchant-substrate interface implicitly. Since the grids are fixed, a diffusion problem remains a diffusion problem unlike the moving grid approach where the diffusion problem becomes the convection-diffusion problem due to the mesh velocity. For demonstration purposes, the finite volume method is used to solve for the transient concentration distribution of etchant. In this article, two-dimensional diffusion-controlled wet chemical etching processes are modeled. The results obtained from the proposed total concentration method are compared with available “analytic” solutions and solutions from moving-grid approach.
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8

Lee, T. W. "A Review of Wet Etch Formulas for Silicon Semiconductor Failure Analysis." In ISTFA 1996. ASM International, 1996. http://dx.doi.org/10.31399/asm.cp.istfa1996p0319.

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Abstract WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.
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9

Alani, R., R. J. Mitro, and W. Hauffe. "Recent Advances in Broad Ion Beam Based Techniques/Instrumentation for SEM Specimen Preparation of Semiconductors." In ISTFA 1999. ASM International, 1999. http://dx.doi.org/10.31399/asm.cp.istfa1999p0439.

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Abstract The semiconductor industry routinely prepares crosssectional SEM specimens using several traditional techniques. Included in these are cleaving, mechanical polishing, wet chemical etching and focused ion beam (FIB) milling. This presentation deals with a new alternate method for preparation of SEM semiconductor specimens based upon a dedicated broad ion beam instrument. Offered initially as an alternative to wet chemical etching, the instrument was designed to etch and coat SEM and metallographic specimens in one vacuum chamber using inert gas (Ar) ion beams. The system has recently undergone further enhancement by introducing iodine Reactive Ion Beam Etching (RIBE) producing much improved etching/cleaning capabilities compared with inert gas ion beam etching. Further results indicate Ar broad ion beam etching can offer a rapid, simple, more affordable alternative (to FIB machines) for precision cross sections and for “slope cutting,” a technique producing large cross-sections within a short time frame. The overall effectiveness of this system for iodine RIBE etching, for precision cross sectioning and “slope cutting” will be shown for a number of traditional and advanced semiconductor devices.
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10

Malberti, P., and M. Ciappa. "Selective Wet-Etch of Silicon Nitride Passivation Layers." In ISTFA 1998. ASM International, 1998. http://dx.doi.org/10.31399/asm.cp.istfa1998p0429.

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Abstract Selective removal of silicon nitride passivation layers is of major importance in failure analysis of semiconductor devices. Typical applications are: cleaning of the die surface for optical microsccjpy and for removal of superficial contamination, electron microscopy, liquid crystals, voltage contrast, electron beam testing, mechanical microprobing, and . selective layer-by-layer strip. A new wet-etch for silicon nitride passivation layers has been developed, which is fully selective! over aluminum metallization and which preserves full device functionality after passivation removal. For the first time in the failure analysis literature, the chemical recipe and the etching procedure are given in details. This etchant has been experimented for more than two years in many failure analysis laboratories on a wide spectrum of discrete and integrated semiconductor devices, always with excellent results. Its capability and efficiency are illustrated by two failure analysis case histories.
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Reports on the topic "Wet chemical semiconductor etching processes"

1

Snyder, Paul G. Real Time Optical Monitoring of III-V Semiconductor Wet Chemical Etching. Fort Belvoir, VA: Defense Technical Information Center, December 2000. http://dx.doi.org/10.21236/ada387435.

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2

Mistkawi, Nabil. Fundamental Studies in Selective Wet Etching and Corrosion Processes for High-Performance Semiconductor Devices. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6.

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