Journal articles: 'Wet chemical semiconductor etching processes'

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VOSHCHENKOV, ALEXANDER M. "FUNDAMENTALS OF PLASMA ETCHING FOR SILICON TECHNOLOGY (PART 1)." International Journal of High Speed Electronics and Systems 01, no. 03n04 (September 1990): 303–45. http://dx.doi.org/10.1142/s0129156490000149.

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Over the past decade, as the rapid evolution of semiconductor technology has progressed towards submicron design rules, plasma (dry) etching has supplanted simple wet etching processes for the transfer of patterns. To understand the underlying need for development of plasma etching, a brief background of integrated semiconductor technology is presented. Along with a historical perspective of the evolution of plasma etching, the relationship of plasma etching to lithography needs, its basic characteristics and advantages over wet chemical processing are discussed. Following this, relevant concepts of plasma physics and chemistry, based on experience with plasma etching applications for silicon technology, which can be used as building blocks for technology development are described.

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Saito, Suguru, Yoshiya Hagimoto, Hayato Iwamoto, and Yusuke Muraki. "Mechanism of Plasma-Less Gaseous Etching Process for Damaged Oxides from the Ion Implantation Process." Solid State Phenomena 145-146 (January 2009): 227–30. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.227.

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Recently, plasma-less gaseous etching processes have attracted attention for their interesting etching properties. Previously, we reported on the etching properties of theses processes for various kinds of oxides and revealed that they reduce the etch rate of the chemical-vapor-deposited (CVD) oxides more than the conventional wet etching process does [1]. Our results also revealed that depressions called divots in the CVD oxide of the shallow trench isolation (STI) became smaller in size by substituting a plasma-less gaseous etching process for the conventional wet etching process. In semiconductor manufacturing, many processes are used to remove oxides damaged during ion implantation or reactive ion etching on the device surface. Therefore, it is very important to understand the etching properties of plasma-less gaseous etching processes for damaged oxides as well as those for other kinds of oxides. In this report, we evaluate the etching properties of one particular plasma-less gaseous etching process for oxide films damaged during the ion implantation process under various conditions and discuss the mechanism of interesting etching properties for the damaged oxides.

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Patzig, Sebastian, Gerhard Roewer, Edwin Kroke, and Ingo över. "NOHSO4/HF – A Novel Etching System for Crystalline Silicon." Zeitschrift für Naturforschung B 62, no. 11 (November 1, 2007): 1411–21. http://dx.doi.org/10.1515/znb-2007-1110.

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Solutions consisting of HF - NOHSO4 - H2SO4 exhibit a strong reactivity towards crystalline silicon which is controlled by the concentrations of the reactive species HF and NO+. Selective isotropic and anisotropic wet chemical etching with these solutions allows to generate a wide range of silicon surface morphology patterns. Traces of Ag+ ions stimulate the reactivity and lead to the formation of planarized (polished) silicon surfaces. Analyses of the silicon surface, the etching solution and the gas phase were performed with scanning electron microscopy (SEM), DR/FT-IR (diffusive reflection Fourier transform infra-red), FT-IR, Raman and NMR spectroscopy, respectively. It was found that the resulting silicon surface is hydrogen-terminated. The gas phase contains predominantly SiF4, NO and N2O. Furthermore, NH4+ is produced in solution. The study has confirmed the crucial role of nitrosyl ions for isotropic wet chemical etching processes. The novel etching system is proposed as an effective new way for selective surface texturing of multi- and monocrystalline silicon. A high etching bath service lifetime, besides a low contamination of the etching solution with reaction products, provides ecological and economical advantages for the semiconductor and solar industry.

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Dolah, Asban, Muhammad Azmi Abd Hamid, Mohamad Deraman, Ashaari Yusof, Nor Azhadi Ngah, and Norman Fadhil Idham Muhammad. "Ohmic Contact in P-HEMT Wafer Using Metallization with Ge/Au/Ni/Au." Advanced Materials Research 896 (February 2014): 351–53. http://dx.doi.org/10.4028/www.scientific.net/amr.896.351.

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In this study, Ohmic contact were fabricated on AlGaAs HEMTs structure. A good metal-semiconductor interface are essentially for achieving lower specific contact resistance. An AlGaAs epi wafer was supply by the vendor. AlGaAs substrate was cleaned using wet chemical etching. Electrodes were fabricated through a sequenced of lithography, cleaning, sputtering and lift-off processes. The electrodes were made with metal layers of Ge, Au and Ni. Parameters such as metal thickness, annealing temperatures (from 300°C to 400°C) and annealing time were varies during fabrication process. Electrical characterizations after annealing are carried out using transmission line method (TLM) to obtain the specific contact resistance. Annealing temperature between 340°C to 360°C produced contact resistance below 5 x 10ˉ³Ω/cm-2.

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PEARTON, S. J. "HYDROGEN IN CRYSTALLINE SEMICONDUCTORS: PART II–III–V COMPOUNDS." International Journal of Modern Physics B 08, no. 10 (April 30, 1994): 1247–342. http://dx.doi.org/10.1142/s0217979294000592.

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The properties of hydrogen in III–V semiconductors are reviewed. Atomic hydrogen is found to passivate the electrical activity of shallow donor and acceptor dopants in virtually all III–V materials, including GaAs, Alx Ga1−x As, InP, InGaAs, GaP, InAs, GaSb, InGaP, AlInAs and AlGaAsSb. The passivation is due to the formation of neutral dopant-hydrogen complexes, with hydrogen occupying a bond-centered position in p-type semiconductors and an anti-bonding site in n-type materials. The dopants are reactivated by annealing at ≤400° C. The neutral hydrogen-dopant complexes have characteristic vibrational bands, around 2000cm−1 for stretching modes and 800cm−1 for wagging modes. Deep levels such as EL2, DX and metallic impurities are also passivated by hydrogen. The diffusivity of hydrogen is high in III–V semiconductors and unintentional incorporation can occur during epitaxial growth, annealing in H2, dry etching, water boiling, wet etching or chemical vapor deposition processes, Surface passivation by (NH4)xS or NH3 plasma treatment is also effective in lowering surface recombination velocities in many III-V semiconductors.

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Zhang, Zhi Yu, Xu Yang, and Li Gong Zheng. "Fabrication of Computer Generated Hologram for Aspheric Surface Measurement." Advanced Materials Research 1136 (January 2016): 620–23. http://dx.doi.org/10.4028/www.scientific.net/amr.1136.620.

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High-precision aspheric surfaces are generally measured using interferometer with a computer-generated holograms (CGH), which has a wavy line pattern fabricated onto a glass substrate. CGH patterns are generally made using lithographic techniques that was developed for semiconductor industry. Patterns can be subsequently etched into glass substrate using reactive ion or chemical etching. The accuracy of the drawn pattern on a CGH decides the accuracy of the measurement. Draw pattern error mainly includes the line-width deviation and its position error. In this paper, the influences of defocus of drawing laser and the wet-etching processes on the line-width were firstly investigated. On the other hand, the position error under different line-width was obtained by analyzing the relationship of line-width error and the position error. Based on the above-obtained results, a CGH having a diameter of 80 mm and the minimum line-width of 1.8 μm was successfully fabricated. Testing results showed that the wavefront error was only 3.79 nm, significantly higher than the commercial-available ones. The fabricated CGH is expected to use in the high-precision measurement of asphercal surfaces.

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Choi, Geun Min. "Necessity of Cleaning and its Application in Future Memory Devices." Solid State Phenomena 219 (September 2014): 3–10. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.3.

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Concerning the processes of the semiconductor industry, device integration is increasing and cell structure is becoming more complicated, which brings many new kinds of challenges. The basic requirements for a future integration device are minimum feature size reduction with device integration and high-speed operation with sufficient cell capacitance. Many kinds of conventional films including electrode and dielectric materials should be altered to meet device requirements. Moreover, as the allowance level for contaminants on substrate surfaces becomes more stringent, the importance of removing them becomes even greater. Because of this, the semiconductor process for high quality device fabrication will never be realized without perfect cleaning on all surfaces. It is reported that the conventional cleaning solutions such as a NH4OH/H2O2/H2O (SC-1) solution (1:4:20, 80 °C), H2SO4/H2O2 (SPM) solution (4:1, 90 to 120°C), and HCl/H2O2/H2O (HPM) solution (1:1:6, 80 to 90°C) are not compatible with metal film exposed surfaces with very tiny patterns, due to the fast etching rate of metal films [1] . In 1995, at the base of the mechanism of the removal of the adhered contaminants such as metallic impurities, particles and organics, T. Ohmi proposed a total room temperature wet cleaning process (so called “UCT cleaning”) [2]. As a result of the continuous research on developed cleaning, the five steps process was revised to a four step room temperature wet cleaning for real device cleaning. The cleaning consists of 1) CO2 added O3-UPW cleaning for removing organic and metallic impurities, 2) NH3 added H2-UPW+MS cleaning for removing of particles, 3) HF/H2O2(FPM) cleaning for removing metallic impurities, and 4) H2-UPW+MS rinse for the removal of chemical residues, prevention of particle re-adhesion, suppression of native oxide growth, and enhancement of H-termination.

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Collins, George, and Donald J. Rej. "Plasma Processing of Advanced Materials." MRS Bulletin 21, no. 8 (August 1996): 26–31. http://dx.doi.org/10.1557/s0883769400035673.

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A plasma, commonly referred to as the “fourth state of matter,” is an ensemble of randomly moving charged particles with a sufficient particle density to remain, on average, electrically neutral. While their scientific study dates from the 19th century, plasmas are ubiquitous, comprising more than 99% of the known material universe. The term “plasma” was first coined in the 1920s by Irving Langmuir at the General Electric Company after the vague resemblance of a filamented glow discharge to a biological plasma.Plasmas are studied for many reasons. Physicists analyze the collective dynamics of ions and electron ensembles, utilizing principals of classical electromagnetics, and fluid and statistical mechanics, to better understand astrophysical, solar, and ionospheric phenomenon, and in applied problems such as thermonuclear fusion. Electrical engineers use plasmas to develop efficient lighting, and high-power electrical switchgear, and for magneto-hydrodynamic (MHD) power conversion. Aerospace engineers apply plasmas for attitude adjustment and electric propulsion of satellites. Chemists, chemical engineers, and materials scientists routinely use plasmas in reactive ion etching and sputter deposition. These methods are commonplace in microelec tronics since they allow synthesis of complex material structures with submicron feature sizes. A substantial portion of the multi-billion-dollar market for tooling used to manufacture semiconductors employs some form of plasma process. When compared with traditional wet-chemistry techniques, these dry processes result in minimal waste generation. Plasmas are also useful in bulk processing—for example as thermal sprays for melting materials.While the quest for controlled thermonuclear fusion dominated much of plasma research in the 1960s and 1970s, in the last 20 years it has been the application of plasmas to materials processing that has provided new challenges for many plasma practitioners. It is not surprising that the guest editors and several of the authors for this issue of MRS Bulletin come from a fusion plasma-physics background.

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Causier, Alexandre, Isabelle Gérard, Muriel Bouttemy, Pierre Tran-Van, and Arnaud Etcheberry. "Fundamentals of III-V Semiconductor Electrochemistry and Wet Etching Processes: Br2 Etching Properties onto InP." ECS Transactions 35, no. 8 (December 16, 2019): 61–66. http://dx.doi.org/10.1149/1.3567737.

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Ikossi‐Anastasiou, K., S. C. Binari, G. Kelner, J. B. Boos, C. S. Kyono, J. Mittereder, and G. L. Griffin. "Wet Chemical Etching with Lactic Acid Solutions for InP ‐ based Semiconductor Devices." Journal of The Electrochemical Society 142, no. 10 (October 1, 1995): 3558–64. http://dx.doi.org/10.1149/1.2050022.

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Philipsen, Harold, Nils Mouwen, Sander Teck, Wouter Monnens, Quoc Toan Le, Frank Holsteyns, and Herbert Struyf. "Wet-chemical etching of metals for advanced semiconductor technology nodes: Ru etching in acidic Ce4+ solutions." Electrochimica Acta 306 (May 2019): 285–98. http://dx.doi.org/10.1016/j.electacta.2019.03.065.

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Urisu, Tsuneo, Hakaru Kyuragi, Yuichi Utsumi, Jun‐ichi Takahashi, and Mamoru Kitamura. "Synchrotron radiation stimulated semiconductor processes: Chemical vapor deposition and etching." Review of Scientific Instruments 60, no. 7 (July 1989): 2157–59. http://dx.doi.org/10.1063/1.1140807.

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Alani, R., R. J. Mitro, and K. Ogura. "Reactive Ion Beam Etching (RIBE) Technique and Instrumentation for SEM Specimen Preparation of Semiconductors." Microscopy and Microanalysis 5, S2 (August 1999): 912–13. http://dx.doi.org/10.1017/s1431927600017888.

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Argon ion beam etching has established itself as an alternative technique to “wet chemical” etching for the preparation of cross sectional SEM specimens of semiconductors [1]. Complementing this technique, we are reporting the results of an iodine RIBE method for improved etching/cleaning capabilities with a measurable increase in etching rates as compared to argon ion beam etching. RIBE systems have been used for decades in the semiconductor research/industry for wafer processing, patterning and surface cleaning. This same technique has also been used for high quality TEM specimen preparation of certain semiconductor materials [2,3]. The beneficial aspects of the iodide RIBE technique for surface etching for a variety of semiconductor structures along with the related instrumentation will be discussed. The semiconductor specimens include traditional ICs and more advanced copper technology devices.The design and construction of the original system used in this work has already been reported [4].

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Litz-Montanaro, Lisa. "The Art of Tungsten Etching in Semiconductor Chips." Microscopy Today 7, no. 2 (March 1999): 24–25. http://dx.doi.org/10.1017/s1551929500063902.

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In the course of both physical and failure analysis of semiconductor chips (i.e., verifying what you actually deposited as a layer, vs, what caused the circuit to fail), it is essential to have appropriate deprocessing tools at your disposal in order to evaluate complex semiconductor structures, Deprocessing techniques are developed for each product manufactured and involve multi-step procedures that reveal the layer-by-layer secrets of the chip, These techniques require constant tweaking in duration and procedure as the manufacturing process imposes changes and as the architecture of the semiconductor changes. While there are many tools that assist in these analytical pursuits, such as RIE (reactive ion etching - a dry etching technique), ion milling, and microcleaving, the wet chemical etching of tungsten is sometimes more reproducible than RIE techniques.

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Lim, Ee Leong, Jing Hua Teng, Soo Jin Chua, J. R. Dong, Norman Soo Seng Ang, and Lip Fah Chong. "Novel Passivation Method in the Fabrication of Submicron InGaAsP/InP Ridge Waveguide Lasers." Advanced Materials Research 31 (November 2007): 30–32. http://dx.doi.org/10.4028/www.scientific.net/amr.31.30.

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One challenge for the realization of electrically drive nano-photonic devices is the formation of metal contacts and passivation. In this paper, we report a novel self-aligned method suitable for the formation of the metal contact and passivation for submicron photonic devices. Two different dielectric materials with high selectivity in wet chemical etching and a wet etching of semiconductor to create an undercut are involved. The whole process is completely compatible with existing compound semiconductor process. As a demonstration of this method, the fabrication and characterization of an InGaAsP/InP submicron-ridge waveguide lasers is presented. The method is extendable to high aspect ratio-submicron ridge waveguide and other device fabrication.

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Ueda, Dai, Yousuke Hanawa, Hiroaki Kitagawa, Naozumi Fujiwara, Masayuki Otsuji, Hiroaki Takahashi, and Kazuhiro Fukami. "Effect of Hydrophobicity and Surface Potential of Silicon on SiO₂ Etching in Nanometer-Sized Narrow Spaces." Solid State Phenomena 314 (February 2021): 155–60. http://dx.doi.org/10.4028/www.scientific.net/ssp.314.155.

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Wet etching in nanometer-sized three-dimensional spaces creates new challengesbecause of the scaling of semiconductor devices with complex 3D architecture. Wet etching withinspaces is affected by the mass transport of the etchant ions that are impacted by the hydrophobicityand surface potential of surface. However, the kinetics of chemical reactions within the spaces is stillunclear.In this paper, we studied the effect of hydrophobicity and surface potential of silicon surface on SiO2etching in nanometer-sized narrow spaces by adding various additive components to etching solutions.We found that the transport of etchant ions into narrow spaces is governed by controlling thehydrophobicity and surface potential of the confined system walls.

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Edwards, Stephanie, Ryan Persons, Steve Feltham, Jeff Howerton, Geoffrey Lott, and Daniel Macko. "Laser Etching of Gold Conductors for RF Applications." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000373–80. http://dx.doi.org/10.4071/2380-4505-2019.1.000373.

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Abstract Thick film customers who require fine line resolution for their circuitry typically utilize wet chemical etching as a means to reduce conductor's lines and spaces when fine line definition cannot be reliably attained with screen printing alone. Wet chemical etching typically has the means to reduce conductor line widths from a printed definition of 3 mil (75 μm) to as low as 1 mil (25 μm) lines and spaces. The process of performing this chemical etching is time consuming and costly when factoring in the necessary process limitations. With the issues presented by wet chemical etching, thick film customers are presented with a high process cost, yield loss due to the imaging process, and costly wastewater/environmental treatment regulations. Therefore, laser etching will be presented as an alternative method to wet chemical etching for various thick film conductor products. For many years, specialized gold formulations have been etched using typical wet chemical etching processes. Standard and less costly conductor alloys that typically would not be suitable for wet chemical etching will be explored, possibly opening the doors for a wide variety of different applications which would benefit from utilizing this laser etching method. By being able to utilize different conductor alloys (Ag, Cu, etc.), laser etching offers alternative solutions for some of these applications with the added benefit of improved cost and increased throughput. As an example, wet chemical processing of silver conductors has proven to be very challenging in some cases due to the metal form-factor and specialized glasses required. By having the option of laser ablating the silver, a potentially advantageous and cost-effective option would now be possible. Taking into account that laser etching of thick film conductors on ceramic is a relatively new method, this paper will concentrate on some of the opportunities/advantages it can offer. It will illustrate the boundaries of laser etching and how it compares to wet chemical etching while determining/comparing the impact on several properties including adhesion, signal propagation, line definition, and other important defining characteristics of the fired film in the final application.

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Çakır, Orhan. "Review of Etchants for Copper and its Alloys in Wet Etching Processes." Key Engineering Materials 364-366 (December 2007): 460–65. http://dx.doi.org/10.4028/www.scientific.net/kem.364-366.460.

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Wet etching processes have been widely used for producing micro-components for various applications. These processes are simple and easy to implement. The selection of suitable chemical solution which is called etchant is the most important factor in the wet etching processes. It affects etch rate and surface finish quality. Copper and its alloys are important commercial materials in various industries, especially in electronics industry. Their wide applications are due to their excellent electrical and thermal conductivity, ease of fabrication, good strength and fatigue properties. The present study examines the possible etchants for copper and its alloys and reviews studies in detail to find out optimum etchant and its application parameters. The study is also aimed to provide information about safety, health and environmental issues caused by using various etchants in wet etching processes of copper and copper alloys.

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Radjenovic, Branislav, and Marija Radmilovic-Radjenovic. "Level set simulations of the anisotropic wet etching process for device fabrication in nanotechnologies." Chemical Industry 64, no. 2 (2010): 93–97. http://dx.doi.org/10.2298/hemind100205008r.

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Chemical etching is employed as micromachining manufacturing process to produce micron-size components. As a semiconductor wafer is extremely expensive due to many processing steps involved in the making thereof, the need to critically control the etching end point in an etching process is highly desirable. It was found that not only the etchant and temperature determine the exact anisotropy of etched silicon. The angle between the silicon surface and the mask was also shown to play an important role. In this paper, angular dependence of the etching rate is calculated on the base of the silicon symmetry properties, by means of the interpolation technique using experimentally obtained values of the principal <100>, <110>, <111> directions in KOH solutions. The calculations are performed using an extension of the sparse field method for solving three dimensional (3D) level set equations that describe the morphological surface evolution during etching process. The analysis of the obtained results confirm that regardless of the initial shape the profile evolution ends with the crystal form composed of the fastest etching planes, {110} in our model.

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Melkonyan, D., C. Fleischmann, A. Veloso, A. Franquet, J. Bogdanowicz, R. J. H. Morris, and W. Vandervorst. "Wet-chemical etching of atom probe tips for artefact free analyses of nanoscaled semiconductor structures." Ultramicroscopy 186 (March 2018): 1–8. http://dx.doi.org/10.1016/j.ultramic.2017.12.009.

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Galaly, Ahmed Rida, Farouk Fahmy Elakshar, and Mohamed Atta Khedr. "Study of the Etching Processes of Si [1 0 0] Wafer Using Ultra Low Frequency Plasma." Materials Science Forum 756 (May 2013): 143–50. http://dx.doi.org/10.4028/www.scientific.net/msf.756.143.

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The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely the wet chemical etching method, using HNO3-HF-CH3COOH solution, and the Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching using inert gas only (e.g., argon gas), and ion chemical etching using an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning microscope (OSM) and Joel Scanning microscope (JSM). The formed hole width (ω) increases by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about ( 0.0707 and 0.0537 µm/min ) .Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. Normal 0 21 false false false MS X-NONE X-NONE The etching processes of Si [1 0 0] wafer have been studied using two different methods; namely wet chemical etching method, using HNO3-HF-CH3COOH solution, and Ultra Low Frequency Plasma (ULFP) method at (1KHz). Ion etching used inert gas only (e.g., argon gas) while ion chemical etching used an active gas (beside the inert gas) such as oxygen techniques were used. Calculations of the different parameters produced by chemical etching and plasma etching for silicon wafer (sample) such as ( hole depth, hole width and etching rate) were investigated using the images of Optical Scanning Microscope (OSM) and Joel Scanning Microscope (JSM). The formed hole width (ω) increased by increasing the exposure time of the sample in the different types of etching. Values of the hole width were in the range of 2- 7 µm during exposure times of (30 to 100 min). The sample growth exponent constant was about (0.0707 and 0.0537 µm/ min). Hole has depths in the range of( 0.5 to 3 µm) in time of (30 to 100 min).The average distances between the holes were decreased by increasing the exposure time from (14 to 4 µm) in the time range of (30 – 100 min). The rates of etching were ranged from (0.0226 to 0.0448 µm/ min) either for dry or wet etching. /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

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VOSHCHENKOV, A. M. "PLASMA ETCHING PROCESSES FOR GIGAHERTZ SILICON INTEGRATED CIRCUITS (Part 2)." International Journal of High Speed Electronics and Systems 02, no. 01n02 (March 1991): 45–88. http://dx.doi.org/10.1142/s0129156491000041.

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In the preceding paper of this series, “Fundamentals of plasma etching for silicon technology (Part 1)”,1 a historical perspective of the evolution of plasma etching, its relationship to lithography needs, basic characteristics of plasma etching, advantages over wet chemical processing, and a practical viewpoint of the underlying fundamental concepts of plasma physics and chemistry were presented. In this paper, original work in plasma etcher design and a variety of process applications to multigigahertz rate silicon technology as practiced in Bell Laboratories, Holmdel, are described.

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Ogura, K., and R. Alani. "A new approach for Cross-Sectioning Sem Specimens of Semiconductors by Broad-Ion Beam Milling." Microscopy and Microanalysis 4, S2 (July 1998): 864–65. http://dx.doi.org/10.1017/s1431927600024442.

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The cross-sectioning of semiconductor wafers for SEM studies has traditionally been carried out by tedious and laborious mechanical grinding and polishing techniques. The mechanically polished surfaces are treated using a “wet chemical” etching method to enhance and delineate certain features or layers in a given specimen. The etched specimens are then coated by conductive layers to prevent charging during SEM examination. As an alternative to “wet chemical etching”, broad-ion beam etching techniques have been developed for surface treatment of mechanically polished specimens. More specifically, we have reported [1] the utilization of a combined process of broad-ion beam etching and coating of mechanically cross sectioned semiconductors in a single vacuum chamber. As a further progress to that work, we report a rapid and reliable technique for preparing precision SEM cross sections. The technique is based on perpendicular broad-ion beam milling of cleaved wafers to expose any desired cross-section through a given feature of the specimen.

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Rath, P., J. C. Chai, H. Zheng, Y. C. Lam, and V. M. Murukeshan. "Total concentration approach for three-dimensional diffusion-controlled wet chemical etching." International Journal of Heat and Mass Transfer 49, no. 19-20 (September 2006): 3408–16. http://dx.doi.org/10.1016/j.ijheatmasstransfer.2006.02.053.

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Rajesh, K., L. J. Huang, W. M. Lau, R. Bruce, S. Ingrey, and D. Landheer. "Modification of the GalnAsP(100) surface by oxidation and sulfur passivation." Canadian Journal of Physics 74, S1 (December 1, 1996): 89–94. http://dx.doi.org/10.1139/p96-839.

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The quaternary III–V compound semiconductor (GaInAsP) is one of the important materials for optoelectronic devices such as long-wavelength semiconductor lasers. Understanding its surface chemistry, which is subjected to oxidation, and sulphur passivation, a widely used passivation technique, is of importance for its use for device fabrication. In this study, modification of the quaternary GaInAsP(100) surfaces was performed by UV/ozone and wet chemical oxidation, dilute HF etching, and sulfur passivation. The surface chemistry and composition of the oxidized, oxide-free, and the sulfur-passivated surfaces were measured by X-ray photoemission spectroscopy (XPS). It was found that oxidation by wet chemical etching resulted in preferential oxidation while, oxidation by ozone exposure formed multiple oxide phases of all the constituent elements. Both the HF etch and sulfur-passivation treatment were effective in generating surfaces having no oxide. Preliminary data on surface Fermi-level changes induced by the above surface treatments indicated that both the HF etch and sulfur-passivation treatment reduced the surface-state density on an oxidized surface.

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Ide, T., M. Shimizu, A. Suzuki, X. Q. Shen, H. Okumura, and T. Nemoto. "AlN/GaN Metal Insulator Semiconductor Field Effect Transistor Using Wet Chemical Etching with Hot Phosphoric Acid." physica status solidi (a) 188, no. 1 (November 2001): 351–54. http://dx.doi.org/10.1002/1521-396x(200111)188:1<351::aid-pssa351>3.0.co;2-x.

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Wada, Masayuki, Kenichi Sano, James Snow, Rita Vos, L. H. A. Leunissens, Paul W. Mertens, and Atsuro Eitoku. "All Wet Photoresist Strip by Solvent Aerosol Spray." Solid State Phenomena 145-146 (January 2009): 285–88. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.285.

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The introduction of metal gates and high-k dielectrics in FEOL and porous ULK dielectrics in BEOL presents severe issues [1] and leads to the requirement of new chemistries and processes. A major challenge in cleaning is the removal of photoresist (PR) in both FEOL and BEOL. In current semiconductor device fabrication flow, the photoresist strip process in FEOL is mostly achieved by applying a sequence of plasma ashing followed by a wet-clean step with sulfuric-peroxide mixture (SPM). But in general, ashing leads to strong oxidation or etching of silicon substrate. Hence, several approaches for ashless PR strip have been reported, such as hot SPM [2] and the combination of a pre-treatment using high velocity CO2 aerosol [3].

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Lim, Sang Woo. "Toward the Surface Preparation of InGaAs for the Future CMOS Integration." Solid State Phenomena 282 (August 2018): 39–42. http://dx.doi.org/10.4028/www.scientific.net/ssp.282.39.

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The integration of III-V and Ge materials on Si surface causes many issues with complexity such as lattice mismatch with silicon. In particular, the surface preparation and passivation of InGaAs is very challenging, because the formation of InGaAs/high-K interface is important, but not well understood. For the systematical study of InGaAs surface during wet processes, the effect of various wet etching processes on the surfaces of binary III-V compound semiconductors (GaAs, InAs, GaSb and InSb) was studied from the viewpoints of surface oxidation, material loss (dissolution), and passivation. Based on that, further effort to understand the surface reactions on ternary InGaAs compound semiconductor was made. In addition, process sequential effect on the InGaAs surface was investigated.

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Kumagai, Masami, Kiyoyuki Yokoyama, and Satoshi Tazawa. "A Compound Semiconductor Process Simulator and its Application to Mask Dependent Undercut Etching." VLSI Design 6, no. 1-4 (January 1, 1998): 393–97. http://dx.doi.org/10.1155/1998/65787.

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This paper describes a process simulator that is designed to describe the etching and deposition processes used in constructing compound semiconductors, which have at least two different atomic species. This nature dictates a very different response to compound semiconductor process from the silicon process. One of the most remarkable processes in compound semiconductors is the reverse-mesa formation. This simulator successfully represents the mesa and the reverse mesa profiles that are often observed after chemical etching. The mask material dependence of the undercut etching can also be simulated with a good agreement between the experimental and the simulated shapes.

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CHOI, S. S., M. Y. JUNG, J. W. KIM, J. H. BOO, and J. S. YANG. "FABRICATION OF NEARFIELD OPTICAL PROBE ARRAY USING VARIOUS NANOFABRICATION PROCEDURES." International Journal of Nanoscience 02, no. 04n05 (August 2003): 283–91. http://dx.doi.org/10.1142/s0219581x03001309.

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The nanosize silicon oxide aperture on the cantilever array has been successfully fabricated as nearfield optical probe. The various semiconductor processes were utilized for subwavelength size aperture fabrication. The anisotropic etching of the Si substrate by alkaline solutions followed by anisotropic crystal orientation dependent oxidation, anisotropic plasma etching, isotropic oxide etching was carried out. The 3 and 4 micron size dot array were patterned on the Si(100) wafer. After fabrication of the V-groove shape by anisotropic TMAH etching, the oxide growth at 1000° C was performed to have an oxide etch-mask. The oxide layer on the Si(111) plane have been utilized as an etch mask for plasma dry etching and water-diluted HF wet etching for nanosize aperture fabrication. The Au thin layer was deposited on the fabricated oxide nanosize aperture on the cantilever array. The 160 nm metal apertures on (5×1) cantilever array were successfully fabricated using electron beam evaporator.

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31

Hvozdiyevskyy, E. E., Z. F. Tomashik, V. M. Tomashyk, and R. O. Denysyuk. "Chemical Treatment of CdTe and Solid Solution ZnxCd1-xTe and Cd0,2Hg0,8Te and Aqueous Solutions of HNO3–НІ-Lactate Acid." Фізика і хімія твердого тіла 17, no. 2 (June 15, 2016): 247–50. http://dx.doi.org/10.15330/pcss.17.2.247-250.

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The method of disk rotating kinetics of dissolution processes CdTe, ZnxCd1-xTe and Cd0,2Hg0,8Te in yodvydilyayuchyh etching compositions HNO3-NO-lactate acid. The dependence of etching rate of said material concentration oxidizer and organic solvent. Optimized polishing compositions herbalists and modes chemical dynamic polishing of semiconductor materials studied. The influence of Zn and Hg content in the composition of solid solutions on the quality of the resulting surface etching mixtures.

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32

Rath, P., J. C. Chai, H. Zheng, Y. C. Lam, V. M. Murukeshan, and H. Zhu. "A fixed-grid approach for diffusion- and reaction-controlled wet chemical etching." International Journal of Heat and Mass Transfer 48, no. 11 (May 2005): 2140–49. http://dx.doi.org/10.1016/j.ijheatmasstransfer.2004.12.033.

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Hung, Yung-Jr, San-Liang Lee, Kai-Chung Wu, Yian Tai, and Yen-Ting Pan. "Antireflective silicon surface with vertical-aligned silicon nanowires realized by simple wet chemical etching processes." Optics Express 19, no. 17 (August 3, 2011): 15792. http://dx.doi.org/10.1364/oe.19.015792.

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Jang, Hyun-Ik, Hae-Su Yoon, Tae-Ik Lee, Sangmin Lee, Taek-Soo Kim, Jaesool Shim, and Jae Hong Park. "Creation of Curved Nanostructures Using Soft-Materials-Derived Lithography." Nanomaterials 10, no. 12 (December 3, 2020): 2414. http://dx.doi.org/10.3390/nano10122414.

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In this study, curved nanostructures, which are difficult to obtain, were created on an Si substrate through the bonding, swelling, and breaking processes of the polymer and silicone substrate. This method can be utilized to obtain convex nanostructures over large areas. The method is simpler than typical semiconductor processing with photolithography or compared to wet- or vacuum-based dry etching processes. The polymer bonding, swelling (or no swelling), and breaking processes that are performed in this process were theoretically analyzed through a numerical analysis of permeability and modeling. Through this process, we designed a convex nanostructure that can be produced experimentally in an accurate manner.

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Tang, Chao Wei, Shih Chieh Tseng, Hong Tsu Young, Kuan Ming Li, Mike Yang, and Hsueh Chuan Liao. "Enhancement of through Silicon via Sidewall Quality by Nanosecond Laser Pulses with Chemical Etching Process." Advanced Materials Research 579 (October 2012): 3–9. http://dx.doi.org/10.4028/www.scientific.net/amr.579.3.

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Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system in package, and wafer level packaging applications. In this study, a wet chemical etching (WCE) process has been employed to enhance the sidewall quality of TSVs fabricated using nanosecond (ns) laser pulses. Experimental results show that the TSV sidewall roughness can be markedly reduced, from micrometer scale to nanometer scale. We concluded that the proposed method would enable semiconductor manufactures to use ns laser drilling for industrial TSV fabrication as the desired TSV sidewall quality can be achieved by incorporating the WCE process, which is suitable for mass production.

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PARK, W. B., J. H. CHOI, C. W. PARK, G. M. KIM, H. S. SHIN, C. N. CHU, and B. H. KIM. "FABRICATION OF MICRO PROBE-TYPE ELECTRODES FOR MICROELECTRO-CHEMICAL MACHINING USING MICROFABRICATION." International Journal of Modern Physics B 24, no. 15n16 (June 30, 2010): 2639–44. http://dx.doi.org/10.1142/s0217979210065398.

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In this study, the mass fabrication of microelectrode tools for microelectrochemical machining (MECM) was studied using microfabrication processes. The cantilever type geometry of microelectrodes was defined by photolithography processes, and metal patterns were made for electrical contacts. Various fabrication processes were studied for the fabrication of microelectrode tools, such as wet etching, lift-off, and electroforming for metal layer patterning. MECM test results showed feasibility of the fabricated electrode tools. The microfabricated electrodes can be used as micromachining tools for various electrical micromachining of steel mold and parts of microdevices.

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Hwang, Guang Yaw, J. H. Liao, S. F. Tzou, Mark Lin, Autumn Yeh, David Lou, Eason Chen, et al. "A Hybrid Dry-Wet Approach for Removal of a Dummy Polysilicon Gate in a Replacement Metal Gate Scheme." Solid State Phenomena 187 (April 2012): 57–60. http://dx.doi.org/10.4028/www.scientific.net/ssp.187.57.

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Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.

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Rath, P., J. C. Chai, H. Zheng, Y. C. Lam, and V. M. Murukeshan. "Modeling two-dimensional diffusion-controlled wet chemical etching using a total concentration approach." International Journal of Heat and Mass Transfer 49, no. 7-8 (April 2006): 1480–88. http://dx.doi.org/10.1016/j.ijheatmasstransfer.2005.09.021.

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Park, Jongsung, and Nochang Park. "Wet etching processes for recycling crystalline silicon solar cells from end-of-life photovoltaic modules." RSC Adv. 4, no. 66 (2014): 34823–29. http://dx.doi.org/10.1039/c4ra03895a.

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Ide, Toshihide, Mitsuaki Shimizu, Akira Suzuki, Xu-Qiang Shen, Hajime Okumura, and Toshio Nemoto. "Advantages of AlN/GaN Metal Insulator Semiconductor Field Effect Transistor using Wet Chemical Etching with Hot Phosphoric Acid." Japanese Journal of Applied Physics 40, Part 1, No. 8 (August 15, 2001): 4785–88. http://dx.doi.org/10.1143/jjap.40.4785.

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Muranaka, Tsutomu, Suguru Iizuka, Masao Hishikawa, Kazuki Kodama, Kenta Ohmori, Yoichi Nabetani, and Takashi Matsumoto. "Structural and optical properties of ZnSe-based diluted magnetic semiconductor quantum-well wire arrays by wet chemical etching." physica status solidi (c) 7, no. 6 (April 14, 2010): 1648–50. http://dx.doi.org/10.1002/pssc.200983199.

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Shang, Zheng Guo, Zhi Yu Wen, Dong Ling Li, and Sheng Qiang Wang. "Application of KOH Anisotropic Etching in the Fabrication of MEMS Devices." Key Engineering Materials 483 (June 2011): 62–65. http://dx.doi.org/10.4028/www.scientific.net/kem.483.62.

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It is known that the wet chemical etching of silicon in alkaline solution has attracted wide attention due to its advantages such as lower cost, simpler setup, higher rate, smoother surface at micro level, higher degree of anisotropy, and lower pollution. In this paper, the key processes of fabricating vacuum microelectronic accelerometer and slits are presented. The cone curvature radius of the silicon tip arrays less than 30nm was fabricated with wet anisotropic etching of silicon in 33wt. % KOH solution at 70°C added potassium iodine (KI) and Iodine (I2) as additive and the cone aspect ratio was about 0.7. Smooth surface after etching in 33wt. %KOH solution added isopropyl alcohol (IPA) at 80°C was obtained and lateral etching was less than 5um after etching several hours for etching depth over 400um. Scalar slits with bottom width 25um and depth 500um were attained. A constant etch rate lead to precise and reproducible production. The test result reveals that the process to a specific occasion can reach practical requirements.

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Abdur-Rahman, Eyad, Ibrahim Alghoraibi, and Hassan Alkurdi. "Effect of Isopropyl Alcohol Concentration and Etching Time on Wet Chemical Anisotropic Etching of Low-Resistivity Crystalline Silicon Wafer." International Journal of Analytical Chemistry 2017 (2017): 1–9. http://dx.doi.org/10.1155/2017/7542870.

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A micropyramid structure was formed on the surface of a monocrystalline silicon wafer (100) using a wet chemical anisotropic etching technique. The main objective was to evaluate the performance of the etchant based on the silicon surface reflectance. Different isopropyl alcohol (IPA) volume concentrations (2, 4, 6, 8, and 10%) and different etching times (10, 20, 30, 40, and 50 min) were selected to study the total reflectance of silicon wafers. The other parameters such as NaOH concentration (12% wt.), the temperature of the solution (81.5°C), and range of stirrer speeds (400 rpm) were kept constant for all processes. The surface morphology of the wafer was analyzed by optical microscopy and atomic force microscopy (AFM). The AFM images confirmed a well-uniform pyramidal structure with various average pyramid sizes ranging from 1 to 1.6 μm. A UV-Vis spectrophotometer with integrating sphere was used to obtain the total reflectivity. The textured silicon wafers show high absorbance in the visible region. The optimum texture-etching parameters were found to be 4–6% vol. IPA and 40 min at which the average total reflectance of the silicon wafer was reduced to 11.22%.

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Peng, Deng-Jr, Yih-Shing Duh, and Chi-Min Shu. "Wet bench reactive hazards of cleaning stages in semiconductor manufacturing processes." Journal of Loss Prevention in the Process Industries 19, no. 6 (November 2006): 743–53. http://dx.doi.org/10.1016/j.jlp.2006.06.002.

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45

Banhart, F., F. O. Phillipp, R. Bergmann, E. Czech, M. Konuma, and E. Bauser. "Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study." Proceedings, annual meeting, Electron Microscopy Society of America 48, no. 4 (August 1990): 566–67. http://dx.doi.org/10.1017/s042482010017596x.

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Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

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Haslinger, Michael, M. Soha, S. Robert, M. Claes, Paul W. Mertens, and J. John. "‘Just-Clean-Enough’: Optimization of Wet Chemical Cleaning Processes for Crystalline Silicon Solar Cells." Solid State Phenomena 255 (September 2016): 344–47. http://dx.doi.org/10.4028/www.scientific.net/ssp.255.344.

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Advanced concepts for photovoltaic silicon solar cells, especially high-efficiency n-type solar cells, requires appropriate wet cleaning treatment in order to remove metallic contamination prior to high temperature processes like diffusion and passivation [1]. The cost of the cleaning process should be as low as possible that requires an optimized usage of the chemicals by increasing process tank lifetimes and developing dedicated feed and bleed recipes. The just clean enough concept has been developed to fulfil the needs of PV industry to minimize the consumption of chemicals. When the dominant contamination metal is identified in quality and quantity, a dedicated wet chemical cleaning process can be applied to remove the metal concentration from the semiconductor surface under a specified limit with the minimum volume on cleaning solution. The paper describes how to optimize a dedicated wet cleaning process for prominent metal impurities like Fe, Cu, Cr, Ti, Co and Zn. For each metal an exchange volume is determined to develop a feed and bleed recipe. The accumulation of the metal impurities in the process tank is calculated and process tank lifetimes are predicted.

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Panjan, Peter, Aljaž Drnovšek, Peter Gselman, Miha Čekada, and Matjaž Panjan. "Review of Growth Defects in Thin Films Prepared by PVD Techniques." Coatings 10, no. 5 (May 3, 2020): 447. http://dx.doi.org/10.3390/coatings10050447.

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The paper summarizes current knowledge of growth defects in physical vapor deposition (PVD) coatings. A detailed historical overview is followed by a description of the types and evolution of growth defects. Growth defects are microscopic imperfections in the coating microstructure. They are most commonly formed by overgrowing of the topographical imperfections (pits, asperities) on the substrate surface or the foreign particles of different origins (dust, debris, flakes). Such foreign particles are not only those that remain on the substrate surface after wet cleaning procedure, but also the ones that are generated during ion etching and deposition processes. Although the origin of seed particles from external pretreatment of substrate is similar to all PVD coatings, the influence of ion etching and deposition techniques is rather different. Therefore, special emphasis is given on the description of the processes that take place during ion etching of substrates and the deposition of coating. The effect of growth defects on the functional properties of PVD coatings is described in the last section. How defects affect the quality of optical coatings, thin layers for semiconductor devices, as well as wear, corrosion, and oxidation resistant coatings is explained. The effect of growth defects on the permeation and wettability of the coatings is also shortly described.

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Chiou, Chyow-San, Kai-Jen Chuang, Ya-Fen Lin, Hua-Wei Chen, and Chih-Ming Ma. "Application of Ozone Related Processes to Mineralize Tetramethyl Ammonium Hydroxide in Aqueous Solution." International Journal of Photoenergy 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/191742.

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Tetramethyl ammonium hydroxide (TMAH) is an anisotropic etchant used in the wet etching process of the semiconductor industry and is hard to degrade by biotreatments when it exists in wastewater. This study evaluated the performance of a system combined with ultraviolet, magnetic catalyst (SiO2/Fe3O4) andO3, denoted as UV/O3, to TMAH in an aqueous solution. The mineralization efficiency of TMAH under various conditions follows the sequence: UV/O3> UV/H2O2/O3>H2O2/SiO2/Fe3O4/O3>H2O2/O3>SiO2/Fe3O4/O3>O3> UV/H2O2. The results suggest that UV/O3process provides the best condition for the mineralization of TMAH (40 mg/L), resulting in 87.6% mineralization, at 60 min reaction time. Furthermore, the mineralization efficiency ofSiO2/Fe3O4/H2O2/O3was significantly higher than that ofO3,H2O2/O3, and UV/H2O2. More than 90% of the magnetic catalyst was recovered and easily redispersed in a solution for reuse.

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Sioncke, Sonja, David P. Brunco, Marc Meuris, Olivier Uwamahoro, Jan Van Steenbergen, Evi Vrancken, and Marc M. Heyns. "Etch Rate Study of Germanium, GaAs and InGaAs: A Challenge in Semiconductor Processing." Solid State Phenomena 145-146 (January 2009): 203–6. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.203.

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The Si transistor has dominated the semiconductor industry for decades. However, to fulfill the demands of Moore’s law, the Si transistor has been pushed to its physical limits. Introducing new materials with higher intrinsic carrier mobility is one way to solve this problem. Ge, GaAs and InGaAs are known for their high mobilities and are therefore suitable candidates for replacing Si as a channel material. However, introduction of new materials raises new issues. For Si processing, several steps such as cleaning, etching and stripping are based on wet treatments. The knowledge of etch rates of the semiconductor material is of great importance. In this paper, etch rates of Ge, GaAs and InGaAs in several chemical solutions are studied. A comparison of the etch rates is made between the materials.

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Hsu, Chia Jung, Chieh Ju Wang, Sheng Hung Tu, Makonnen Payne, Emanuel Cooper, and Steven Lippy. "High Throughput Wet Etch Solution for BEOL TiN Removal." Solid State Phenomena 255 (September 2016): 245–50. http://dx.doi.org/10.4028/www.scientific.net/ssp.255.245.

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Sub-10 nm technology node manufacturing processes may require the use of thicker and denser TiN hard mask for patterning at the BEOL. The modified TiN, which tends to be more chemically robust, must be removed using a wet etch process, while maintaining typical throughput - no extension of typical wet etch process times. To satisfy these needs, a new TiN etching accelerator was found that enhanced the activity of peroxide-related species in a wet etch chemical formulation that achieved increased TiN etch rate relative to formulation without TiN etch rate accelerator (Sample 1), while also minimizing the damage to ultra-low-k inter layer dielectric (ILD) layer by a strong base, also present in the formulation. We report here the result of a solvent based formulation, which adopted the TiN etching accelerator. The formulation was able to maintain TiN etch rate and remove post-etch residue, while remaining selective to ultra-low-k ILD, Co and Cu. The TiN etch rate of the accelerator enhanced formulation can be further tuned by modifying the process temperature or the hydrogen peroxide to formulation mixing ratio and has the potential capability to process > 400 wafers.

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Journal articles on the topic 'Wet chemical semiconductor etching processes'

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