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Dissertations / Theses on the topic 'Wireless communication systems Wireless communication systems Integrated circuits'
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1
Liu, Feng. "Lifetime maximization through adaptive power allocation in reconfigurable system design for wireless systems /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20LIU.
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Yang, Zhen. "Photonic integrated circuits for high speed sub-terahertz wireless communications." Thesis, University of Cambridge, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.708677.
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Beck, Sungho. "An interference-cancellation receiver for multi-band and multi-standard wireless communication systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44826.
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The dissertation presents novel methodologies to realize a multi-band and multi-standard receiver with an interference-cancellation capability. First, the receiver specifications are derived from the wireless communication standard. These specifications are then used to obtain the required amount of TX leakage cancellation by using a proposed frequency selective feedback topology with multi-band capability. The effectiveness of this technique is demonstrated by the measurement of prototype integrated circuit (IC). To make the IC operate for multi-standard, another novel technique is also proposed for a channel-selection filter. With a proposed interpolated resistor bank, the active-RC channel-selection filter has programmable gain and pseudo-continuous bandwidth, which reduce the total power consumption and silicon area of the receiver. The measured result of a prototype silicon chip shows the effectiveness of the technique. With these two topologies, a multi-band multi-standard receiver that uses low power can be realized at a cost.
4
Guo, Xiaoling. "CMOS intra-chip wireless clock distribution." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011427.
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Lo, Ernest Sze-Yuen. "Differential OFDM with iterative detection and signal space diversity for broadband wireless communication /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20LO.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.Includes bibliographical references (leaves 67-69). Also available in electronic version. Access restricted to campus users.
6
Ahlehagh, Hasti. "Techniques for communication and geolocation using wireless ad hoc networks." Link to electronic thesis, 2004. http://www.wpi.edu/Pubs/ETD/Available/etd-0526104-111538/.
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Li, Ran. "A wireless clock distribution system using an external antenna." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011385.
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8
Kim, Kwan-Woo. "A fully-integrated all-digital outphasing transmitter for wireless communications." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37263.
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The objective of the proposed research is to present a new all-digital outphasing transmitter IC, a comprehensive explanation of its operation, and its performance characterization. The all-digital transmitter chip leverages flexible digital phase modulators (DPMs) to adaptively compensate for amplifier mismatches. As the DPM uses a digital input to directly modulate the RF phase of each path, the phase control becomes very simple and accurate for power amplifier (PA) gain/phase mismatch compensation. Furthermore, this digital phase modulation scheme also facilitates minimizing the distortion of an RF combiner. It is newly proposed that two distinct digital predistortion algorithms are required for perfect compensation for both PAs and a combiner. All phase calibration values can be adaptively calculated as a function of outphase angle and saved in digital look-up tables to predistort the phase inputs of two DPMs.
Various types of PAs and combiners are investigated to further enhance the performance of the outphasing transmitter. These features are implemented in a chip fabricated in a 0.18-¥ìm CMOS process and evaluated with IEEE 802.16e baseband symbols.
9
Park, Byeong-Ha. "A low-voltage, low-power, CMOS 900MHZ frequency synthesizer." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/16686.
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Senguttuvan, Rajarajan. "Low-cost test, diagnosis, and tuning for adaptive radio frequency systems." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22575.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Committee Chair: Chatterjee, Abhijit; Committee Member: Anderson, David; Committee Member: Durgin, Gregory; Committee Member: Swaminathan, Madhavan; Committee Member: Zhou, Hao-Min.
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Iyer, Gopal Balakrishnan. "Digital communication and control circuits for 60ghz fully integrated CMOS digital radio." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/39589.
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Emerging "bandwidth hungry" applications such as high definition video distribution and ultra fast multimedia side-loading have extended the need for multi-gigabit wireless solutions beyond the reach of conventional WLAN technology or even more recently emerging UWB and MIMO systems. The availability of 7GHz of unlicensed bandwidth in the 60GHz spectrum, represents a unique opportunity to address such data-throughput requirements. The 60GHz Integrated CMOS digital radio chipset comprises of PHY and MAC layers, RF transceiver, High-Speed Digital Interface and an underlying Serial Communication Fabric.
To have a complete communication solution compliant with the latest ECMA-369, ISO/DIS 13156 and IEEE 802.15.3c standards, we build a million gate digital implementation of MAC and PHY. The Serial Peripheral Interface (SPI) serves as the bridge between the higher layers in the communication stack (PAL-MAC) and the lower layers like PHY-RF Front End. The MAC module can setup the communication link on the fly by tuning parameters such as operating channel, channel bonding and bandwidth, data rates, error correction mechanisms, handshaking mechanisms, etc, by using the SPI to communicate with internal components. The SPI interface plays a crucial rule in not only this, but also during the testing and debug phase. Operation of each of the RF modules is monitored through the serial interface using local SPI slaves which are hooked up to the 4-wire serial bus running all through the chip. The SPI host controller emulates an embedded protocol analyzer. For calibration and fine tuning purposes, digital settings can also be loaded onto these modules through the SPI interface. R-2R DACs are used to convert these commands into analog voltages which then provide a tunable bias to the RF and mixed-signal modules. Other key functions of this serial communication and control interface are: Initialization of all of the RF and mixed signal modules, DC calibration of data converter, PLL and other mixed-signal modules, data acquisition, parametric tuning for digital modules such as linear equalizer, Gain Control loops (AGC, VGA), etc.
Ultra high speed digital Input-Output buffers are used to provide an external data interface to the radio chipset. These high speed I/Os are also used in the gbps (gigabit-per-second) link for data transfer between the RF transceiver chip and the PHY-MAC baseband chip. The IOs are expected to comply with different signaling standards such as LVDS, SLVS200, SLVS400, etc. A robust system involves a meticulous pad ring design with proper power domains and power cuts. Full-chip integration of the digital PHY, MAC, peripheral logic and IO ring is done in a semi-custom fashion.
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Bomstad, Wayne Roger. "An ultra-compact antenna test system and its analysis in the context of wireless clock distribution." [Gainesville, Fla.]: University of Florida, 2002. http://purl.fcla.edu/fcla/etd/UFE0000507.
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Choi, Jaehyouk. "Fully-integrated DLL/PLL-based CMOS frequency synthesizers for wireless systems." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/42698.
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A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important.
As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs.
In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.
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Zheng, Guizhen. "Low power reconfigurable microwave circuits using RF MEMS switches for wireless systems." Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-05242005-135940/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006.John Papapolymerou, Committee Chair ; Joy Laskar, Committee Member ; John Cressler, Committee Member ; Alan Doolittle, Committee Member ; Clifford Henderson, Committee Member.
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al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.
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Zhang, Wei Zhang. "Wireless receiver designs from information theory to VLSI implementation /." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31817.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Ma, Xiaoli; Committee Member: Anderson, David; Committee Member: Barry, John; Committee Member: Chen, Xu-Yan; Committee Member: Kornegay, Kevin. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Moon, Sung Tae. "Design of high performance frequency synthesizers in communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2329.
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Frequency synthesizer is a key building block of fully-integrated wireless communication
systems. Design of a frequency synthesizer requires the understanding of
not only the circuit-level but also of the transceiver system-level considerations. This
dissertation presents a full cycle of the synthesizer design procedure starting from the
interpretation of standards to the testing and measurement results.
A new methodology of interpreting communication standards into low level circuit
specifications is developed to clarify how the requirements are calculated. A
detailed procedure to determine important design variables is presented incorporating
the fundamental theory and non-ideal effects such as phase noise and reference
spurs. The design procedure can be easily adopted for different applications.
A BiCMOS frequency synthesizer compliant for both wireless local area network
(WLAN) 802.11a and 802.11b standards is presented as a design example. The two
standards are carefully studied according to the proposed standard interpretation
method. In order to satisfy stringent requirements due to the multi-standard architecture,
an improved adaptive dual-loop phase-locked loop (PLL) architecture is
proposed. The proposed improvements include a new loop filter topology with an
active capacitance multiplier and a tunable dead zone circuit. These improvements
are crucial for monolithic integration of the synthesizer with no off-chip components.
The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time
performance while making it more suitable for monolithic integration. It opens a
new possibility of using an integer-N architecture for various other communication
standards, while maintaining the benefit of the integer-N architecture; an optimal
performance in area and power consumption.
18
Yoo, Seungyup. "Field effect transistor noise model analysis and low noise amplifier design for wireless data communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13024.
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Pham, Tien Ke. "Low-power, high-accuracy, and fast-tuning integrated continuous-time 450-KHz bandpass filter." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13525.
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Perumana, Bevin George. "Low-power CMOS front-ends for wireless personal area networks." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/26712.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanouil. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Zheng, Guizhen. "Low Power Reconfigurable Microwave Circuts Using RF MEMS Switches for Wireless Systems." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/11656.
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This dissertation presents the research on several different projects. The first project is a via-less CPW RF probe pad to microstrip transition; The second, the third, and the fourth one are reconfigurable microwave circuits using RF MEMS switches: an X-band reconfigurable bandstop filter for wireless RF frontends, an X-band reconfigurable impedance tuner for a class-E high efficiency power amplifier using RF MEMS switches, and a reconfigurable self-similar antenna using RF MEMS switches. The first project was developed in order to facilitate the on-wafer measurement for the second and the third project, since both of them are microstrip transmission line based microwave circuits. A thorough study of the via-less CPW RF probe pad to microstrip transition on silicon substrates was performed and general design rules are derived to provide design guidelines. This research work is then expanded to W-band via-less transition up to 110 GHz. The second project is to develop a low power reconfigurable monolithic bandstop filter operating at 8, 10, 13, and 15 GHz with cantilever beam capacitive MEMS switches. The filter contains microstrip lines and radial stubs that provide different reactances at different frequencies. By electrically actuating different MEMS switches, the different
reactances from different radial stubs connecting to these switches will be selected, thus, the filter will resonate at different frequencies. The third project is to develop a monolithic reconfigurable impedance tuner at 10 GHz with the cantilever DC contact MEMS switch. The impedance tuner is a two port network based on a 3bit-3bit digital design, and uses 6 radial shunt stubs that can be selected via integrated DC contact MEMS switches. By selecting different states of the switches, there will be a total of 2^6 = 64 states, which means 64 different impedances will be generated at the output port of the tuner. This will provide a sufficient tuning range for the output port of the power amplifier to maximize the power efficiency. The last project is to integrate the DC contact RF MEMS switches with self-similar planar antennas, to provide a reconfigurable antenna system that radiates with similar patterns over a wide range of frequencies.
22
Kong, Wan-Chul. "Low-power low-phase noise LC oscillators in silicon-on-sapphire CMOS technology /." Title page, table of contents and abstract only, 2004. http://web4.library.adelaide.edu.au/theses/09ENS/09ensk822.pdf.
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Cui, Yan Niu Guofu. "High frequency noise modeling and microscopic noise simulation for SiGe HBT and RF CMOS." Auburn, Ala., 2006. http://repo.lib.auburn.edu/Send%2012-15-07/CUI_YAN_8.pdf.
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Cook, Benjamin Stassen. "Vertical integration of inkjet-printed RF circuits and systems (VIPRE) for wireless sensing and inter/intra-chip communication applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51844.
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Inkjet-printing is a technology which has for the last decade been exploited to fabricate flexible RF components such as antennas and planar circuit elements. However, the limitations of feature size and single layer fabrication prevented the demonstration of compact, and high efficiency RF components operating above 10 GHz into the mm-Wave regime which is critical to silicon integration and fully-printed modules. To overcome these limitations, a novel vertically-integrated fully inkjet-printed process has been developed and characterized up to the mm-Wave regime which incorporates up to five highly conductive metal layers, variable thickness dielectric layers ranging from 200 nm to 200 um, and low resistance through-layer via interconnects. This vertically-integrated inkjet printed electronics process, tagged VIPRE, is a first of its kind, and is utilized to demonstrate fully additive RF capacitors, inductors, antennas, and RF sensors operating up to 40 GHz. In this work, the first-ever fully inkjet printed multi-layer RF devices operating up to 40 GHz with high-performance are demonstrated, along with a demonstration of the processing techniques which have enabled the printing of multi-layer RF structures with multiple metal layers, and dielectric layers which are orders of magnitude thicker than previoulsy demonstrated inkjet-printed structures. The results of this work show the new possibilities in utilizing inkjet printing for the post-processing of high-efficiency RF inductors, capacitors, and antennas and antenna arrays on top of silicon to reduce chip area requirements, and for the production of entirely printed wireless modules.
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Woo, Sang Hyun. "Low noise RF CMOS receiver integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50127.
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The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which senses and compensates local oscillator (LO) phase mismatches, the dominant cause of flicker noise.
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Kim, Jihwan. "High performance radio-frequency and millimeter-wave front-end integrated circuits design in silicon-based technologies." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44704.
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Design techniques and procedures to improve performances of radio-frequency and millimeter-wave front-end integrated circuits were developed. Power amplifiers for high data-rate wireless communication applications were designed using CMOS technology employing a novel device resizing and concurrent power-combining technique to implement a multi-mode operation. Comprehensive analysis on the efficiency degradation effect of multi-input-single-output combining transformers with idle input terminals was performed. The proposed discrete resizing and power-combining technique effectively enhanced the efficiency of a linear CMOS power amplifier at back-off power levels. In addition, a novel power-combining transformer that is suitable to generate multi-watt-level output power was proposed and implemented. Employing the proposed power-combining transformer, a high-power linear CMOS power amplifier was designed. Furthermore, receiver building blocks such as a low-noise amplifier, a down-conversion mixer, and a passive balun were implemented using SiGe technology for W-band applications.
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Muppalla, Ashwin K. "Ultra low power multi-gigabit digital CMOS modem technology for millimeter wave wireless systems." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41084.
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The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system.
The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis,
Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure.
The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a multi-gigabit wireless communication system. The demodulator operates at input data rates of multiple gigabits per second, which presents the challenge of designing the building blocks to operate at speeds of multiple GHz. The high speed complex multiplier is a major component of the non coherent demodulator. As part of the coherent demodulator the complex multiplier derotates the input sequence by multiplying with cosine and sine functions, Costas error calculator computes the phase error in the derotated input signal. The NCO (Numerically controlled Oscillator) is a look up table based system used to generate the cosine and sine functions, used by the derotator.The CIC filter is used to decimate the costas error signal as the loop bandwidth is significantly smaller compared to the sampling frequency. All these modules put together form the coherent demodulator which is an integral part of the wireless communication system. An implementation of Serdes is also presented which acts as an interface between the baseband modules and the RF front end.
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Chen, Chih-Hung Deen M. Jamal. "Noise characterization and modeling of MOSFETs for RF IC applications /." *McMaster only, 2002.
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Goyal, Abhilash. "Methodologies for low-cost testing and self-healing of rf systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44705.
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This thesis proposes a multifaceted production test and post-manufacture yield enhancement framework for RF systems. This framework uses low-cost test and post-manufacture calibration/tuning techniques. Since the test cost and the yield of the RF circuits/sub-system directly contribute to the manufacturing cost of RF systems, the proposed framework minimizes overall RF systems' manufacturing cost by taking two approaches. In the first approach, low-cost testing methodologies are proposed for RF amplifiers and integrated RF substrates with an embedded RF passive filter and interconnect. Techniques are developed to test RF circuits by the analysis of low-frequency signal of the order of few MHz and without using any external RF test-stimulus. Oscillation principles are used to enable testing of RF circuits without any external test-stimulus. In the second approach, to increase the yield of the RF circuits for parametric defects, RF circuits are tuned to compensate for a performance loss during production test using on-board or on-chip resources. This approach includes a diagnosis algorithm to identify faulty circuits within the system, and performs a compensation process that adjusts tunable components to enhance the performance of the RF circuits. In the proposed yield improvement methodologies, the external test stimulus is not required because the stimulus is generated by the RF circuit itself with the help of additional circuitry and faulty circuits are detected using low-cost test methods developed in this research. As a result, the proposed research enables low-cost testing and self-healing of RF systems.
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Douglas, Dale Scott. "Flicker noise in cmos lc oscillators." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26550.
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Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted.
A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techniques to be evaluated, despite possibly changing bias points or tank Q, which would change phase noise and FOM in the 1/f2 region.
The work of Hajimiri is extended with a simple Amplitude ISF DC component estimator for the special case of LC CMOS oscillators. A method of adaptive control of an oscillator core is presented, as well, comprised of a CMOS oscillator with a digitally adjustable N and P width, and a circuit (which is essentially a tracking ADC) which repeatedly adjusts the relative N to P width dependent on the estimate to maintain the condition of minimum flicker noise upconversion. A fixed calibration constant is sufficient to allow convergence to within 0.7dB of optimal FOM1 for all cases of N width, for a varactorless oscillator test cell.
Finally, a circuit is proposed which would allow the flicker noise reduction technique of cycling to accumulation to be applied to continuous time oscillators, but is not rigorously vetted.
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Ozgur, Soner. "Reduced Complexity Sequential Monte Carlo Algorithms for Blind Receivers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10518.
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Monte Carlo algorithms can be used to estimate the state of a system given relative observations. In this dissertation, these algorithms are applied to physical layer communications system models to estimate channel state information, to obtain soft information about transmitted symbols or multiple access interference, or to obtain estimates of all of these by joint estimation.
Initially, we develop and analyze a multiple access technique utilizing mutually orthogonal complementary sets (MOCS) of sequences. These codes deliberately introduce inter-chip interference, which is naturally eliminated during processing at the receiver. However, channel impairments can destroy their orthogonality properties and additional processing becomes necessary.
We utilize Monte Carlo algorithms to perform joint channel and symbol estimation for systems utilizing MOCS sequences as spreading codes. We apply Rao-Blackwellization to reduce the required number of particles. However, dense signaling constellations, multiuser environments, and the interchannel interference introduced by the spreading codes all increase the dimensionality of the symbol state space significantly. A full maximum likelihood solution is computationally expensive and generally not practical. However, obtaining the optimum solution is critical, and looking at only a part of the symbol space is generally not a good solution. We have sought algorithms that would guarantee that the correct transmitted symbol is considered, while only sampling a portion of the full symbol space. The performance of the proposed method is comparable to the Maximum Likelihood (ML) algorithm. While the computational complexity of ML increases exponentially with the dimensionality of the problem, the complexity of our approach increases only quadratically.
Markovian structures such as the one imposed by MOCS spreading sequences can be seen in other physical layer structures as well. We have applied this partitioning approach with some modification to blind equalization of frequency selective fading channel and to multiple-input multiple output receivers that track channel changes.
Additionally, we develop a method that obtains a metric for quantifying the convergence rate of Monte Carlo algorithms. Our approach yields an eigenvalue based method that is useful in identifying sources of slow convergence and estimation inaccuracy.
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Omer, Mohammad. "Towards harmonious coexistence : linear and nonlinear techniques for interference management in RFICs." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51938.
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This thesis has sought to provide another look at RF interference at the fundamental level. While previous interference control and regulation methods have existed in the literature, they were more focused on preventing the interference from happening. On the contrary, we have taken a different approach of correcting the interference once it has happened. This allows the transmitters to be more nonlinear, passive filter design to be eased, and receivers to be aware of interference problems. Under this unifying theme of building intelligent radios where receivers are more cognizant of the transmission environment, we have presented a number of architectures.
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Bharath, Krishna. "Signal and power integrity co-simulation using the multi-layer finite difference method." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28155.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitaraman.
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Yamamoto, Silas Demmy. "Integração de sistema transceptor de 60 GHz para aplicações sem fio de interface multimídia de alta definição." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259229.
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Orientador: Jacobus Willibrordus SwartDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
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Resumo: O trabalho intitulado Integração de Sistema Transceptor de 60 GHz para Aplicações Sem Fio de Interface Multimídia de Alta Definição (Wireless HDMI) foi realizado na empresa STMicroelectronics (França), no departamento de P&D de Tecnologia / CAD Central e Soluções, como requisito para a obtenção do título de mestre. O objetivo deste trabalho foi de pesquisar e propor uma integração de sistema do tipo Sistema no Empacotamento (SiP ou System in Package) a nível industrial, com o desenvolvimento de um Módulo de Múltiplos Chips (MCM ou Multi-Chip Module) de camadas cerâmicas com tecnologia Cerâmica Cossinterizada sob Alta Temperatura (HTCC), integrando componentes de diferentes tecnologias - um circuito integrado CMOS 65 nm, um circuito integrado monolítico de micro-ondas (MMIC) de Arseneto de Gálio (GaAs) comercial e antenas IPD (Dispositivo de Integração Passiva) de vidro. Além disso foram desenvolvidas técnicas de projeto de integração na tecnologia HTCC, atendendo-se às regras para fabricação e montagem industrial. Utilizaram-se no projeto ferramentas software de projeto de simulação elétrica e eletromagnética, resultando no módulo com área de 13 x 8 mm2 e 1,12 mm de espessura incluindo os componentes. Nas linhas de transmissão do sinal a 60 GHz e de banda base foram medidas perdas de inserção de 1,0 dB/mm e 0,6 dB respectivamente. A antena integrada no módulo apresentou um ganho mínimo de 6 dBi (de 53,5 a 59,5 GHz), com perda de retorno maior que 10 dB (de 51 a 63 GHz) e um pequeno deslocamento em relação à banda especificada. Os resultados de medição de algumas amostras demonstraram que a tecnologia HTCC, para integração do sistema, é viável tanto em termos de desempenho, quanto nos aspectos industrial e comercial, mesmo antes da análise da montagem e desempenho do MMIC HPA e do sistema
Abstract: This Master's degree work, entitled System-in-Package (SiP) Integration of 60 GHz Transceiver for Wireless High Definition Multimedia Interface Application, was executed at STMicroelectronics Company (France), Minatec site in the department of Research and Technological Development/Central CAD and Solutions Department, under the guidance of PhD. Andreia Cathelin. The objective was to research and propose a SiP integration for industrial production. The Multi-Chip Module with ceramic materials (MCM-C) of High Temperature Cofired Ceramic technology (HTCC) was developed. Components and devices of different technologies - an RF 65 nm CMOS Integrated Circuit (IC), a commercial Gallium Arsenide (GaAs) monolithic microwave IC (MMIC), and IPD (Integrated Passive Device) antennas with glass substrate - were integrated into the same module. Further design techniques were developed complying with techniques for industrial assembly and the design rules of Kyocera, the company which provides HTCC technology and module manufacturing. The complete system integration was designed with electronic design automation (EDA) software tools with electrical and electromagnetic simulation resulting in a 13 x 8 mm2 area and 1.12 mm thickness module including its components. The 60 GHz and the base band transmission lines presented an insertion loss of 1.0 dB/mm and 0.6 dB respectively. The IPD antenna integrated in the module presented a 6 dBi minimum gain (53.5 to 59.5 GHz band) with return loss above 10 dB (51 to 63 GHz band) and a small shift of the frequency band. The measurement results of some assembled samples showed that HTCC technology is viable in terms of performance and industrial production for the 60 GHz application, even before the analysis of MMIC HPA and the system evaluation
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Yoo, Seoung-Jae. "Design of analog baseband circuits for wireless communication receivers." Columbus, Ohio Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1073617255.
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Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xvi, 167 p.; also includes graphics (some col.). Includes abstract and vita. Advisor: Mohammed Ismail ElNaggar, Dept. of Electrical Engineering. Includes bibliographical references (p. 163-167).
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Huang, Deping. "Design Techniques for Timing Circuits in Wireline and Wireless Communication Systems." Diss., The University of Arizona, 2014. http://hdl.handle.net/10150/344107.
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Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer electronic devices, effective design of CDR and frequency synthesizer has become more and more important. The advanced scaled-down CMOS process has the limitations of leakage current, low supply voltage and process variation which pose great challenge to the analog circuit design. To overcome these issues, a digital intensive CDR solution is needed. Besides, it is desirable for the CDR to cover a wide range of data-rate and to be reference-less for improved flexibility. As for the frequency synthesizer design, the support for multi-standard to reduce the cost and area is desirable. In this work, a digital reference-less CDR is proposed to support continuous datarate ranging from 1 Gbps to 16 Gbps. The CDR adopts an 8 GHz~16 GHz DCO to achieve low random noise performance. A reference-less digital frequency locking loop is included in the system as the acquisition assistance for the CDR loop. To address the difficulty of jitter and stability evaluations for bang-band CDR, a Simulink model is developed to find out the jitter transfer (JTRAN), jitter generation (JGEN) and jitter tolerance (JTOL) performances for the CDR. The prototype CDR is implemented in a 65 nm CMOS process. The core area is 0.68 mm². At 16 Gbps, the CDR consumes a power of 92.5 mW and is able to tolerate a sinusoidal jitter with an amplitude of 0.4 UI and a frequency of 4 MHz. The second part of this dissertation develops a frequency synthesizer for multistandard wireless receivers. The frequency synthesizer is based on an analog fractional-N PLL. Optimally-coupled quadrature voltage-controlled-oscillator (QVCO), dividers and harmonic rejection single sideband mixer (HR-SSBmixer) are combined to synthesize the desired frequency range without posing much phase noise penalty on the QVCO. The QVCO adopts a new phase-shift scheme to improve phase noise and to eliminate bimodal oscillation. Combining harmonic rejection and single sideband mixing, the HR-SSBmixer is developed to suppress spurious signals. Designed in a 0.13-μm CMOS technology, the synthesizer occupies an active area of 1.86 mm² and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer frequency range, the phase noise, the settling time and the spur performances meet the specifications of the wireless receivers for the above standards. For a wide range frequency synthesizer, an automatic frequency calibration circuit (AFC) is needed to select proper oscillator tuning curve before the PLL settling. An improved counter-based AFC is proposed in this dissertation that provides a more robust and faster tuning curve searching process. The proposed AFC adopts a time-to-digital converter (TDC), which is able to captures the fractional VCO cycle information within the counting window, to improve the AFC frequency detection accuracy. The TDC-based AFC is designed in a 0.13-μm CMOS technology. Simulation results show that the TDCbased AFC greatly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time.
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Zhang, Tan Tan. "Nano-watt class CMOS interface circuits for wireless sensor nodes." Thesis, University of Macau, 2018. http://umaclib3.umac.mo/record=b3952097.
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Heo, Deukhyoun. "Silicon MOS field effect transistor RF/Microwave nonlinear model study and power amplifier development for wireless communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15618.
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Sutono, Albert. "Development and implementation of design methodologies for integrated wireless communications system on package." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13433.
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Olutade, Bolaji OmoLaja. "Thin film ZnO-based resonators for integrated wireless applications." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13547.
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Gard, Kevin. "Autocorrelation analysis of spectral regrowth generated by nonlinear circuits in wireless communication systems /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3112869.
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Huang, Yan-Yu. "CMOS-based amplitude and phase control circuits designed for multi-standard wireless communication systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44908.
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Designing CMOS linear transmitter front-end, specially the power amplifiers (PAs), in multi-band wireless transceivers is a major challenge for the single-chip integration of a CMOS radio. In some of the linear PA systems, for example, polar- or predistortion-PA system, amplitude and phase control circuits are used to suppress the distortion produces by the PA core. The requirements of these controlling circuits are much different from their conventional role in a receiver or a phase array system. In this dissertation, the special design issues will be addressed, and the circuit topologies of the amplitude and phase controllers will be proposed.
In attempt to control the high-power input signal of a PA system, a highly linear variable attenuator with adaptive body biasing is first introduced. The voltage swing on the signal path is intentionally coupled to the body terminal of the triple-well NMOS devices to reduce their impedance variation. The fabricated variable attenuator shows a significant improvement on linearity as compared to previous CMOS works. The results of this research are then used to build a variable gain amplifier for linear PA systems that requires gain of its amplitude tuning circuits. Different from the conventional attenuator-based VGAs, the high linearity of the suggested attenuator allows it to be put after the gain stage in the presented VGA topology. This arrangement along with the current boosting technique gives the VGA a better noise performance while having a linear-in-dB tuning curve and better worst-case linearity.
The following part of the dissertation is about a compact, linear-in-degree tuned variable phase shifter as the phase controller in the PA system. This design uses a modified RC poly-phase filter to produce a set of an orthogonal phase vectors with smaller loss. A specially designed control circuit combines these vectors and generates an output signal with different phases, while having very small gain mismatches at different phase setting. The proposed amplitude and phase control circuits are then verified with a system level analysis. The results show that the proposed designs successfully reduce the non-linear effect of a wireless transmitter.
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Zhang, Benyong. "A 2.4GHz, Low Power, Fully-Integrated CMOS Frequency Synthesizer for Wireless Communications." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13050.
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Yang, Shun Yu. "OPNET/STK integrated environment for modeling an UAV network." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03sep%5FYang.pdf.
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Thesis (M.S. in Systems Engineering)--Naval Postgraduate School, September 2003.Thesis advisor(s): Alex Bordetsky, Rex Buddenberg. Includes bibliographical references (p. 45). Also available online.
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Roy, Palash. "High-Power, High-Efficiency, Multi-Functional CMOS Radio Frequency Integrated Circuit for Wireless Communication of Unmanned Aircraft System." Diss., North Dakota State University, 2017. http://hdl.handle.net/10365/26047.
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Recently the Unmanned Aircraft System (UAS) has become very popular due to its current and projected opportunities in diversified applications from surveillance to security to militry. The Federal Aviation Administration (FAA) has mandated for all UASs to be equipped with an Automatic Dependent Surveillance Broadcast (ADS-B) transmitter by 2020. ADS-B is a next generation aircraft communication system, operating with two frequencies, 978 MHZ and 1090 MHz, which will transmit the information of identification, and precise position of an airplane to the nearby airplanes and ground station. At present, the ADS-B transmitter is fabricated with hybrid integrated circuits (HICs) in three different modules: a Phase Locked Loop (PLL) module, an Up-converter (modulator) module and a Power Amplifier (PA) module [8-10] which makes the system very large in size and expensive. In this work, for the first time an ADS-B transmitter as a part of Universal Access Transceievr (UAT) and Universal Beacon Radio (UBR) has beeen developed in a fully integrated single chip using the Complementary Metal Oxide Semiconductor (CMOS) process which is capable of operating both at 978 MHz UAT and 1090 MHz Extended Squitter (ES) modes. The chip provides the modulated output power of 23 dBm which is sufficient for the UAS to operate below class-A airspace. If the UAS needs to operate above this range or needs to operate for a manned aircraft system, this single chip ADS-B transmitter can be interfaced to drive an off-chip high-power PA, and, thus, it will reduce the burden of the input power and the gain of the off-chip PA. The chip supports both single tone and modulated baseband signals. In addition, this chip is capable of operating a part of new datalinks (960 MHz to 1164 MHz) and DME bands for UAS.Center of Research Excellence (CORE) of North Dakota
Limited Deployment Cooperative Airspace Project: NDSU ADS-B Miniaturization Program
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Zhu, Xi. "High frequency CMOS integrated filters for computer hard disk drive and wireless communication systems." Thesis, University of Hertfordshire, 2008. http://hdl.handle.net/2299/2069.
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Operational transconductance amplifier and capacitor (OTA-C) filters have outstood among different types of filter due to high frequency and low power capabilities in the main stream digital CMOS technology. They have been widely used in computer hard disk drive (HDD) and wireless communication transceivers. OTA-C filters based on cascade and passive ladder simulation are well-known. However, multiple loop feedback (MLF) OTA-C filters which have certain advantages still have the scope for further research. So far there have been no explicit formulas for current-mode leapfrog (LF) filter design and performance evaluation of current-mode MLF OTA-C filters are still lacking. From application viewpoints, read channels for computer hard disk drives require very high frequency continuous-time filters. This automatically disqualifies active- RC/MOSFET-C filters and OTA-C filters become the only solution. In wireless communications, active-RC/MOSFET-C filters have been proved useful for mobile systems whose baseband frequency falls below a few MHz. However, for wireless LANs with the frequency of several tens of MHz, OTA-C filters are a strong candidate. Whilst in HDD read channels, cascaded OTA-C architectures have been most utilized and in wireless receivers, OTA-C structures based on ladder simulation have been popular, MLF OTA-C filters have not been practically used in either of the applications. This thesis describes some novel designs and applications of multiple loop feedback OTA-C filters with extensive CMOS simulations. Analogue filters for computer hard disk drive systems are first reviewed; the state of the art and design considerations are provided. Three VHF linear phase lowpass OTA-C filters are then designed, which include a seventh-order and a fifth-order current-mode filter based on the follow-the-leader-feedback (FLF) structure and a seventh-order voltage-mode filter using the inverse FLF (IFLF) configuration. These filters all have very low power consumption. The synthesis and design of general current-mode LF OTA-C filters are conducted next. Iterative design formulas for both all-pole and finite-zero functions are derived and explicit formulas for up to sixth-orders are given. These formulas are very easy to use for designing any type of characteristics. Subsequently, linear phase lowpass OTA-C filter design for HDD read channels using LF structures are investigated in details. A current-mode filter and a voltage-mode filter using the fifth-order LF structure are presented. The two filters can operate up to 800MHz and have very small passband phase ripple. Analogue filters for wireless communication baseband applications are also reviewed thoroughly in this thesis, where the design of a fourth-order current-mode FLF Butterworth lowpass OTA-C filter for multi-standard receivers is presented. Then two fifth-order current-mode elliptic lowpass OTA-C filters based on respective LF and FLF structures for wireless communication baseband are designed. Fifth-order voltage-mode IFLF and LF elliptic lowpass filters are also presented. All these MLF baseband filters designed can operate up to 40MHz to cover all important wireless and mobile standards. Simulations show that the LF structures have better dynamic range and stopband attenuation performances than the FLF and IFLF configurations.
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Kho, Yau Hee. "MIMO Receiver Structures with Integrated Channel Estimation and Tracking." Thesis, University of Canterbury. Electrical and Computer Engineering, 2008. http://hdl.handle.net/10092/1264.
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This thesis looks at the problem of channel estimation and equalization in a multiple-input multiple-output (MIMO) dispersive fading environments. Two classes of MIMO receiver structure are proposed with integrated channel estimation and tracking. One is a symbol-by-symbol based receiver using a MIMO minimum mean square error (MMSE) decision feedback equalizer (DFE), and the other is a sequence-based receiver using a partitioned Viterbi algorithm (PVA) which approaches the performance of maximum likelihood sequence estimation (MLSE). A MIMO channel estimator capable of tracking the time and frequency selective channel impulse responses, known as the vector generalized recursive least squares (VGRLS) algorithm, is developed. It has comparable performance and a similar level of complexity as the optimum Kalman filter. However, it does not require any knowledge of the channel statistics to operate and as such it can be employed in a Rician fading channel readily. A reduced complexity form of the estimator, known as the vector generalized least mean squares (VGLMS) algorithm, is also developed. This is achieved by replacing the online recursive computation of the VGRLS algorithm's 'intermediate' Riccatti matrix with an offline pre-computed matrix. This reduces the complexity of the algorithm by an order of a magnitude, but at the expense of degraded performance. The estimators are integrated with the above-mentioned equalizers in a decision directed mode to form a receiver structure that can operate in continuously time-varying fading channels. Due to decision delays, the outputs from the equalizer are delayed and this then produces 'delayed' channel estimates. A simple polynomial-based channel prediction module is employed to provide up-to-date channel estimates required by the equalizers. However, simulation results show that the channel prediction module may be omitted for a very slowly fading channel where the channel responses do not vary much. In the case of the PVA- receiver, the zero-delay tentative decisions are used as feedback to the channel estimators with negligible loss.
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Nafkha, Amor. "A geometrical approach detector for solving the combinatorial optimisation problem : application in wireless communication systems." Lorient, 2006. http://www.theses.fr/2006LORIS067.
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Cette thèse s'intéresse à la résolution du problème classique de décodage d'un mélange linéaire entaché d'un bruit additif gaussien. A partir d'une observation bruitée: y = Hx+b, d'un vecteur d'entiers x mélangé linéairement par une matrice H connue, b étant un vecteur de bruit, on cherche le vecteur x minimisant la distance Euclidienne entre y et le vecteur Hx. Ce problème est réputé NP-complet. Il intervient dans un grand nombre de systèmes de télécommunications (MIMO, MC-CDMA, etc. ). Nous proposons dans cette thèse un algorithme de résolution quasi optimal de ce problème et bien adapté à une implémentation matérielle. Notre démarche s'appuie sur l'utilisation des méthodes classiques de recherche opérationnelle : trouver des points initiaux répartis sur l'espace des solutions possibles et potentiellement proches de la solution optimale (diversification) et effectuer une recherche locale au voisinage des ces points (intensification). Dans ce travail, la diversification est basée sur une approche géométrique utilisant les axes dominants de concentration du bruit. Les performances en terme de taux d'erreur par bit de la méthode proposée sont proches de l'optimum tout en gardant une complexité constante et un degré de parallélisme important. Nous avons étendu cette méthode à la constellation MAQ-16 d'une part, et à la génération d'une décision souple d'autre part. Nous avons étudié l'algorithme proposé du point de vue implémentation matérielle. L'algorithme proposé présente d'une part une nouvelle alternative pour le décodage quasi optimal du mélange bruité et d'autre part un important degré de parallélisme permettant une implémentation efficaceThe demand for mobile communication systems with high data rates and improved link quality for a variety of applications has dramatically increased in recent years. New concepts and methods are necessary in order to cover this huge demand, which counteract or take advantage of the impairments of the mobile communication channel and optimally exploit the limited resources such as bandwidth and power. The problem of finding the least-squares solution to a system of linear equations where the unknown vector is comprised of integers, but the matrix coefficients and given vector are comprised of real numbers, arise in many applications: communications, cryptography, MC-CDMA, MIMO, to name a few. The Maximum Likelihood (ML) decoding is equivalent to finding the closest lattice point in an n-dimensional real space. In general, this problem is known to be non deterministic NP hard. In this thesis, a polynomial-time approximation method called Geometrical Intersection and Selection Detector (GISD) is applied to the MLD problem. Moreover, the proposed approach is based on two complementary "real time" operational research methods: intensification and diversification. Our approach has three important characteristics that make it very attractive for for VLSI implementation. First, It will be shown that the performance of GISD receiver is superior as compared to other sub-optimal detection methods and it provides a good approximation to the optimal detector. Second, the inherent parallel structure of the proposed method leads to a very suitable hardware implementation. Finaly, The GISD allows a near optimal performance with constant polynomial-time, O(n3), computational complexity (unlike the sphere decoding that has exponential-time complexity for low SNR). The proposed Detector can be efficiently employed in most wireless communications systems: MIMO, MC-CDMA, MIMO-CDMA etc. .
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Yulei, W. U. "Performance modelling and evaluation of heterogeneous wired / wireless networks under Bursty Traffic. Analytical models for performance analysis of communication networks in multi-computer systems, multi-cluster systems, and integrated wireless systems." Thesis, University of Bradford, 2010. http://hdl.handle.net/10454/4423.
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Computer networks can be classified into two broad categories: wired networks and wireless networks, according to the hardware and software technologies used to interconnect the individual devices. Wired interconnection networks are hardware fabrics supporting communications between individual processors in highperformance computing systems (e.g., multi-computer systems and cluster systems). On the other hand, due to the rapid development of wireless technologies, wireless networks have emerged and become an indispensable part for people's lives. The integration of different wireless technologies is an effective approach to accommodate the increasing demand of the users to communicate with each other and access the Internet. This thesis aims to investigate the performance of wired interconnection networks and integrated wireless networks under the realistic working conditions. Traffic patterns have a significant impact on network performance. A number of recent measurement studies have convincingly demonstrated that the traffic generated by many real-world applications in communication networks exhibits bursty arrival nature and the message destinations are non-uniformly distributed. Analytical models for the performance evaluation of wired interconnection networks and integrated wireless networks have been widely reported. However, most of these models are developed under the simplified assumption of non-bursty Poisson process with uniformly distributed message destinations. To fill this gap, this thesis first presents an analytical model to investigate the performance of wired interconnection networks in multi-computer systems. Secondly, the analytical models for wired interconnection networks in multi-cluster systems are developed. Finally, this thesis proposes analytical models to evaluate the end-to-end delay and throughput of integrated wireless local area networks and wireless mesh networks. These models are derived when the networks are subject to bursty traffic with non-uniformly distributed message destinations which can capture the burstiness of real-world network traffic in the both temporal domain and spatial domain. Extensive simulation experiments are conducted to validate the accuracy of the analytical models. The models are then used as practical and cost-effective tools to investigate the performance of heterogeneous wired or wireless networks under the traffic patterns exhibited by real-world applications.
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Devarakond, Shyam Kumar. "Signature driven low cost test, diagnosis and tuning of wireless systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47594.
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With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these analog/RF systems are implemented in scaled nanometer nodes. At these nodes, the high level of variability in process variations is making the task of manufacturing high fidelity systems a challenge leading to yield and reliability issues. Hence, in the post-manufacturing phase, test and diagnosis steps are critical to identify the cause and effect of the process variations. Further, intelligent post-manufacturing tuning techniques are required to correct the effect of process variations on analog/RF systems. In this work, a die-level concurrent test and diagnosis approach using optimized measurements obtained in high volume manufacturing environment is proposed for analog/RF circuits. Such a simultaneous test and diagnosis methodology enables monitoring parametric process shifts and providing rapid feedback to the fab to minimize or prevent yield loss. In the case of devices that are continuously operating in the field, an efficient on-line diagnosis approach has been developed to perform reliability related prognosis. For advanced RF technologies such as MIMO-OFDM systems, a rapid system-level testing scheme is presented that performs concurrent testing of the multiple RF chains. Depending on the availability of the computational resources and system tuning knobs, different low-cost methodologies for post-manufacture tuning or self-healing of RF SISO/MIMO systems are developed. These include faster digital monitoring and tuning techniques, on-chip tuning techniques using digital logic that enables die-level self-tuning, and DSP-based power conscious iterative techniques for SISO/MIMO RF systems. An adaptive power-performance tuning technique is developed for those devices that have a post-manufacture power consumption value that is more than the acceptable limit. These intelligent post-manufacturing techniques result in reduced manufacturing cost, improved yield, and reliability of analog/RF systems.