Relevant bibliographies by topics / Word processors

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Word processors'

Author: Grafiati
Published: 4 June 2021
Last updated: 30 January 2023

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Journal articles on the topic "Word processors"

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Kaplan, Sidney. "WORD PROCESSORS." History Workshop Journal 21, no. 1 (1986): 223–24. http://dx.doi.org/10.1093/hwj/21.1.223.

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Van Haalen, Teresa, and George W. Bright. "Writing and Revising by Bilingual Students in Traditional and Word Processing Environments." Journal of Educational Computing Research 9, no. 3 (August 1993): 313–28. http://dx.doi.org/10.2190/6kxy-73wh-tyll-vj30.

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Examination of current research indicates caution in drawing conclusions about the benefits of the use of word processors, especially in elementary school. A variety of factors (e.g., keyboarding skill, technology aptitude, familiarity with the language of the word processor) might influence these benefits. This study focused on the effects of writing with word processors for students with varying proficiency in English.
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Wolfe, Edward W., Sandra Bolton, Brian Feltovich, and Art W. Bangert. "A Study of Word Processing Experience and its Effects on Student Essay Writing." Journal of Educational Computing Research 14, no. 3 (April 1996): 269–83. http://dx.doi.org/10.2190/xtdu-j5l2-wtpp-91w2.

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This study investigates how word processing experience influences student performance on a direct writing assessment. We investigated factors influencing a student's decision about using word processors for writing; whether students with less experience writing with word processors receive lower scores on word processed essays; and differences in length, neatness, mechanical correctness, and tone of the student writing as related to experience with word processors. In this study, students with different levels of experience using word processors wrote two essays: one with word processors and one with pen and paper. Students with less experience using word processors scored considerably higher on our writing assessment when their writing was done with pen and paper. Only small differences were observed between pen and paper and word processed essays for students with more word processing experience. Content analyses revealed that word processed essays appeared neater and longer than handwritten essays but that students who favor handwriting write more words with pen and paper than with word processors.
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Cudeck, Robert, and Dennis P. McGuire. "Three technical word processors." Psychometrika 52, no. 1 (March 1987): 137–50. http://dx.doi.org/10.1007/bf02293961.

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Brophy, David. "Word Processors—Looking Outside." Industrial Management & Data Systems 85, no. 3/4 (March 1985): 18–19. http://dx.doi.org/10.1108/eb057396.

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Tripp, Steven D. "A JAPANESE WORD PROCESSOR FOR THE APPLE." CALICO Journal 2, no. 4 (January 14, 2013): 21–23. http://dx.doi.org/10.1558/cj.v2i4.21-23.

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The Assist 16 is a Japanese language word processor that runs on Apple IIe and IIc computers. It requires no special hardware, and with an Epson-type printer will print Chinese character text in two sizes. For Japanese language teachers in the U.S. who cannot afford dedicated word processors this is a convenient way of editing and printing Japanese text.
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Little, Craig B. "Teaching Writing with Word Processors." Teaching Sociology 16, no. 3 (July 1988): 272. http://dx.doi.org/10.2307/1317529.

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Wanderer, Jules J. "Guttman Scaling with Word Processors." Social Science Computer Review 8, no. 3 (October 1990): 378–86. http://dx.doi.org/10.1177/089443939000800303.

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Van Horn, Royal. "Word Processors and Multiple Authors." Phi Delta Kappan 82, no. 2 (October 2000): 177–78. http://dx.doi.org/10.1177/003172170008200219.

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Balakrishnan, S. "Very long instruction word processors." Resonance 6, no. 12 (December 2001): 61–68. http://dx.doi.org/10.1007/bf02913768.

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Dissertations / Theses on the topic "Word processors"

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Sulaiman, Nasri. "Genetic algorithms for word length optimization of FFT processors." Thesis, University of Edinburgh, 2007. http://hdl.handle.net/1842/14513.

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Genetic algorithms (GAs) are a particular class of evolutionary algorithms that use techniques inspired by evolutionary biology such as inheritance, mutation, selection, and crossover to find best solutions to optimization and search problems. GAs are used in wide variety of applications in fields ranging from computer science, engineering, evolvable hardware, economics, mathematics, physics and biogenetics to name a few. A fast Fourier transform (FFT) is an efficient algorithm to compute the discrete Fourier transform (DFT) and it’s inverse. An FFT processor is used in applications such as signal processing and telecommunications, etc. It is one of the most power consuming block in wireless receivers such as Multi-Carrier Code Division Multiple Access (MC-CDMA). The portability requirement of these receiver systems imposes the need of low power architectures. Thus, designing an FFT processor with low power consumption is of crucial importance for overall system power. Power consumption of an FFT processor depends on the size of word length of the FFT coefficients. One way to reduce the power consumption in this processor is by reducing the switching activity in the FFT coefficients. This can be achieved using smaller word length for the FFT coefficients. This in turn reduces the SNR in the output signals of the FFT. This thesis investigates the impact of word length optimization of FFT coefficients on switching activity and SNR using GAs. The quality of GAs solutions are compared with non-GA solutions in order to determine the feasibility of using GAs to achieve optimum performance in terms of switching activity and SNR. Results show that GAs can find solutions with smaller word length and have significant reductions in switching compared to the non-GA solutions. This thesis also investigates some of the varying parameter settings, such as mutation domain, population size, crossover rate and mutation probability in the GAs, which affects the quality of search performance towards convergence and the speed of convergence.
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Coulter, Catherine Ann. "Writing with word processors : effects on cognitive development, revision and writing quality /." Full-text version available from OU Domain via ProQuest Digital Dissertations, 1986.

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Porpodas, Vasileios. "Instruction scheduling optimizations for energy efficient VLIW processors." Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/8291.

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Very Long Instruction Word (VLIW) processors are wide-issue statically scheduled processors. Instruction scheduling for these processors is performed by the compiler and is therefore a critical factor for its operation. Some VLIWs are clustered, a design that improves scalability to higher issue widths while improving energy efficiency and frequency. Their design is based on physically partitioning the shared hardware resources (e.g., register file). Such designs further increase the challenges of instruction scheduling since the compiler has the additional tasks of deciding on the placement of the instructions to the corresponding clusters and orchestrating the data movements across clusters. In this thesis we propose instruction scheduling optimizations for energy-efficient VLIW processors. Some of the techniques aim at improving the existing state-of-theart scheduling techniques, while others aim at using compiler techniques for closing the gap between lightweight hardware designs and more complex ones. Each of the proposed techniques target individual features of energy efficient VLIW architectures. Our first technique, called Aligned Scheduling, makes use of a novel scheduling heuristic for hiding memory latencies in lightweight VLIW processors without hardware load-use interlocks (Stall-On-Miss). With Aligned Scheduling, a software-only technique, a SOM processor coupled with non-blocking caches can better cope with the cache latencies and it can perform closer to the heavyweight designs. Performance is improved by up to 20% across a range of benchmarks from the Mediabench II and SPEC CINT2000 benchmark suites. The rest of the techniques target a class of VLIW processors known as clustered VLIWs, that are more scalable and more energy efficient and operate at higher frequencies than their monolithic counterparts. The second scheme (LUCAS) is an improved scheduler for clustered VLIW processors that solves the problem of the existing state-of-the-art schedulers being very susceptible to the inter-cluster communication latency. The proposed unified clustering and scheduling technique is a hybrid scheme that performs instruction by instruction switching between the two state-of-the-art clustering heuristics, leading to better scheduling than either of them. It generates better performing code compared to the state-of-the-art for a wide range of inter-cluster latency values on the Mediabench II benchmarks. The third technique (called CAeSaR) is a scheduler for clustered VLIW architectures that minimizes inter-cluster communication by local caching and reuse of already received data. Unlike dynamically scheduled processors, where this can be supported by the register renaming hardware, in VLIWs it has to be done by the code generator. The proposed instruction scheduler unifies cluster assignment, instruction scheduling and communication minimization in a single unified algorithm, solving the phase ordering issues between all three parts. The proposed scheduler shows an improvement in execution time of up to 20.3% and 13.8% on average across a range of benchmarks from the Mediabench II and SPEC CINT2000 benchmark suites. The last technique, applies to heterogeneous clustered VLIWs that support dynamic voltage and frequency scaling (DVFS) independently per cluster. In these processors there are no hardware interlocks between clusters to honor the data dependencies. Instead, the scheduler has to be aware of the DVFS decisions to guarantee correct execution. Effectively controlling DVFS, to selectively decrease the frequency of clusters with slack in their schedule, can lead to significant energy savings. The proposed technique (called UCIFF) solves the phase ordering problem between frequency selection and scheduling that is present in existing algorithms. The results show that UCIFF produces better code than the state-of-the-art and very close to the optimal across the Mediabench II benchmarks. Overall, the proposed instruction scheduling techniques lead to either better efficiency on existing designs or allow simpler lightweight designs to be competitive against ones with more complex hardware.
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Bierman, Cathy. "Revision and writing quality of seventh graders composing with and without word processors." Diss., Virginia Polytechnic Institute and State University, 1988. http://hdl.handle.net/10919/53912.

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This experimental study examined the effects of word processing on revision and writing quality of expository compositions produced by seventh—graders. Thirty—six students in two accelerated English classes served as subjects. Prior to the experimental period, all students completed a handwritten composition (pretest) and received identical instruction in (a) composing and revising and (b) using a word processor. One intact class was randomly assigned as the experimental group. During the six-week treatment period all students wrote six compositions (three drafts per composition). The experimental group completed all composing and revising on the computer and the control group completed their compositions with pen and paper. Posttest l (produced on computer in the experimental group and by hand in the control group) and posttest 2 (handwritten in both groups) were analyzed for the frequency and types of revisions made between first and second drafts. The pretest and three posttests were analyzed for writing quality of final drafts. There were no significant differences: (a) between groups in the number of revisions in posttest l (computer written by experimental subjects and handwritten by control subjects), (b) in percentage of high—level revisions made with and without the word processor, and (c) in quality of compositions produced with and without the computer. There was a significant difference between groups in the number of revisions in handwritten compositions (posttest 2) produced by both groups after the treatment; the word processing group revised more frequently than did the group not exposed to six weeks of word processing. The experimental subjects also significantly increased in frequency of revisions from the time of posttest l (computer written) to posttest 2 (handwritten). A significant difference across time in writing quality scores was found. The findings suggested that students who compose and revise on computer can make substantially more revisions when they resume pen and paper composing and revising; however, use of the word processor does not differentially affect types of revisions attempted or writing quality. Word processors increase motivation, and adequate systems may increase the ability to detect and eliminate textual problems. Recommendations for research, theory, and instruction are discussed.
Ed. D.
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El, Moussawi Ali Hassan. "SIMD-aware word length optimization for floating-point to fixed-point conversion targeting embedded processors." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S150/document.

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Afin de limiter leur coût et/ou leur consommation électrique, certains processeurs embarqués sacrifient le support matériel de l'arithmétique à virgule flottante. Pourtant, pour des raisons de simplicité, les applications sont généralement spécifiées en utilisant l'arithmétique à virgule flottante. Porter ces applications sur des processeurs embarqués de ce genre nécessite une émulation logicielle de l'arithmétique à virgule flottante, qui peut sévèrement dégrader la performance. Pour éviter cela, l'application est converti pour utiliser l'arithmétique à virgule fixe, qui a l'avantage d'être plus efficace à implémenter sur des unités de calcul entier. La conversion de virgule flottante en virgule fixe est une procédure délicate qui implique des compromis subtils entre performance et précision de calcul. Elle permet, entre autre, de réduire la taille des données pour le coût de dégrader la précision de calcul. Par ailleurs, la plupart de ces processeurs fournissent un support pour le calcul vectoriel de type SIMD (Single Instruction Multiple Data) afin d'améliorer la performance. En effet, cela permet l'exécution d'une opération sur plusieurs données en parallèle, réduisant ainsi le temps d'exécution. Cependant, il est généralement nécessaire de transformer l'application pour exploiter les unités de calcul vectoriel. Cette transformation de vectorisation est sensible à la taille des données ; plus leurs tailles diminuent, plus le taux de vectorisation augmente. Il apparaît donc un compromis entre vectorisation et précision de calcul. Plusieurs travaux ont proposé des méthodologies permettant, d'une part la conversion automatique de virgule flottante en virgule fixe, et d'autre part la vectorisation automatique. Dans l'état de l'art, ces deux transformations sont considérées indépendamment, pourtant elles sont fortement liées. Dans ce contexte, nous étudions la relation entre ces deux transformations, dans le but d'exploiter efficacement le compromis entre performance et précision de calcul. Ainsi, nous proposons d'abord un algorithme amélioré pour l'extraction de parallélisme SLP (Superword Level Parallelism ; une technique de vectorisation). Puis, nous proposons une nouvelle méthodologie permettant l'application conjointe de la conversion de virgule flottante en virgule fixe et de l'exploitation du SLP. Enfin, nous implémentons cette approche sous forme d'un flot de compilation source-à-source complètement automatisé, afin de valider ces travaux. Les résultats montrent l'efficacité de cette approche, dans l'exploitation du compromis entre performance et précision, vis-à-vis d'une approche classique considérant ces deux transformations indépendamment
In order to cut-down their cost and/or their power consumption, many embedded processors do not provide hardware support for floating-point arithmetic. However, applications in many domains, such as signal processing, are generally specified using floating-point arithmetic for the sake of simplicity. Porting these applications on such embedded processors requires a software emulation of floating-point arithmetic, which can greatly degrade performance. To avoid this, the application is converted to use fixed-point arithmetic instead. Floating-point to fixed-point conversion involves a subtle tradeoff between performance and precision ; it enables the use of narrower data word lengths at the cost of degrading the computation accuracy. Besides, most embedded processors provide support for SIMD (Single Instruction Multiple Data) as a mean to improve performance. In fact, this allows the execution of one operation on multiple data in parallel, thus ultimately reducing the execution time. However, the application should usually be transformed in order to take advantage of the SIMD instruction set. This transformation, known as Simdization, is affected by the data word lengths ; narrower word lengths enable a higher SIMD parallelism rate. Hence the tradeoff between precision and Simdization. Many existing work aimed at provide/improving methodologies for automatic floating-point to fixed-point conversion on the one side, and Simdization on the other. In the state-of-the-art, both transformations are considered separately even though they are strongly related. In this context, we study the interactions between these transformations in order to better exploit the performance/accuracy tradeoff. First, we propose an improved SLP (Superword Level Parallelism) extraction (an Simdization technique) algorithm. Then, we propose a new methodology to jointly perform floating-point to fixed-point conversion and SLP extraction. Finally, we implement this work as a fully automated source-to-source compiler flow. Experimental results, targeting four different embedded processors, show the validity of our approach in efficiently exploiting the performance/accuracy tradeoff compared to a typical approach, which considers both transformations independently
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Psiakis, Rafail. "Performance optimization mechanisms for fault-resilient VLIW processors." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S095/document.

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Les processeurs intégrés dans des domaines critiques exigent une combinaison de fiabilité, de performances et de faible consommation d'énergie. Very Large Instruction Word (VLIW) processeurs améliorent les performances grâce à l'exploitation ILP (Instruction Level Parallelism), tout en maintenant les coûts et la puissance à un niveau bas. L’ILP étant fortement dépendant de l'application, le processeur n'utilise pas toutes ses ressources en permanence et ces ressources peuvent donc être utilisées pour l'exécution d'instructions redondantes. Cette thèse présente une méthodologie d’injection fautes pour processeurs VLIW et trois mécanismes matériels pour traiter les pannes légères, permanentes et à long terme menant à trois contributions.La première contribution présente un schéma d’analyse du facteur de vulnérabilité architecturale et du facteur de vulnérabilité d’instruction pour les processeurs VLIW. Une méthodologie d’injection de fautes au niveau de différentes structures de mémoire est proposée pour extraire les capacités de masquage architecture / instruction du processeur. Un schéma de classification des défaillances de haut niveau est présenté pour catégoriser la sortie du processeur. La deuxième contribution explore les ressources inactives hétérogènes au moment de l'exécution, à l'intérieur et à travers des ensembles d'instructions consécutifs. Pour ce faire, une technique d’ordonnancement des instructions optimisée pour le matériel est appliquée en parallèle avec le pipeline afin de contrôler efficacement la réplication et l’ordonnancement des instructions. Suivant les tendances à la parallélisation croissante, une conception basée sur les clusters est également proposée pour résoudre les problèmes d’évolutivité, tout en maintenant une pénalité surface/énergie raisonnable. La technique proposée accélère la performance de 43,68% avec une surcoût en surface et en énergie de ~10% par rapport aux approches existantes. Les analyses AVF et IVF évaluent la vulnérabilité du processeur avec le mécanisme proposé.La troisième contribution traite des défauts persistants. Un mécanisme matériel est proposé, qui réplique au moment de l'exécution les instructions et les planifie aux emplacements inactifs en tenant compte des contraintes de ressources. Si une ressource devient défaillante, l'approche proposée permet de relier efficacement les instructions d'origine et les instructions répliquées pendant l'exécution. Les premiers résultats de performance d’évaluation montrent un gain de performance jusqu’à 49% sur les techniques existantes.Afin de réduire davantage le surcoût lié aux performances et de prendre en charge l’atténuation des erreurs uniques et multiples sur les transitoires de longue durée (LDT), une quatrième contribution est présentée. Nous proposons un mécanisme matériel qui détecte les défauts toujours actifs pendant l'exécution et réorganise les instructions pour utiliser non seulement les unités fonctionnelles saines, mais également les composants sans défaillance des unités fonctionnelles concernées. Lorsque le défaut disparaît, les composants de l'unité fonctionnelle concernés peuvent être réutilisés. La fenêtre de planification du mécanisme proposé comprend deux ensembles d'instructions pouvant explorer des solutions d'atténuation lors de l'exécution de l'instruction en cours et de l'instruction suivante. Les résultats obtenus sur l'injection de fautes montrent que l'approche proposée peut atténuer un grand nombre de fautes avec des performances, une surface et une surcharge de puissance faibles
Embedded processors in critical domains require a combination of reliability, performance and low energy consumption. Very Long Instruction Word (VLIW) processors provide performance improvements through Instruction Level Parallelism (ILP) exploitation, while keeping cost and power in low levels. Since the ILP is highly application dependent, the processor does not use all its resources constantly and, thus, these resources can be utilized for redundant instruction execution. This thesis presents a fault injection methodology for VLIW processors and three hardware mechanisms to deal with soft, permanent and long-term faults leading to three contributions. The first contribution presents an Architectural Vulnerability Factor (AVF) and Instruction Vulnerability Factor (IVF) analysis schema for VLIW processors. A fault injection methodology at different memory structures is proposed to extract the architectural/instruction masking capabilities of the processor. A high-level failure classification schema is presented to categorize the output of the processor. The second contribution explores heterogeneous idle resources at run-time both inside and across consecutive instruction bundles. To achieve this, a hardware optimized instruction scheduling technique is applied in parallel with the pipeline to efficiently control the replication and the scheduling of the instructions. Following the trends of increasing parallelization, a cluster-based design is also proposed to tackle the issues of scalability, while maintaining a reasonable area/power overhead. The proposed technique achieves a speed-up of 43.68% in performance with a ~10% area and power overhead over existing approaches. AVF and IVF analysis evaluate the vulnerability of the processor with the proposed mechanism.The third contribution deals with persistent faults. A hardware mechanism is proposed which replicates at run-time the instructions and schedules them at the idle slots considering the resource constraints. If a resource becomes faulty, the proposed approach efficiently rebinds both the original and replicated instructions during execution. Early evaluation performance results show up to 49\% performance gain over existing techniques.In order to further decrease the performance overhead and to support single and multiple Long-Duration Transient (LDT) error mitigation a fourth contribution is presented. We propose a hardware mechanism, which detects the faults that are still active during execution and re-schedules the instructions to use not only the healthy function units, but also the fault-free components of the affected function units. When the fault faints, the affected function unit components can be reused. The scheduling window of the proposed mechanism is two instruction bundles being able to explore mitigation solutions in the current and the next instruction execution. The obtained fault injection results show that the proposed approach can mitigate a large number of faults with low performance, area, and power overhead
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Dawson, Yvette Eileen Alice 1958. "The impact of the use of word processors on third semester Spanish students at the University of Arizona." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276895.

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In this study, the effect of the word processor on third semester Spanish students at the University of Arizona was examined. The study was performed over two semesters, using a control and an experimental group each time. The communicative language approach for second language learning was implemented in a cooperative learning environment for both control and experimental groups. Control groups used paper and pencil to write their class essays and experimental groups used the word processor. The experimental groups outperformed the control groups. The semester variable by itself was also significant. However, there was no significant interaction between group and semester. Replication studies are needed to validate the results of this study.
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Gammon, J. "An investigation into the use of word processors in the teaching of modern languages at a tertiary college." Thesis, University of Surrey, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383517.

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Elza, Dethe. "Browser evolution document access on the World Wide Web." Ohio : Ohio University, 1998. http://www.ohiolink.edu/etd/view.cgi?ohiou1176833339.

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Bobrow, Barbara Creighton. "The impact of a word processor as a tool in the remediation of learning disabled elementary school children /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63128.

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Books on the topic "Word processors"

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Card, Michael. Interfacing word processors and phototypesetters. London: Blueprint, 1987.

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Proofreading and editing for word processors. New York: Arco Pub., 1985.

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Layman, Katie. Word processing exercises for word processors, microcomputers, and electronic typewriters. 2nd ed. Englewood Cliffs, N.J: Prentice Hall, 1988.

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Tait, Debra J. Wang word processing companion. Bowie, MD: Brady Communications Co., 1985.

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Kanō, Takashi. Wāpuro shinjidai: Haiteku shakai tekiō no tame no tsūru. Tōkyō: Aoba Shuppan, 1985.

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Conlin, Jean M. Word processing training on the Wang. Englewood Cliffs, N.J: Prentice-Hall, 1985.

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Chaban, Jane E. Wang word processing training program. Englewood Cliffs, NJ: Prentice-Hill, 1986.

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Wang word processing training program. Englewood Cliffs: Prentice-Hall, 1986.

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Baumann, Mary. Legal keyboarding: Typewriters, electronic typewriters, and word processors. New York: J. Wiley, 1985.

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Chalton, S. N. L. Computers and word processors in a solicitor's office. 3rd ed. Guilford: College of Law, 1985.

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Book chapters on the topic "Word processors"

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Lee, Ruby B., Xiao Yang, and Zhijie Jerry Shi. "Validating Word-Oriented Processors for Bit and Multi-word Operations." In Advances in Computer Systems Architecture, 473–88. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30102-8_40.

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Scott, Mary. "Written English, Word-Processors, and Meaning-Making." In Studies in Writing, 163–76. Dordrecht: Springer Netherlands, 2001. http://dx.doi.org/10.1007/978-94-010-0734-4_9.

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Strobbe, Christophe, Bert Frees, and Jan Engelen. "Accessibility Evaluation for Open Source Word Processors." In Lecture Notes in Computer Science, 575–83. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-25364-5_40.

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Baldwin, Ann. "Authors not Victims: Writing with Word Processors." In Children with Literacy Difficulties, 99–111. London: Routledge, 2021. http://dx.doi.org/10.4324/9781003252726-9.

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Catthoor, Francky, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Angeliki Kritikakou, and Javed Absar. "Exploiting Word-Width Information During Mapping." In Ultra-Low Energy Domain-Specific Instruction-Set Processors, 223–73. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9528-2_9.

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Jayapala, Murali, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, and Henk Corporaal. "A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors." In Lecture Notes in Computer Science, 258–67. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45716-x_26.

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Weik, Martin H. "word processor." In Computer Science and Communications Dictionary, 1930. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_21187.

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Anesa, Patrizia. "Word-formation processes." In Lexical Innovation in World Englishes, 45–52. London ; New York, NY : Routledge, 2018. | Series: Routledge focus on linguistics: Routledge, 2018. http://dx.doi.org/10.4324/9781351109352-4.

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Hughes, Ron. "Introducing the Word Processor." In Word Processing with Amstrad, 1–7. London: Macmillan Education UK, 1986. http://dx.doi.org/10.1007/978-1-349-09082-2_1.

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Hughes, Ron. "LocoScript, the Word Processor." In Word Processing with Amstrad, 56–123. London: Macmillan Education UK, 1986. http://dx.doi.org/10.1007/978-1-349-09082-2_3.

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Conference papers on the topic "Word processors"

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Van Lancker, Dwight, Niels Van Durme, Eveline Vlassenroot, Raf Buyle, Peter Mechant, Pieter Colpaert, and Erik Mannens. "Integrating OSLO semantics in word processors." In ICEGOV 2022: 15th International Conference on Theory and Practice of Electronic Governance. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3560107.3560120.

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Oliver, John, Venkatesh Akella, and Frederic Chong. "Efficient orchestration of sub-word parallelism in media processors." In the sixteenth annual ACM symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1007912.1007946.

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Molina, Martin, and Gemma Blasco. "Human-Readable and Machine-Readable Knowledge Bases Using Specialized Word Processors." In 2008 20th IEEE International Conference on Tools with Artificial Intelligence (ICTAI). IEEE, 2008. http://dx.doi.org/10.1109/ictai.2008.33.

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Pang, Long, Ao Li, Yinan Zhou, Chen Yang, Yizhuang Xie, and He Chen. "Word length Optimization Method for Radix-2k Fixed-Point Pipeline FFT Processors." In 2019 IEEE International Conference on Signal, Information and Data Processing (ICSIDP). IEEE, 2019. http://dx.doi.org/10.1109/icsidp47821.2019.9173398.

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Fryza, Tomas, and Roman Mego. "Instruction-level programming approach for very long instruction word digital signal processors." In 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2017. http://dx.doi.org/10.1109/icecs.2017.8292060.

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Lee, Hae-Na, Vikas Ashok, and I. V. Ramakrishnan. "Repurposing Visual Input Modalities for Blind Users: A Case Study of Word Processors." In 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC). IEEE, 2020. http://dx.doi.org/10.1109/smc42975.2020.9283015.

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Masselos, K., F. Catthoor, C. E. Goutis, and H. DeMan. "Interaction between sub-word parallelism exploitation and low power code transformations for VLIW multi-media processors." In Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design. IEEE, 1999. http://dx.doi.org/10.1109/lpd.1999.750403.

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Raza, Muhammad Usman, Larry Q. Tran, Giang-Huong Nguyen, Danh Tran, Dennis Lam, and Richard H. Livengood. "Memory Array Debug Strategies using FIB Assisted Milling." In ISTFA 2022. ASM International, 2022. http://dx.doi.org/10.31399/asm.cp.istfa2022p0179.

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Abstract Modern processors rely heavily on memory arrays close to the logical processers to have minimal latencies and highest bandwidth for optimal performance. There are memory arrays in the client and server which are configured to different levels based on the size and latency required for the tasks. These memory arrays are separated into bit lines and word lines to address single bits and retrieve required data from the address of the memory location. In any new server validation, a memory access error can happen if the logical to physical memory address is not confirmed. This can lead to corrupt data and operation failure. We have employed here, novel targeted Focused Ion Beam (FIB) milling techniques for Logical to Physical (L2P) memory addressing validation and correction.
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Kamitani, Takayuki, and Yoji Marutani. "Analysis of perplexing situations in word processor work using facial image sequence." In Electronic Imaging '97, edited by Bernice E. Rogowitz and Thrasyvoulos N. Pappas. SPIE, 1997. http://dx.doi.org/10.1117/12.274528.

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Page, Stanley R., Todd J. Johnsgard, Uhl Albert, and C. Dennis Allen. "User customization of a word processor." In the SIGCHI conference. New York, New York, USA: ACM Press, 1996. http://dx.doi.org/10.1145/238386.238541.

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Reports on the topic "Word processors"

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Fenske, K. R. Survey of ANL organization plans for word processors, personal computers, workstations, and associated software. Office of Scientific and Technical Information (OSTI), November 1991. http://dx.doi.org/10.2172/6253722.

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Fenske, K. R., and V. S. Rockwell. Survey of ANL organization plans for word processors, personal computers, workstations, and associated software. Office of Scientific and Technical Information (OSTI), August 1992. http://dx.doi.org/10.2172/6855384.

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Fenske, K. R. Survey of ANL organization plans for word processors, personal computers, workstations, and associated software. Revision 3. Office of Scientific and Technical Information (OSTI), November 1991. http://dx.doi.org/10.2172/10103346.

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Fenske, K. R., and V. S. Rockwell. Survey of ANL organization plans for word processors, personal computers, workstations, and associated software. Revision 4. Office of Scientific and Technical Information (OSTI), August 1992. http://dx.doi.org/10.2172/10104904.

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Marcot, Bruce G. Ecosystem processes related to wood decay. Portland, OR: U.S. Department of Agriculture, Forest Service, Pacific Northwest Research Station, 2017. http://dx.doi.org/10.2737/pnw-rn-576.

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Marcot, Bruce G. Ecosystem processes related to wood decay. Portland, OR: U.S. Department of Agriculture, Forest Service, Pacific Northwest Research Station, 2017. http://dx.doi.org/10.2737/pnw-rn-576.

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Handley, Holly A., and Nancy J. Heacox. Including Organizational Cultural Parameters in Work Processes. Fort Belvoir, VA: Defense Technical Information Center, June 2004. http://dx.doi.org/10.21236/ada465773.

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Steger, Paul. An Analysis of Kindergarten Children's Use of a Word Processor in Their Print Literacy Development. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.1145.

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Kvalbein, Astrid. Wood or blood? Norges Musikkhøgskole, August 2018. http://dx.doi.org/10.22501/nmh-ar.481278.

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Wood or Blood? New scores and new sounds for voice and clarinet Astrid Kvalbein and Gjertrud Pedersen, Norwegian Academy of Music What is this thing called a score, and how do we relate to it as performers, in order to realize a musical work? This is the fundamental question of this exposition. As a duo we have related to scores in a variety of ways over the years: from the traditional reading and interpreting of sheet music of works by distant (some dead) composers, to learning new works in dialogue with living composers and to taking part in the creative processes from the commissioning of a work to its premiere and beyond. This reflective practice has triggered many questions: could the score for instance be conceptualized as a contract, in which some elements are negotiable and others are not? Where two equal parts, the performer(s) and the composer might have qualitatively different assignments on how to realize the music? Finally: might reflecting on such questions influence our interpretative practices? To shed light on these issues, we take as examples three works from our recent repertoire: Ragnhild Berstad’s Vevtråd (Weaving thread, 2010), Jan Martin Smørdal’s The Lesser Nighthawk (2012) and Lene Grenager’s Tre eller blod (Wood or blood, 2005). We will share – attempt to unfold – some of the experiences gained from working with this music, in close collaboration and dialogue with the composers. Observing the processes from a certain temporal distance, we see how our attitudes as a duo has developed over a longer span of time, into a more confident 'we'.
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Alberts, Chris, Audrey Dorofee, Georgia Killcrece, Robin Ruefle, and Mark Zajicek. Defining Incident Management Processes for CSIRTs: A Work in Progress. Fort Belvoir, VA: Defense Technical Information Center, October 2004. http://dx.doi.org/10.21236/ada453378.

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