Relevant bibliographies by topics / Worst Case Circuit Analysis

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Worst Case Circuit Analysis'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Worst Case Circuit Analysis"

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ANTREICH, KURT J., HELMUT E. GRAEB, and CLAUDIA U. WIESER. "PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 04, no. 03 (September 1993): 261–82. http://dx.doi.org/10.1142/s0129156493000121.

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Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.
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Wei Tian, Xie-Ting Ling, and Ruey-Wen Liu. "Novel methods for circuit worst-case tolerance analysis." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 43, no. 4 (April 1996): 272–78. http://dx.doi.org/10.1109/81.488806.

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Latorre, Vittorio, Husni Habal, Helmut Graeb, and Stefano Lucidi. "Derivative free methodologies for circuit worst case analysis." Optimization Letters 13, no. 7 (December 12, 2018): 1557–71. http://dx.doi.org/10.1007/s11590-018-1364-5.

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CIJAN, GREGOR, TADEJ TUMA, and ÁRPÁD BŰRMEN. "A DIRECT SEARCH METHOD FOR WORST CASE ANALYSIS AND YIELD OPTIMIZATION OF INTEGRATED CIRCUITS." Journal of Circuits, Systems and Computers 18, no. 07 (November 2009): 1185–204. http://dx.doi.org/10.1142/s0218126609005617.

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Yield maximization is an important aspect in the design of integrated circuits. A prerequisite for its automation is a reliable and fast worst performance analysis which results in corners that can be used in the process of circuit optimization. We formulate the constrained optimization problem for finding the worst performance of an integrated circuit and develop a direct search method for solving it. The algorithm uses radial steps and rotations for enforcing the inequality constraint. We demonstrate the performance of the proposed algorithm on real world design examples of integrated circuits. The results indicate that the algorithm solves the worst performance problem in an efficient manner. The proposed algorithm was also successfully used in the process of yield maximization, resulting in a 99.65% yield.
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Antreich, K. J., H. E. Graeb, and C. U. Wieser. "Circuit analysis and optimization driven by worst-case distances." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 1 (1994): 57–71. http://dx.doi.org/10.1109/43.273749.

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Dharchoudhury, A., and S. M. Kang. "Worst-case analysis and optimization of VLSI circuit performances." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 4 (April 1995): 481–92. http://dx.doi.org/10.1109/43.372370.

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Trinchero, Riccardo, Paolo Manfredi, Tongyu Ding, and Igor S. Stievano. "Combined Parametric and Worst Case Circuit Analysis via Taylor Models." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 7 (July 2016): 1067–78. http://dx.doi.org/10.1109/tcsi.2016.2546389.

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Schenk, Mario, Annette Muetze, Klaus Krischan, and Christian Magele. "Worst-case analysis of electronic circuits based on an analytic forward solver approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 5 (September 2, 2019): 1655–66. http://dx.doi.org/10.1108/compel-12-2018-0531.

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Purpose The purpose of this paper is to evaluate the worst-case behavior of a given electronic circuit by varying the values of the components in a meaningful way in order not to exceed pre-defined currents or voltages limits during a transient operation. Design/methodology/approach An analytic formulation is used to identify the time-dependent solution of voltages or currents using proper state equations in closed form. Circuits with linear elements can be described by a system of differential equations, while circuits composing nonlinear elements are described by piecewise-linear models. A sequential quadratic program (SQP) is used to find the worst-case scenario. Findings It is found that the worst-case scenario can be obtained with as few solutions to the forward problem as possible by applying an SQP method. Originality/value The SQP method in combination with the analytic forward solver approach shows that the worst-case limit converges in a few steps even if the worst-case limit is not on the boundary of the parameters.
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BALLAY, N., and B. BAYLAC. ""WCAP" : WORST CASE ANALYSIS PROGRAM : A TOOL FOR STATISTICAL CIRCUIT SIMULATION." Le Journal de Physique Colloques 49, no. C4 (September 1988): C4–269—C4–273. http://dx.doi.org/10.1051/jphyscol:1988456.

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Femia, N., and G. Spagnuolo. "Genetic optimization of interval arithmetic-based worst case circuit tolerance analysis." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 46, no. 12 (1999): 1441–56. http://dx.doi.org/10.1109/81.809546.

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Dissertations / Theses on the topic "Worst Case Circuit Analysis"

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Cakir, Sinan. "Tolerance Based Reliability Of An Analog Electric Circuit." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12612929/index.pdf.

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This thesis deals with the reliability analysis of a fuel pump driver circuit (FPDC), which regulates the amount of fuel pumped to a turbojet engine. Reliability analysis in such critical circuits has great importance since unexpected failures may cause serious financial loss and even human death. In this study, two types of reliability analysis are used: &ldquo
Worst Case Circuit Tolerance Analysis&rdquo
(WCCTA) and &ldquo
Failure Modes and Effects Analysis&rdquo
(FMEA). WCCTA involves the analysis of the circuit operation under varying parameters in their tolerance bands. These parameters include the resistances of the resistors, operating temperature and voltage input value. The operation of FPDC is checked and the most critical parameters are determined in the worst case conditions. While performing WCCTA, a method that guarantees the exact worst case conditions is used rather than probabilistic methods like Monte Carlo analysis. The results showed that the parameter variations do not affect the circuit operation unfavorably
operating temperature, voltage input variation and tolerance bands for the resistances are fairly compatible with the circuit operation. FMEA is implemented according to the short circuit and open circuit failures of all the electronic components used in FPDC. The components whose failure has catastrophic effect on the circuit operation have been determined and some preventive actions have been offered for some catastrophic failures.
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Lingasubramanian, Karthikeyan. "Probabilistic Error Analysis Models for Nano-Domain VLSI Circuits." Scholar Commons, 2010. https://scholarcommons.usf.edu/etd/1699.

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Technology scaling to the nanometer levels has paved the way to realize multi-dimensional applications in a single product by increasing the density of the electronic devices on integrated chips. This has naturally attracted a wide variety of industries like medicine, communication, automobile, defense and even house-hold appliance, to use high speed multi-functional computing machines. Apart from the advantages of these nano-domain computing devices, their usage in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for comprehensive error analysis to enhance their reliability. Moreover, these nano-electronic devices have increased propensity to transient errors due to extremely small device dimensions and low switching energy. The nature of these transient errors is more probabilistic than deterministic, and so requires probabilistic models for estimation and analysis. In this dissertation, we present comprehensive analytic studies of error behavior in nano-level digital logic circuits using probabilistic reliability models. It comprises the design of exact probabilistic error models, to compute the maximum error over all possible input space in a circuit-specific manner; to study the behavior of transient errors in sequential circuits; and to achieve error mitigation through redundancy techniques. The model to compute maximum error, also provides the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. The model for sequential logic that can measure the expected output error probability, given a probabilistic input space, can account for both spatial dependencies and temporal correlations across the logic, using a time evolving causal network. For comprehensive error reduction in logic circuits, temporal, spatial and hybrid redundancy models, are implemented. The temporal redundancy model uses the triple temporal redundancy technique that applies redundancy in the input space, spatial redundancy model uses the cascaded triple modular redundancy technique that applies redundancy in the intermediate signal space and the hybrid redundancy techniques encapsulates both temporal and spatial redundancy schemes. All the above studies are performed on standard benchmark circuits from ISCAS and MCNC suites and the subsequent experimental results are obtained. These results clearly encompasses the various aspects of error behavior in nano VLSI circuits and also shows the efficiency and versatility of the probabilistic error models.
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Wang, Wenfei. "Worst-case Analysis of Space Systems." Thesis, University of Exeter, 2011. http://hdl.handle.net/10036/3550.

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Worst-case analysis is one of the most important elements in the verifica-tion and validation process used to ensure the reliable operation of safety-critical systems for defence, aerospace and space applications. In this the-sis, an optimization-based worst-case analysis framework is developed forspace applications. The proposed framework has been applied and success-fully validated on a number of European Space Agency funded researchprojects in the areas of flexible satellites, hypersonic re-entry vehicles, andautonomous rendezvous systems. Firstly, the problem of analyzing the robustness of an Attitude and OrbitalControl Systems (AOCS) for a flexible scientific satellite with a large num-ber of uncertainties is considered. The analysis employs a detailed simula-tion model of a flexible satellite and multivariable controller, together witha number of frequency and time domain performance criteria which arecommonly used by the space industry to verify correct functionality of full-authority multivariable satellite control systems. Second, the flying qualitiesanalysis of a re-entry vehicle is investigated for a number of complex sce-narios involving different types of uncertainties and disturbances. Specificmethods are utilized to deal with analysis problems involving probabilisticuncertainties, physically correlated uncertainties and highly dynamical dis-turbances. In another study, an integrated analytical/optimization-basedanalysis framework is proposed for the robustness analysis of AOCS fora telecoms satellite with flexible appendages. We develop detailed LinearFractional Transformation (LFT)-based models of the uncertainties presentin a modern telecom satellite and apply µ-analysis to these models in or-der to generate robustness guarantees. We validate these models and re-sults by cross-checking them against worst-case analysis results producedby global optimization algorithms applied to the original system model. Fi-nally, the optimization-based framework developed in this thesis is employedto analyze the robustness of the Guidance, Navigation and Control (GNC)system for autonomous spacecraft. This study considers the autonomousrendezvous problem over the terminal flight phase in the presence of a largenumber of realistic parametric uncertainties and a number of safety criteriarelated to the capture specification. An integrated analytical/optimization-based approach was also developed for this problem so that the computa-tional cost of simulation-based analyses can be reduced, through leveragingresults from robust control tools such asµ-analysis. The main contributions of the thesis are (a) to provide convincing demon-strations of the usefulness of optimization-based worst-case analysis on anumber of different space applications, each of which involves highly com-plex simulators developed by leading industrial companies from the Euro-pean Space sector, and (b) to show how optimization-based analysis meth-ods may be combined with analytical tools from robust control theory tocreate a more integrated, efficient and reliable verification and validationprocess for space applications.
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Marref, Amine. "Predicated Worst Case Execution Time Analysis." Thesis, University of York, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.507541.

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Engblom, Jakob. "Processor Pipelines and Static Worst-Case Execution Time Analysis." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2002. http://publications.uu.se/theses/91-554-5228-0/.

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Edgar, Stewart Frederick. "Estimation of worst-case execution time using statistical analysis." Thesis, University of York, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434164.

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Reutemann, Ralf Dieter. "Worst-case execution time analysis for dynamic branch predictors." Thesis, University of York, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.444749.

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Al-Tarawneh, Mutaz. "Worst-case performance analysis of low-power instruction caches /." Available to subscribers only, 2008. http://proquest.umi.com/pqdweb?did=1594486421&sid=9&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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Ermedahl, Andreas. "A Modular Tool Architecture for Worst-Case Execution Time Analysis." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-3502.

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10

Shi, Zhenwu. "Non-worst-case response time analysis for real-time systems design." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51827.

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A real-time system is a system such that the correctness of operations depends not only on the logical results, but also on the time at which these results are available. A fundamental problem in designing real-time systems is to analyze response time of operations, which is defined as the time elapsed from the moment when the operation is requested to the moment when the operation is completed. Response time analysis is challenging due to the complex dynamics among operations. A common technique is to study response time under worst-case scenario. However, using worst-case response time may lead to the conservative real-time system designs. To improve the real-time system design, we analyze the non-worst-case response time of operations and apply these results in the design process. The main contribution of this thesis includes mathematical modeling of real-time systems, calculation of non-worst-case response time, and improved real-time system design. We perform analysis and design on three common types of real-time systems as the real-time computing system, real-time communication network, and real-time energy management. For the real-time computing systems, our non-worst-response time analysis leads a necessary and sufficient online schedulability test and a measure of robustness of real-time systems. For the real-time communication network, our non-worst-response time analysis improves the performance for the model predictive control design based on the real-time communication network. For the real-time energy management, we use the non-worst-case response time to check whether the micro-grid can operate independently from the main grid.
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Books on the topic "Worst Case Circuit Analysis"

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Johanson, Brian. Worst case circuit analysis application guidelines. Rome, NY (P.O. Box 4700, Rome 13442-4700): The Center, 1993.

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Roughgarden, Tim, ed. Beyond the Worst-Case Analysis of Algorithms. Cambridge University Press, 2020. http://dx.doi.org/10.1017/9781108637435.

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Engblom, Jakob. Processor Pipelines & Static Worst-Case Execution Time Analysis. Uppsala Universitet, 2002.

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Ermedahl, Andreas. Modular Tool Architecture for Worst-Case Execution Time Analysis. Uppsala Universitet, 2003.

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Worst case analysis study on forest plantation herbicide use. Ruston, La: K.S. Crump, 1986.

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J, Brenner Martin, and United States. National Aeronautics and Space Administration., eds. A worst-case approach for on-line flutter prediction. [Washington, D.C: National Aeronautics and Space Administration, 1998.

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A worst-case approach for on-line flutter prediction. [Washington, D.C: National Aeronautics and Space Administration, 1998.

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A worst-case approach for on-line flutter prediction. [Washington, D.C: National Aeronautics and Space Administration, 1998.

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J, Brenner Martin, and United States. National Aeronautics and Space Administration., eds. A worst-case approach for on-line flutter prediction. [Washington, D.C: National Aeronautics and Space Administration, 1998.

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United States. National Aeronautics and Space Administration., ed. Worst case analysis: Earth sensor assembly for the Tropical Rainfall Measuring Mission observatory. [Washington, D.C.?: National Aeronautics and Space Administration, 1993.

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Book chapters on the topic "Worst Case Circuit Analysis"

1

Schor, Lars, Hoeseok Yang, Iuliana Bacivarov, and Lothar Thiele. "Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 288–97. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_29.

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Lin, Saihua, and Huazhong Yang. "Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling." In Lecture Notes in Computer Science, 504–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_49.

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Simchi-Levi, David, Xin Chen, and Julien Bramel. "Worst-Case Analysis." In The Logic of Logistics, 65–84. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-9149-1_4.

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Bramel, Julien, and David Simchi-Levi. "Worst-Case Analysis." In The Logic of Logistics, 15–35. New York, NY: Springer New York, 1997. http://dx.doi.org/10.1007/978-1-4684-9309-2_2.

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Antreich, Kurt J., and Helmut E. Graeb. "Circuit Optimization Driven by Worst-Case Distances." In The Best of ICCAD, 585–95. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0292-0_47.

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Marref, Amine, and Guillem Bernat. "Predicated Worst-Case Execution-Time Analysis." In Reliable Software Technologies – Ada-Europe 2009, 134–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-01924-1_10.

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Puffitsch, Wolfgang, Benedikt Huber, and Martin Schoeberl. "Worst-Case Analysis of Heap Allocations." In Lecture Notes in Computer Science, 464–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-16561-0_42.

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Suzuki, Einoshin. "Worst-Case Analysis of Rule Discovery." In Discovery Science, 365–77. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45650-3_31.

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Mosk-Aoyama, Damon, and Tim Roughgarden. "Worst-Case Efficiency Analysis of Queueing Disciplines." In Automata, Languages and Programming, 546–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-02930-1_45.

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Ambainis, Andris, Artūrs Bačkurs, Kaspars Balodis, Agnis Škuškovniks, Juris Smotrovs, and Madars Virza. "Worst Case Analysis of Non-local Games." In Lecture Notes in Computer Science, 121–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-35843-2_12.

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Conference papers on the topic "Worst Case Circuit Analysis"

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Davis, Henry. "Method for Automated Worst Case Circuit Design and Analysis." In SAE 2006 World Congress & Exhibition. 400 Commonwealth Drive, Warrendale, PA, United States: SAE International, 2006. http://dx.doi.org/10.4271/2006-01-0591.

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Sugathan, Reshma, Ananda S, Vinitha Ramdas, P. Satyanarayana, Sankaran M, and Ekkundi R S. "Worst case circuit analysis of a new balancing circuit for spacecraft application." In 2015 International Conference on Power and Advanced Control Engineering (ICPACE). IEEE, 2015. http://dx.doi.org/10.1109/icpace.2015.7274967.

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Durbhakula, Kalyan C., Ahmed M. Hassan, and Anthony N. Caruso. "Worst-Case Coupled Voltage Analysis of Printed Circuit Board Traces." In 2020 XXXIIIrd General Assembly and Scientific Symposium of the International Union of Radio Science (URSI GASS). IEEE, 2020. http://dx.doi.org/10.23919/ursigass49373.2020.9232151.

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Herrmann, Andreas, Christof Hielscher, Alexander Mueller, Gisbert Hoelzer, and Helmut Graeb. "Realistic worst-case parameter sets for MEMS technologies." In 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). IEEE, 2017. http://dx.doi.org/10.1109/smacd.2017.7981594.

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Sang-Hoon Lee, Kyung-Ho Kim, Jin-Kyu Park, Chang-Hoon Choi, Jeong-Taek Kong, Won-Woo Lee, Wong-Seong Lee, Jei-Hwan Yoo, and Soo-In Cho. "A realistic methodology for the worst case analysis of VLSI circuit performances." In Proceedings of International Conference on Simulation of Semiconductor Processes and Devices. IEEE, 1996. http://dx.doi.org/10.1109/sispad.1996.865318.

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Qian, Liuxi, Dian Zhou, Sheng-Guo Wang, Xuan, and Zeng. "Worst case analysis of linear analog circuit performance based on Kharitonov's rectangle." In 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2010. http://dx.doi.org/10.1109/icsict.2010.5667428.

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Saibua, Siwat, Liuxi Qian, and Dian Zhou. "Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method." In 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2011. http://dx.doi.org/10.1109/vlsisoc.2011.6081660.

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Vudathu, Shyam Praveen, Srikanth Lavu, and Rainer Laur. "Design for Reliability (DfR) in MEMS using Worst-Case Methods." In 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IEEE, 2007. http://dx.doi.org/10.1109/ipfa.2007.4378098.

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Liau, Eric, and Doris Schmitt-Landsiedel. "Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment." In ISTFA 2003. ASM International, 2003. http://dx.doi.org/10.31399/asm.cp.istfa2003p0506.

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Abstract Power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. In this paper, we propose a novel approach based on ATE (automatic test equipment) that teaches neural networks (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as a learning behavior of chip power consumption change due to different input patterns. Then a genetic algorithm (GA) was applied to further optimize this set of NN worst case patterns. A final set of worst case patterns were expected to detect a small critical sequence of high switching currents that was directly related to the worst case power supply noise. This novel diagnosis approach can efficiently identify the defective design or weakness due to PSN as well as locate the defect or weaknesses within the design.
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Mohan, Vineeth, Wenjing Hsu, Wei Zhang, and Xiaowen Wu. "An extended framework for worst-case throughput analysis with router constraint." In 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2014. http://dx.doi.org/10.1109/apccas.2014.7032875.

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Reports on the topic "Worst Case Circuit Analysis"

1

RELIABILITY ANALYSIS CENTER GRIFFISS AFB NY. Worst Case Circuit Analysis Application Guidelines. Fort Belvoir, VA: Defense Technical Information Center, January 1993. http://dx.doi.org/10.21236/ada278216.

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