Journal articles: 'Worst Case Circuit Analysis'

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ANTREICH, KURT J., HELMUT E. GRAEB, and CLAUDIA U. WIESER. "PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 04, no. 03 (September 1993): 261–82. http://dx.doi.org/10.1142/s0129156493000121.

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Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

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Wei Tian, Xie-Ting Ling, and Ruey-Wen Liu. "Novel methods for circuit worst-case tolerance analysis." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 43, no. 4 (April 1996): 272–78. http://dx.doi.org/10.1109/81.488806.

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Latorre, Vittorio, Husni Habal, Helmut Graeb, and Stefano Lucidi. "Derivative free methodologies for circuit worst case analysis." Optimization Letters 13, no. 7 (December 12, 2018): 1557–71. http://dx.doi.org/10.1007/s11590-018-1364-5.

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CIJAN, GREGOR, TADEJ TUMA, and ÁRPÁD BŰRMEN. "A DIRECT SEARCH METHOD FOR WORST CASE ANALYSIS AND YIELD OPTIMIZATION OF INTEGRATED CIRCUITS." Journal of Circuits, Systems and Computers 18, no. 07 (November 2009): 1185–204. http://dx.doi.org/10.1142/s0218126609005617.

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Yield maximization is an important aspect in the design of integrated circuits. A prerequisite for its automation is a reliable and fast worst performance analysis which results in corners that can be used in the process of circuit optimization. We formulate the constrained optimization problem for finding the worst performance of an integrated circuit and develop a direct search method for solving it. The algorithm uses radial steps and rotations for enforcing the inequality constraint. We demonstrate the performance of the proposed algorithm on real world design examples of integrated circuits. The results indicate that the algorithm solves the worst performance problem in an efficient manner. The proposed algorithm was also successfully used in the process of yield maximization, resulting in a 99.65% yield.

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Antreich, K. J., H. E. Graeb, and C. U. Wieser. "Circuit analysis and optimization driven by worst-case distances." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 1 (1994): 57–71. http://dx.doi.org/10.1109/43.273749.

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Dharchoudhury, A., and S. M. Kang. "Worst-case analysis and optimization of VLSI circuit performances." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 4 (April 1995): 481–92. http://dx.doi.org/10.1109/43.372370.

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Trinchero, Riccardo, Paolo Manfredi, Tongyu Ding, and Igor S. Stievano. "Combined Parametric and Worst Case Circuit Analysis via Taylor Models." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 7 (July 2016): 1067–78. http://dx.doi.org/10.1109/tcsi.2016.2546389.

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Schenk, Mario, Annette Muetze, Klaus Krischan, and Christian Magele. "Worst-case analysis of electronic circuits based on an analytic forward solver approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 5 (September 2, 2019): 1655–66. http://dx.doi.org/10.1108/compel-12-2018-0531.

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Purpose The purpose of this paper is to evaluate the worst-case behavior of a given electronic circuit by varying the values of the components in a meaningful way in order not to exceed pre-defined currents or voltages limits during a transient operation. Design/methodology/approach An analytic formulation is used to identify the time-dependent solution of voltages or currents using proper state equations in closed form. Circuits with linear elements can be described by a system of differential equations, while circuits composing nonlinear elements are described by piecewise-linear models. A sequential quadratic program (SQP) is used to find the worst-case scenario. Findings It is found that the worst-case scenario can be obtained with as few solutions to the forward problem as possible by applying an SQP method. Originality/value The SQP method in combination with the analytic forward solver approach shows that the worst-case limit converges in a few steps even if the worst-case limit is not on the boundary of the parameters.

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BALLAY, N., and B. BAYLAC. ""WCAP" : WORST CASE ANALYSIS PROGRAM : A TOOL FOR STATISTICAL CIRCUIT SIMULATION." Le Journal de Physique Colloques 49, no. C4 (September 1988): C4–269—C4–273. http://dx.doi.org/10.1051/jphyscol:1988456.

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Femia, N., and G. Spagnuolo. "Genetic optimization of interval arithmetic-based worst case circuit tolerance analysis." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 46, no. 12 (1999): 1441–56. http://dx.doi.org/10.1109/81.809546.

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Spagnuolo, G., and N. Femia. "True worst-case circuit tolerance analysis using genetic algorithms and affine arithmetic." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 47, no. 9 (2000): 1285–96. http://dx.doi.org/10.1109/81.883323.

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GHEORGHIU, MIHAELA, and JANUSZ BRZOZOWSKI. "SIMULATION OF FEEDBACK-FREE CIRCUITS IN THE ALGEBRA OF TRANSIENTS." International Journal of Foundations of Computer Science 14, no. 06 (December 2003): 1033–54. http://dx.doi.org/10.1142/s0129054103002163.

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An efficient simulation algorithm using an algebra of transients for gate circuits was proposed by Brzozowski and Ésik. This algorithm seems capable of predicting all the signal changes that can occur in a circuit under worst-case delay conditions. We verify this claim by comparing simulation with binary analysis. For any feedback-free circuit consisting of one- and two-input gates, we prove that all signal changes predicted by simulation occur in binary analysis, provided that wire delays are taken into account. Two types of finite automata play an important role in our proof.

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Jin, Song, and Yi Ran Huang. "Analysis and Evaluation on NBTI-Induced Circuit Aging." Applied Mechanics and Materials 513-517 (February 2014): 3976–82. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.3976.

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Aging effects degrade circuit performance with time, inducing reliability problem. Accurate prediction of circuit aging can help designer determine the reasonable design margin, avoiding the over-design of the circuit. Based on the physical understanding of aging mechanism, an analysis framework is proposed to predict NBTI-induced circuit aging. The analysis framework starts at the worst case prediction, which assumes the extremely operational conditions. Then, the impacts of different workloads and logic topology of the circuit on the aging-induced degradation are incorporated into the analysis framework to make the predicted result be closer to the practical scenario. Experimental results demonstrate that the effectiveness of the proposed analysis framework.

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Sahoo, Manodipan, and Hafizur Rahaman. "Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects." Journal of Circuits, Systems and Computers 26, no. 06 (March 5, 2017): 1750102. http://dx.doi.org/10.1142/s021812661750102x.

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Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11[Formula: see text]nm and 8[Formula: see text]nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1[Formula: see text]mm long intermediate interconnects and less than 7% of that of copper interconnects for 5[Formula: see text]mm long global interconnects at 8[Formula: see text]nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology.

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Nassif, S. R., A. J. Strojwas, and S. W. Director. "A Methodology for Worst-Case Analysis of Integrated Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 1 (January 1986): 104–13. http://dx.doi.org/10.1109/tcad.1986.1270181.

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Jone, W. B., D. C. Huang, S. C. Chang, and S. R. Das. "Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis." VLSI Design 12, no. 4 (January 1, 2001): 457–74. http://dx.doi.org/10.1155/2001/28741.

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Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits. Although the defect level estimation for pseudorandom testing has been performed using sequential statical analysis, no closed form can be accomplished as complex combinatorial enumerations are involved. In this work, a Markov model is employed to describe the pseudorandom test behaviors. For the first time, a closed form of the defect level equation is derived by solving the differential equation extracted from the Markov model. The defect level equation clearly describes the relationships among defect level, fabrication yield, the number of all input combinations, circuit detectability (in terms of the worst single stuck-at fault), and pseudorandom test length. The Markov model is then extended to consider all single stuck-at faults, instead of only the worst single stuck-at fault. Results demonstrate that the defect level analysis for pseudorandom testing by only dealing with the worst single stuck-at fault is not adequate (In fact, the worst single stuck-at fault analysis is just a special case). A closed form of the defect level equation is successfully derived to incorporate all single stuck-at faults into consideration. Although our discussions are primarily based on the single struck-at fault model, it is not difficult to extend the results to other fault types.

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Matarrese, G., C. Marzocca, and F. Corsi. "Fast and realistic worst case analysis of CMOS integrated circuits." Electronics Letters 37, no. 6 (2001): 350. http://dx.doi.org/10.1049/el:20010254.

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DJAHANSHAHI, HORMOZ, MAJID AHMADI, GRAHAM A. JULLIEN, and WILLIAM C. MILLER. "A LOW-VARIATION NONLINEAR NEURON CIRCUIT." Journal of Circuits, Systems and Computers 08, no. 04 (August 1998): 447–51. http://dx.doi.org/10.1142/s0218126698000249.

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A resistive-type neuron circuit is presented that combines nonlinear characteristics of four MOS transistors to realize a saturating function. Despite circuit simplicity, characteristic variations are found to be small based on circuit analyses and fabrication measurements. Maximum variation between neurons within one chip is 1.3%, while worst-case chip-to-chip variation from 10 fabrications is 2.2%.

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Tian, M. W., and R. C. J. Shi. "Worst case tolerance analysis of linear analog circuits using sensitivity bands." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 47, no. 8 (2000): 1138–45. http://dx.doi.org/10.1109/81.873869.

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Kolev, L. "Worst-case tolerance analysis of linear DC and AC electric circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 49, no. 12 (December 2002): 1693–701. http://dx.doi.org/10.1109/tcsi.2002.805700.

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Wan, Lu, and Deming Chen. "Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 5 (May 2012): 662–75. http://dx.doi.org/10.1109/tcad.2011.2181512.

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Bu, Aiguo, and Jie Li. "A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction." Electronics 9, no. 11 (November 22, 2020): 1976. http://dx.doi.org/10.3390/electronics9111976.

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Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

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Arunachalam, Ravishankar, Ronald DeShawn Blanton, and Lawrence T. Pileggi. "Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation." VLSI Design 15, no. 3 (January 1, 2002): 605–18. http://dx.doi.org/10.1080/1065514021000012228.

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Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. The impact of this switching on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. Apart from the delay modeling inaccuracies, the temporal and functional isolation of the aggressors can contribute to the pessimism. This paper introduces TACO, a timing analysis approach that addresses both these issues. TACO captures the provably worst-and best-case delays as a function of the timing-window inputs to the gates. We then present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. Results on industrial examples and benchmark circuits show the value of our approach.

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BORAGE, MANGESH, SUNIL TIWARI, and SWARNA KOTAIAH. "COMPONENT TOLERANCE ANALYSIS OF A PARALLEL RESONANT MAGNET EXCITATION SCHEME FOR RAPID CYCLING SYNCHROTRON USING PSpice." Journal of Circuits, Systems and Computers 14, no. 03 (June 2005): 439–52. http://dx.doi.org/10.1142/s0218126605002416.

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The parallel resonant scheme used to excite the magnets is characterized with high quality factor. The characteristic steep slope of the network gain near the resonant frequency makes the performance susceptible to the changes in component values. To accommodate the effect of varying component values, appropriate amplitude and phase over-drive capabilities in the ac source are required to maintain the magnet current of desired amplitude and in desired phase. A method of analysis of component tolerances using general purpose circuit simulation software, PSpice, is proposed in this letter. Using proposed normalized circuit description of the parallel resonant scheme, worst-case combination of component tolerances is determined. The evaluation of the effect of component tolerances in terms of required magnitude and phase over-drive of the ac source is presented under illustrative circuit conditions. Effect of various parameters on the over-drive is examined.

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Korkosz, Mariusz, Jan Prokop, Bartlomiej Pakla, Grzegorz Podskarbi, and Piotr Bogusz. "Analysis of Open-Circuit Fault in Fault-Tolerant BLDC Motors with Different Winding Configurations." Energies 13, no. 20 (October 13, 2020): 5321. http://dx.doi.org/10.3390/en13205321.

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In this study, tests were carried out on a brushless permanent magnet DC motor with different winding configurations. Three configurations were compared: star, delta and combined star–delta. A mathematical model was constructed for the motor, taking into account the different winding configurations. An analysis of the operation of the motor in the different configurations was performed, based on numerical calculations. The use of different winding configurations affects the properties of the motor. This is significant in the case of the occurrence of various fault states. Based on numerical calculations, an analysis of an open-circuit fault in one of the phases of the motor was performed. Fast Fourier Transform—FFT analysis of the artificial neutral-point voltage was used for the detection of fault states. The results were verified by tests carried out under laboratory conditions. It was shown that the winding configuration has an impact on the behaviour of the motor in the case of an open circuit in one of the phases. The classical star configuration is the worst of the possible arrangements. The most favourable in this respect is the delta configuration. In the case of the combined star–delta configuration, the consequences of the fault depend on the location of the open circuit.

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Sampaio, Carlos, José Monteiro, and L. Miguel Silveira. "Analysis of the conditions for the worst case switching activity in integrated circuits." Analog Integrated Circuits and Signal Processing 70, no. 2 (September 24, 2011): 229–40. http://dx.doi.org/10.1007/s10470-011-9782-7.

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Abderrahman, A., E. Cerny, and B. Kaminska. "Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, no. 3 (March 1999): 332–45. http://dx.doi.org/10.1109/43.748163.

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Ferber, Moises, Anton Korniienko, Gerard Scorletti, Christian Vollaire, Florent Morel, and Laurent Krahenbuhl. "Systematic LFT Derivation of Uncertain Electrical Circuits for the Worst-Case Tolerance Analysis." IEEE Transactions on Electromagnetic Compatibility 57, no. 5 (October 2015): 937–46. http://dx.doi.org/10.1109/temc.2015.2419455.

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Saha, Aloke, Sushil Kumar, Debajit Das, and Mrinmoy Chakraborty. "LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology." International Journal of High Speed Electronics and Systems 26, no. 04 (December 2017): 1740024. http://dx.doi.org/10.1142/s0129156417400249.

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Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage Temperature) variations on LP-HS XOR circuit. The worst case delay and PDP variation is recorded. Finally the 8:1 Multiplexer is designed, optimized and evaluated based on LP-HS Logic. The evaluated results are compared with some recent competitive designs to benchmark. To resolve reliability issue the corner analysis with PVT variation has been performed on designed 8:1 Multiplexor circuit. All the simulations are done on TSMC 0.18μm CMOS technology using Tanner EDA V.13 at 25°C temperature with 1.8V supply rail.

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PEHL, MICHAEL, and HELMUT GRAEB. "TOLERANCE DESIGN OF ANALOG CIRCUITS USING A BRANCH-AND-BOUND BASED APPROACH." Journal of Circuits, Systems and Computers 21, no. 08 (December 2012): 1240022. http://dx.doi.org/10.1142/s0218126612400221.

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The design of circuits which are robust against variations in operating and process conditions is crucial in today's IC industry. In the analog design flow this problem can be tackled during the sizing of a new circuit. However, hardly any methods are available which support the designer to compute such a robust design if discrete parameters should be considered in this design step. Discrete parameters arise predominantly if a layout-friendly sizing should be computed in the sense that, e.g., a manufacturing grid for the transistor lengths and widths is considered or that transistor multipliers are used to allow the layout of a transistor as multifinger or common centroid structure without applying rounding operations to the carefully computed sizing. This paper presents a new Branch-and-Bound based approach which allows the automatic computation of a robust design using classical and realistic worst case analysis. The results of the sizing of three circuits show that the new approach is highly efficient. The robustness of the results computed by the new approach is validated by Monte Carlo analyses.

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Styslo, Bohdan, Roman Zaitsev, Kseniia Minakova, Mykhailo Kirichenko, and Oleksandr Eresko. "ANALYSIS OF BATTERIES ACTIVE BALANCE SCHEMES EFFICIENCY." Bulletin of the National Technical University «KhPI» Series: New solutions in modern technologies, no. 2(8) (June 15, 2021): 38–45. http://dx.doi.org/10.20998/2413-4295.2021.02.06.

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The paper reviews the existing circuit solutions of devices for balancing electric batteries. The balancing principle on the basis of capacitive and inductive buffer elements has been described. It was shown the features of their work and the basic calculations for each device type. For circuits with transformer topology, the calculated values for determining the balancing current are indicated. Based on the circuit solutions analysis, the efficiency of using solutions based on inductive buffer elements is numerically determined and proved. Powerful batteries for power supply systems are used in the form of stacks, consisting of a series-parallel connection of single cells. During their operation, there is a problem of uneven discharge or charge, to compensate which it is necessary to make voltage levels balancing in the stack batteries. For safely using electrochemical batteries the using of specialized balancing devices is required. The most efficient, from an energy point of view, are active balancing systems. The analysis of the mathematical model of two types (capacitive and inductive) buffer elements operation allowed to give a qualitative assessment of their efficiency. The first, in comparison with inductive - not only have worse energy characteristics, but also do not allow to perform "scaling" of the device without significant complication of the control system. The current amplitude value in circuits with a capacitive buffer element is limited only by the internal parasitic resistances of the circuit elements, therefore, with a relatively large value of imbalance, in circuit elements (including batteries) takes place a significant energy loss in the form of heat which negatively effects on rechargeable battery parameters. The current amplitude value in the circuit based on inductive buffer elements is limited by the inductance value. It can be calculated at the device design stage. In addition, providing the control system with intermittent converter operation allows to reduce switching losses in the circuit power switches and increases the overall operation efficiency. With a large number of batteries (more than three) should be preferred transformer balancing systems, as a special case of inductive topology.

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Kolev, L. V., and M. W. Tian. "Comments on "Worst-case tolerance analysis of linear analog circuits using sensitivity bands" [with reply]." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 48, no. 10 (October 2001): 1265–67. http://dx.doi.org/10.1109/81.956026.

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Kuzichkin, Oleg R., Dmitriy I. Surzhik, Gleb S. Vasiliev, Igor A. Kurilov, and Nikolai V. Dorofeev. "Analysis of Noise Characteristics of Multichannel Systems of the Formation of Signals of Georadars with Synthesized Aperture." Active and Passive Electronic Components 2018 (December 4, 2018): 1–7. http://dx.doi.org/10.1155/2018/9429863.

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The noise characteristics of multichannel systems of forming signals based on hybrid frequency synthesizers with automatic compensation of phase distortions of direct digital synthesizers, which are used in the composition of georadars with synthesized aperture, are investigated. It is established that the phase noise of the output signals of the formers at the 1 kHz detuning from the carrier oscillation at the output frequencies of the devices in the range from 500 to 3500 MHz is characterized by a level of minus 100 - minus 130 dB. In this case, the circuit of the signal former based on a hybrid frequency synthesizer with direct digital synthesizer as a reference oscillator of a phase locked loop is characterized by the worst noise characteristics but with the highest degree of autocompensation (about 13 dB). Conversely, the circuit of the signal former based on a hybrid frequency synthesizer with direct digital synthesizer as a support generator of the phase-locked loop has the best phase noises level from the considered variants of devices and least degree of autocompensation (about 6 dB).

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Cha, Kim, Park, and Choi. "Modeling and Control of Double-Sided LCC Compensation Topology with Semi-Bridgeless Active Rectifier for Inductive Power Transfer System." Energies 12, no. 20 (October 16, 2019): 3921. http://dx.doi.org/10.3390/en12203921.

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This paper proposes the modeling and design of a controller for an inductive power transfer (IPT) system with a semi-bridgeless active rectifier (S-BAR). This system consists of a double-sided Inductor-Capacitor-Capacitor (LCC) compensation network and an S-BAR, and maintains a constant output voltage under load variation through the operation of the rectifier switches. Accurate modeling is essential to design a controller with good performance. However, most of the researches on S-BAR have focused on the control scheme for the rectifier switches and steady-state analysis. Therefore, modeling based on the extended describing function is proposed for an accurate dynamic analysis of an IPT system with an S-BAR. Detailed mathematical analyses of the large-signal model, steady-state operating solution, and small-signal model are provided. Nonlinear large-signal equivalent circuit and linearized small-signal equivalent circuit are presented for intuitive understanding. In addition, worst case condition is selected under various load conditions and a controller design process is provided. To demonstrate the effectiveness of the proposed modeling, experimental results using a 100 W prototype are presented.

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Kersten, Julia, Andreas Rauh, and Harald Aschemann. "Analyzing Uncertain Dynamical Systems after State-Space Transformations into Cooperative Form: Verification of Control and Fault Diagnosis." Axioms 10, no. 2 (May 10, 2021): 88. http://dx.doi.org/10.3390/axioms10020088.

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When modeling real-life applications, uncertainty appears in the form of, for example, modeling approximations, measurement errors, or simply physical restrictions. Those uncertainties can either be treated as stochastic or as bounded, with known limits in the form of intervals. The latter is considered in this paper for a real-life application in the form of an electrical circuit. This is reasonable because the electrical circuit is subject to uncertainties, mainly due to circuit element tolerances and variable load conditions. Since conservative worst-case limits for such parameters are commonly known, interval methods can be applied. The aim of this paper is to demonstrate a possible overall handling of the given uncertain system. Firstly, this includes a control and a reliable computation of the states’ interval enclosures. On the one hand, this can be used to predict the system’s behavior, and on the other hand to verify the control numerically. Here, the implemented feedback control is based on linear matrix inequalities (LMIs) and the states are predicted using an interval enclosure technique based on cooperativity. Since the original system is not cooperative, a transformation is performed. Finally, an observer is implemented as a diagnosis tool regarding faulty measurements or component failures. Since adding a state-of-the-art observer would destroy this structure, a cooperativity-preserving method is applied. Overall, this paper combines methods from robust control design and interval-based evaluations, and presents a suitable observer technique to show the applicability of the presented methods.

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Romaniuk, F. A., E. V. Buloichik, O. A. Huryanchyk, and M. A. Shevaldin. "DETERMINING A TYPE OF A DAMAGE IN THE CURRENT PROTECTION OF POWER LINES OF 6–35 KV." ENERGETIKA. Proceedings of CIS higher education institutions and power engineering associations 60, no. 6 (November 23, 2017): 497–504. http://dx.doi.org/10.21122/1029-7448-2017-60-6-497-504.

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The methods to identify types of phase-to-phase short circuits that can be used to improve technical excellence by speed-current line protection of distribution networks of 6–35 kV are considered. As a result of the assessment of the appropriateness of their application in current protection, the choice was made in favor of the method based on the control of the relative current unbalance. The influence of contact resistances and load currents of various levels on the magnitude and character of the change of relative unbalance taking into account the errors of measuring transformers of current has been studied with the aid of the method of numerical experiment. It is demonstrated that in a lot of cases of arch short circuits in the loaded power line and in idle mode, the control only asymmetry is insufficient for reliable determination of the type of damage. A better algorithm has been proposed for determining phase-to-phase short circuit based on the control and the analysis of the two relative unbalance currents determined by the current values of the differences of the phase currents of the line. Its serviceability was evaluated. It was found out that in all the modes being considered, the proposed method – when boundary conditions are properly chosen – makes it possible to fix three-phase and two-phase short circuit on the protected line, and in the area of remote redundancy. The dynamic properties of the proposed method are investigated for different modes of the line. It is established that in the worst case, the determining of the damage is provided during the time not exceeding 25 ms.

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Suriyamoorthi, Poornapushpakala. "Worst Case Error Budget and Analysis in the Design of a Novel Signal Conditioning Circuit for Eddy Current Flow Meter in Sodium Cooled Fast Breeder Reactor." Indian Journal of Science and Technology 6, no. 11 (November 20, 2013): 1–7. http://dx.doi.org/10.17485/ijst/2013/v6i11.16.

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Noh, Jung-Hun, Seong-il Song, and Deog-Jae Hur. "Numerical Analysis of the Cooling Performance in a 7.2 kW Integrated Bidirectional OBC/LDC Module." Applied Sciences 10, no. 1 (December 30, 2019): 270. http://dx.doi.org/10.3390/app10010270.

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To satisfy increasing demands for ecofriendly vehicles, researchers are now studying electric vehicle (EV)-related technologies. In particular, integrated bidirectional onboard battery charger (OBC)/low-voltage DC–DC converter (LDC) modules are being researched to improve the efficiency of onboard chargers for EV charging applications. In this study, a numerical analysis method is proposed that considers the power loss and heat flow characteristics in the design of a 7.2 kW integrated bidirectional OBC/LDC module. The developed module supports four operating modes depending on the service situation: OBC and LDC single operation, OBC/LDC simultaneous operation, and LDC operation. The mode is selected based on the power system flow. The characteristics of the circuit were analyzed in each of the four modes to compute the heat loss from the major heating elements. The results of a numerical analysis of the internal cooling characteristics showed that the internal temperature was higher in the OBC single operating mode than in the OBC and LDC simultaneous operating mode in which the power loss was the highest. The results emphasize the importance of ensuring that cooling designs consider the characteristics of various modes as well as the worst-case power loss.

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KIM, YOUNG-HO, GERALD E. LOEB, RAYMOND A. PECK, JASSPREET SINGH, SUDEEP DESHPANDE, LUCINDA L. BAKER, and J. TIMOTHY BRYANT. "A FAILURE ANALYSIS OF INTRAMUSCULAR RIGID IMPLANTS FOR MUSCLE CONTRACTIONS." Modern Physics Letters B 22, no. 11 (May 10, 2008): 791–96. http://dx.doi.org/10.1142/s0217984908015395.

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Several studies have been made to develop different versions of new leadless, permanently implanted small electronic devices that allow to be injected into muscles (BIONs™). Their circuitry should be protected from body fluids by thin-walled hermetic capsules of rigid and brittle materials such as glass or ceramic to include feed through for their electrodes. These packages experience repetitive stresses due to the muscle contraction from their excitations. This study provides a worst-case analysis of such stresses and methods to test and validate devices intended for such usage, along with the failure analysis and remediation strategy for a design that experienced unanticipated failures in vivo.

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Jagieła, Mariusz, and Janusz Gwoźdź. "Steady-state time-periodic finite element analysis of a brushless DC motor drive considering motion." Archives of Electrical Engineering 64, no. 3 (September 1, 2015): 471–86. http://dx.doi.org/10.2478/aee-2015-0036.

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Abstract This paper aims at providing a framework for comprehensive steady-state time-domain analysis of rotating machines considering motion. The steady-state waveforms of electromagnetic and circuit quantities are computed via iterative solution of the nonlinear field-circuit-and-motion problem with constraints of time periodicity. The cases with forced speed and forced load torque are considered. A comparison of execution times with a conventional time-stepping transient model is carried out for two different machines. The numerical stability of a time-periodic model with forced speed is shown to be worse than that of traditional transient time-stepping one, although the model converges within a reasonable number of iterations. This is not the case if forced load via equation of mechanical balance is accounted for. To ensure convergence of the iterative process the physical equation of motion is replaced by the fixed-point equation. In this way the model delivers time-periodic solutions regarding not only the electromagnetic quantities but also the rotational speed.

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Fan, Suyan, Man-Kay Law, Mingzhong Li, Zhiyuan Chen, Chio-In Ieong, Pui-In Mak, and Rui P. Martins. "Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell." Journal of Circuits, Systems and Computers 25, no. 01 (November 15, 2015): 1640006. http://dx.doi.org/10.1142/s0218126616400065.

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In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

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Marranghello, Felipe S., André I. Reis, and Renato P. Ribas. "Improving Analytical Delay Modelingfor CMOS Inverters." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 123–34. http://dx.doi.org/10.29292/jics.v10i2.414.

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Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

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Breuer, Rinat, and Itamar Levi. "How Bad Are Bad Templates? Optimistic Design-Stage Side-Channel Security Evaluation and its Cost." Cryptography 4, no. 4 (December 8, 2020): 36. http://dx.doi.org/10.3390/cryptography4040036.

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Cryptographic designs are vulnerable to side-channel analysis attacks. Evaluating their security during design stages is of crucial importance. The latter is achieved by very expensive (slow) analog transient-noise simulations over advanced fabrication process technologies. The main challenge of such rigorous security-evaluation analysis lies in the fact that technologies are becoming more and more complex and the physical properties of manufactured devices vary significantly due to process variations. In turn, a detailed security evaluation process imposes exponential time complexity with the circuit-size, the number of physical implementation corners (statistical variations) and the accuracy of the circuit-simulator. Given these circumstances, what is the cost of not exhausting the entire implementation space? In terms of simulation-time complexity, the benefits would clearly be significant; however, we are interested in evaluating the security implications. This question can be formulated for many other interesting side-channel contexts such as for example, how would an attack-outcome vary when the adversary is building a leakage template over one device, i.e., one physical corner, and it performs an evaluation (attack) phase of a device drawn from a different statistical corner? Alternatively, is it safe to assume that a typical (average) corner would represent the worst case in terms of security evaluation or would it be advisable to perform a security evaluation over another specific view? Finally, how would the outcome vary concretely? We ran in-depth experiments to answer these questions in the hope of finding a nice tradeoff between simulation efforts and expertise, and security-evaluation degradation. We evaluate the results utilizing methodologies such as template-attacks with a clear distinction between profiling and attack-phase statistical views. This exemplary view of what an adversary might capture in these scenarios is followed by a more complete statistical evaluation analysis utilizing tools such as the Kullback–Leibler (KL) divergence and the Jensen-Shannon (JS) divergence to draw conclusions.

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Rendón-Segador, Fernando J., Juan A. Álvarez-García, Fernando Enríquez, and Oscar Deniz. "ViolenceNet: Dense Multi-Head Self-Attention with Bidirectional Convolutional LSTM for Detecting Violence." Electronics 10, no. 13 (July 3, 2021): 1601. http://dx.doi.org/10.3390/electronics10131601.

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Introducing efficient automatic violence detection in video surveillance or audiovisual content monitoring systems would greatly facilitate the work of closed-circuit television (CCTV) operators, rating agencies or those in charge of monitoring social network content. In this paper we present a new deep learning architecture, using an adapted version of DenseNet for three dimensions, a multi-head self-attention layer and a bidirectional convolutional long short-term memory (LSTM) module, that allows encoding relevant spatio-temporal features, to determine whether a video is violent or not. Furthermore, an ablation study of the input frames, comparing dense optical flow and adjacent frames subtraction and the influence of the attention layer is carried out, showing that the combination of optical flow and the attention mechanism improves results up to 4.4%. The conducted experiments using four of the most widely used datasets for this problem, matching or exceeding in some cases the results of the state of the art, reducing the number of network parameters needed (4.5 millions), and increasing its efficiency in test accuracy (from 95.6% on the most complex dataset to 100% on the simplest one) and inference time (less than 0.3 s for the longest clips). Finally, to check if the generated model is able to generalize violence, a cross-dataset analysis is performed, which shows the complexity of this approach: using three datasets to train and testing on the remaining one the accuracy drops in the worst case to 70.08% and in the best case to 81.51%, which points to future work oriented towards anomaly detection in new datasets.

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Bian, Zhongjian, Xiaofeng Hong, Yanan Guo, Lirida Naviner, Wei Ge, and Hao Cai. "Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario." Micromachines 12, no. 5 (May 12, 2021): 551. http://dx.doi.org/10.3390/mi12050551.

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Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 ∘C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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Aldridge, Dustin S. "Characterizing the Natural Temperature and Humidity Environment Severity." Journal of the IEST 60, no. 1 (January 1, 2017): 42–55. http://dx.doi.org/10.17764/1098-4321.60.1.42.

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Abstract Severe yet common product environmental tests are 1000 hours at 85 °C/85% RH or 95 °C/95% RH for products, circuit card assemblies, and electronic components. Such environments never occur naturally; however, they attempt to simulate the corrosion damage that could be expected in service. To what natural environment do these tests correlate? Further, how do tests based on MIL-HDBK-310, MIL-STD-810, and STANAG 2895 B3 daily environments compare to these standard test environments? The analysis employs the Physics-of-Failure (POF) Peck power law temperature-humidity model with common conservative values for the Arrhenius activation energy and the relative humidity exponent, based on aluminum corrosion, coupled with climatological data from 49 United States weather stations and 19 international locations. The monthly average temperature and humidity extremes were transformed into an hourly diurnal cycle assumed to occur every day of each month. Using the power law model the equivalent time at the test condition was calculated for each day, and summed for each month and location. The 85 °C/85% RH test can be correlated with about 10 years in a hot and moist natural environment, such as Singapore, with 1000 hours of 95 °C/95% RH exposure equivalent to 25 years. Long-term tests based on the worst-case diurnal temperature and humidity cycles in military standards are on the order of 1 in 1,000,000 probability of occurrence in nature.

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Długosz, Rafał, Andrzej Rydlewski, and Tomasz Talaśka. "Novel, low power, nonlinear dilatation and erosion filters realized in the CMOS technology." Facta universitatis - series: Electronics and Energetics 28, no. 2 (2015): 237–49. http://dx.doi.org/10.2298/fuee1502237d.

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In this paper we propose novel, binary-tree, asynchronous, nonlinear filters suitable for signal processing realized at the transistor level. Two versions of the filter have been proposed, namely the dilatation (Max) and the erosion (Min) one. In the proposed circuits an input signal (current) is sampled in a delay line, controlled by a multiphase clock. In the subsequent stage particular samples are converted to 1-bit digital signals with delays proportional to the values of these samples. In the last step the delays are compared in digital binary-tree structure in order to find either the Min or the Max value, depending on which filter is used. Both circuits have been simulated in the TSMC CMOS 0.18?m technology. To make the results reliable we applied the corner analysis procedure. The circuits were tested for temperatures ranging from -40 to 120?C, for different transistor models and supply voltages. The circuits offer a precision of about 99% at a typical detection time of 20 ns (for the Max filter) and 100 ns for the Min filter (the worst case scenario). The energy consumed per one input during a single calculation cycle equals 0.32 and 1.57 pJ, for the Max and Min filters, respectively.

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Tuohy, P., A. Gribben, A. J. Walton, and J. M. Robertson. "Realistic worst-case parameters for circuit simulation." IEE Proceedings I Solid State and Electron Devices 134, no. 5 (1987): 137. http://dx.doi.org/10.1049/ip-i-1.1987.0025.

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Li, Hua, and Wolfgang Rucker. "A hybrid method for the calculation of the inductances of coils with and without deformed turns." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 35, no. 4 (July 4, 2016): 1360–70. http://dx.doi.org/10.1108/compel-07-2015-0265.

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Purpose – The purpose of this paper is to present an accurate and efficient hybrid method for the calculation of the inductance of a coil and its inductance change due to deformed turns using numerical methods. Design/methodology/approach – The paper opted for finite element method coupled with analytical method (FCA) to accurately calculate the inductance of a coil, which is used as reference value. An algorithm with a power function is presented to approximate the partial inductance matrix with the purpose of obtaining the percentage change of the inductance due to deformed turns by using the partial element equivalent circuit (PEEC) with an approximated model and an optimization process. The presented method is successfully validated by the numerical results. Findings – The paper provides a systematic investigation of the inductance of an arbitrary shaped coil and shows how to accurately and efficiently evaluate the inductance change of a coil due to its deformed turns. It suggests that the inductance of a coil can be accurately calculated by using FCA and its percentage change due to deformed turns can be efficiently calculated by using the PEEC_Approximation. Research limitations/implications – As this research is for the magnetostatics, the skin- and proximity-effects have not been taken into account. Practical implications – The paper includes implication for the worst-case analysis of the coil’s inductance due to mechanical damage or manufacturing tolerance. Originality/value – This paper fulfills an identified need to study how the inductance change of a coil can be obtained accurately and efficiently.

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Kersten, W. F. J., and W. M. C. van den Heuvel. "Worst case studies of short-circuit making-currents." IEE Proceedings C Generation, Transmission and Distribution 138, no. 2 (1991): 129. http://dx.doi.org/10.1049/ip-c.1991.0016.

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Journal articles on the topic 'Worst Case Circuit Analysis'

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