Relevant bibliographies by topics / Write blocker

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Write blocker'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "Write blocker"

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Meffert, Christopher S., Ibrahim Baggili, and Frank Breitinger. "Deleting collected digital evidence by exploiting a widely adopted hardware write blocker." Digital Investigation 18 (August 2016): S87—S96. http://dx.doi.org/10.1016/j.diin.2016.04.004.

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Raychaudhuri, Kumarshankar, and M. George Christopher. "An Empirical study to determine the role of file-system in modification of hash value." International Journal of Cybersecurity Intelligence and Cybercrime 3, no. 1 (February 28, 2020): 24–41. http://dx.doi.org/10.52306/03010320nptv7468.

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In digital forensics, maintaining the integrity of digital exhibits is an essential aspect of the entire investigation and examination process, which is established using the technique of hashing. Lack of knowledge, while handling digital exhibits, might lead to unintentional alteration of computed hash, rendering the exhibit unacceptable in the court of Law. The hash value of a physical drive does not solely depend upon the data files present in it but also its file-system. Therefore, any change to the file-system might result in the change of the disk hash, even when the data files within it remain untouched. In this paper, our objective is to study the role of file-system in modification of the hash value. We examine and analyse the changes in the file-system of a NTFS formatted USB storage device, which leads to modification in its hash value when the device is plugged-in to the computer system without using write-blocker. The outcome of this research would justify the importance of write blockers while handling digital exhibits and also substantiate that the alteration in hash value of a storage device might not be an indication that data within the device has been tampered with.
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Kimbro, Devori, Michael Noschka, and Geoffrey Way. "Lend Us Your Earbuds: Shakespeare/Podcasting/Poesis." Humanities 8, no. 2 (March 28, 2019): 67. http://dx.doi.org/10.3390/h8020067.

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Podcasts by nature break down traditional economic barriers to making and accessing content. With low costs to both distribute and access, does podcasting provide a new outlet for academics, practitioners, and audiences to explore typically “high-minded” art or scholarly discussions usually blocked by the price of a theater ticket or a subscription to a paywalled database? To answer these questions, we define a poetics of podcasting—one that encourages humanities thinking par excellence—and, more importantly, carries with it implications for humanities studies writ large. To think in terms of poetics of podcasting shifts attention to the study of how we can craft, form, wright, and write for and with different communities both inside and outside the academy. In examining the current field of Shakespeare studies and podcasting, we argue podcasting incorporates elements ranging from the “slow” professor movement, to composition studies, to the early modern print market, discussing different methods that are both inspired by and disrupt traditional forms of knowledge production in the process.
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Teyssedou, A., A. Tapucu, and R. Camarero. "Blocked Flow Subchannel Simulation Comparison With Single-Phase Flow Data." Journal of Fluids Engineering 114, no. 2 (June 1, 1992): 205–13. http://dx.doi.org/10.1115/1.2910017.

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The time integral of the local instantaneous conservation laws has been used as the starting point to write a subchannel model. The assumption of an ergodic stationary process has made possible further spatial integration of the resulting equations. The SIMPLER algorithm is adapted for the numerical solution. An adequate blockage model assures an overall momentum balance over the discretized cell elements. Comparison of the predictions of the proposed model with the experimental data confirms that it is capable of handling blockages of up to 90 percent of the flow area. Presently, this model only accounts for the hydrodynamic aspect of vertical adiabatic flows.
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McGrath, Brian. "Impassivities: From Paradise Lost to Hellas." Comparative Literature 72, no. 2 (June 1, 2020): 114–27. http://dx.doi.org/10.1215/00104124-8127416.

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Abstract Though the words impasse and impassive come to English from two different etymological sources—impasse from the French, meaning without a pass; impassive from the Latin, meaning without suffering or without feeling—English invites confusion. In part because one cannot write directly about an impasse without making it less of one, this essay takes up the question of the impasse through the available pun: that is, with attention to impassivity. It begins with the origin of impasse in Voltaire and then, following the Oxford English Dictionary, turns to uses of impassive in Milton’s Paradise Lost and Shelley’s Hellas to explore the interplay between feeling (the feeling of being blocked, for instance) and feeling’s absence.
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Wang, Danli, Yang Zhang, and Shengyong Chen. "E-Block: A Tangible Programming Tool with Graphical Blocks." Mathematical Problems in Engineering 2013 (2013): 1–10. http://dx.doi.org/10.1155/2013/598547.

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This paper designs a tangible programming tool, E-Block, for children aged 5 to 9 to experience the preliminary understanding of programming by building blocks. With embedded artificial intelligence, the tool defines the programming blocks with the sensors as the input and enables children to write programs to complete the tasks in the computer. The symbol on the programming block's surface is used to help children understanding the function of each block. The sequence information is transferred to computer by microcomputers and then translated into semantic information. The system applies wireless and infrared technologies and provides user with feedbacks on both screen and programming blocks. Preliminary user studies using observation and user interview methods are shown for E-Block's prototype. The test results prove that E-Block is attractive to children and easy to learn and use. The project also highlights potential advantages of using single chip microcomputer (SCM) technology to develop tangible programming tools for children.
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Handayani, Emi Puasa. "PERLINDUNGAN HUKUM TERHADAP JURNALIS WARGA YANG BERBASIS TEKNOLOGI INFORMASI." DIVERSI : Jurnal Hukum 1, no. 1 (April 30, 2018): 1. http://dx.doi.org/10.32503/diversi.v1i1.125.

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Along with the development of technology with the invention of the internet, the speed information cannot be blocked. Black list that occurredin the print era no longer applied when the era of information technology. The problem is, when it appears journalists from citizens namely the ordinary citizens who write news or facts in blogs or personal website, then it is exposed to public whether there is any protection for the journalist. These are problems that were examined in the article titled Legal Protection Against Journalists Citizen-Based Information Technology. The results of this study can be concluded that now everyone can write and submit his writings to the audience with ease. Currently in Indonesia citizen journalism grown fairly well. This is evidenced by the number of blogs that exist in Indonesia and made by the people of Indonesia. The existence of the blog has signaled that citizen journalism is a phenomenon that is in demand and will continue to grow in the community. The nature of citizen journalism that allows all internet users can enter information that he had through the Internet, can cause a state of some kind of 'abuse of power' by the accessor. The absence of clear boundaries about what should and should not be put on the internet has made sites and blogs contain information that should not be. Therefore it needs to be a rule in the special form of legislation on the protection of citizen journalists. Keywords : Legal Protection, Citizen J
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Hossain, Md Amir. "Doris Lessing’s Fiction as Feminist Projections." International Journal of English and Cultural Studies 1, no. 1 (March 6, 2018): 23. http://dx.doi.org/10.11114/ijecs.v1i1.3081.

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Doris Lessing, an unrivaled novelist in the literary genres around the globe, portrays the fundamental problems of women as well as social system of her times. Lessing searches for new models to communicate the experiences of a blocked woman writer, who spends her early life in Africa, becomes an active and a disappointed communist, who is a politically committed writer, a mother, a wife, or a mistress sometimes a woman. With her very keen and subtle attitude, Lessing wants to present women’s psychological conflicts between marriage and love; motherhood and profession, unfairness of the double standard; alienation of a single career woman; hollowness of marriage in the traditional order and society. Lessing portrays her women in various social problems and with various perspectives of male against female. She tries to awaken women community to protest against the patriarchy through her feminist writings. For this purpose, this research paper would like to examine the psychological conflicts and traumatic experiences of powerful heroines, including- Anna Wulf of The Golden Notebook, Mary Turner of The Grass Is Singing, and Clefts of The Cleft.
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Staley, David J. "Teaching the Future of Technology in the History Classroom: A Case Study." World Futures Review 10, no. 4 (August 1, 2018): 253–62. http://dx.doi.org/10.1177/1946756718791273.

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This article will describe how historians can teach the future of technology. Historians need not alter their traditional methods of historical inquiry to teach the future, and indeed the history classroom is a natural site for foresight education. Historical inquiry begins with questions, and futuring similarly begins with asking the right questions. The historian seeks out evidence, and futurists as well identify drivers and blockers, considering how these drivers and blockers will interact with each other. In contrast to social scientists, historians work with imperfect or incomplete information, an apt description of the state of our evidence about the future. In a manner similar to historians, futurists interpret and draw inferences from evidence. After the research an analysis of the evidence is complete, the historian/futurist writes representations. This article will describe how I employed the historical method to teach the future of technology in a history research seminar, the results produced by the students, and ways that the study of the future can be situated in the history classroom.
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Giannini, Stefano. "Memory and the realization of the nothingness: On a letter from Vittorio Sereni to Giuseppe Ungaretti." Forum Italicum: A Journal of Italian Studies 52, no. 1 (December 17, 2017): 111–29. http://dx.doi.org/10.1177/0014585817747260.

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Ungaretti’s problematic relationship with his city of birth sheds light on the interplay between memory and oblivion in his poetry and prose. The shuttling back and forth between these poles marks the nature of his unfulfilled desire to recreate a lost Alexandrian atmosphere. Language opacity in Ungaretti is coupled with his attempts to represent a city—as he writes—that is suffocated by the sun and whose hidden ancient port is submerged by the sea depths. Blinding light and the darkness of the deep waters make the understanding of Ungaretti’s Alexandria a delicate process. In a letter to his friend Ungaretti, Sereni writes that he is preparing a poem but he is blocked at the stage where Ungaretti’s poetry comes into play. Is Sereni referring to a specific poem? The block persisted and is never explicitly resolved by Sereni. I argue that Ungaretti’s presence in Sereni’s poems is to be understood as a long process of reflection that comes to fruition only in Sereni’s late poems of “Stella variabile.” Sereni reconsiders the themes of light and of the city in his own poetry, but he realizes that those images are drowned in the recognition of the unalterable human limitations.
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Dissertations / Theses on the topic "Write blocker"

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Bengtsson, Johnny. "Forensisk hårddiskkloning och undersökning av hårddiskskrivskydd." Thesis, Linköping University, Department of Science and Technology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2378.

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Detta examensarbete reder ut arbetsprinciperna för olika typer av hårddiskskrivskydd; hårdvaruskrivskydd, mjukvaruskrivskydd, hybridskrivskydd och bygelskrivskydd. Slutsatsen av utredningen är att endast hårdvaruskrivskydd Detta examensarbete reder ut arbetsprinciperna för olika typer av hårddiskskrivskydd; hårdvaruskrivskydd, mjukvaruskrivskydd, hybridskrivskydd och bygelskrivskydd. Slutsatsen av utredningen är att endast hårdvaruskrivskydd bedöms ha tillräckligt pålitliga skyddsprinciper, vilket motiveras av dess oberoende från både hårdvara och operativsystem.

Vidare undersöks hårdvaruskrivskyddet Image MASSter(TM) Drive Lock från Intelligent Computer Solutions (ICS). Några egentliga slutsatser gick inte dra av kretskonstruktionen, bortsett från att den är uppbyggd kring en FPGA (Xilinx Spartan-II, XC2S15) med tillhörande PROM (XC17S15APC).

En egenutvecklad idé till autenticieringsmetod för hårddiskkloner föreslås som ett tillägg till arbetet. Principen bygger på att komplettera hårddiskklonen med unik information om hårddisk såväl kloningsomständigheter, vilka sammanflätas genom XOR-operation av komponenternas hashsummor.Autenticieringsmetoden kan vid sjösättning möjligen öka rättsäkerheten för både utredarna och den som står misstänkt vid en brottsutredning.

Arbetet är till stora delar utfört vid och på uppdrag av Statens kriminaltekniska laboratorium (SKL) i Linköping.

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Grusecki, Travis R. "Improving block sharing in the Write Anywhere File Layout file system." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/76818.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 41).
It is often useful in modern file systems for several files to share one or more data blocks. Block sharing is used to improve storage utilization by storing only one copy of a block shared by multiple files or volumes. This thesis proposes an approach, called Space Maker, which uses garbage collection techniques to simplify the up-front cost of file system operations, moving some of the more difficult block tracking work, such as the work required to clean-up after a file delete, to a back-end garbage collector. Space Maker was developed on top of the WAFL file system used in NetApp hardware. The Space Maker is shown to have fast scan performance, while decreasing the front-end time to delete files. Other operations, like file creates and writes have similar performance to a baseline system. Under Space Maker, block sharing is simplified, making a possible for new file system features that rely on sharing to be implemented more quickly with good performance.
by Travis R. Grusecki.
M.Eng.
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Hagström, Adrian, and Rustam Stanikzai. "Writer identification using semi-supervised GAN and LSR method on offline block characters." Thesis, Högskolan i Halmstad, Akademin för informationsteknologi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-43316.

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Block characters are often used when filling out forms, for example when writing ones personal number. The question of whether or not there is recoverable, biometric (identity related) information within individual digits of hand written personal numbers is then relevant. This thesis investigates the question by using both handcrafted features and extracting features via Deep learning (DL) models, and successively limiting the amount of available training samples. Some recent works using DL have presented semi-supervised methods using Generative adveserial network (GAN) generated data together with a modified Label smoothing regularization (LSR) function. Using this training method might improve performance on a baseline fully supervised model when doing authentication. This work additionally proposes a novel modified LSR function named Bootstrap label smooting regularizer (BLSR) designed to mitigate some of the problems of previous methods, and is compared to the others. The DL feature extraction is done by training a ResNet50 model to recognize writers of a personal numbers and then extracting the feature vector from the second to last layer of the network.Results show a clear indication of recoverable identity related information within the hand written (personal number) digits in boxes. Our results indicate an authentication performance, expressed in Equal error rate (EER), of around 25% with handcrafted features. The same performance measured in EER was between 20-30% when using the features extracted from the DL model. The DL methods, while showing potential for greater performance than the handcrafted, seem to suffer from fluctuation (noisiness) of results, making conclusions on their use in practice hard to draw. Additionally when using 1-2 training samples the handcrafted features easily beat the DL methods.When using the LSR variant semi-supervised methods there is no noticeable performance boost and BLSR gets the second best results among the alternatives.
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Alves, Marco Antonio Zanata. "Increasing energy efficiency of processor caches via line usage predictors." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/96062.

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O consumo de energia se torna cada vez mais importante para a arquitetura de processadores, onde o número de cores dentro de um mesmo chip está aumentando mas o total de energia disponível se mantém no mesmo nível ou até mesmo se reduz. Assim, técnicas para economizar energia, tais como opções de escala de frequência e desligamento automático de subsistemas, estão sendo usadas para manter a troca entre energia e desempenho. Para se obter alto desempenho, os atuais Chip Multiprocessors (CMPs) integram grandes memórias cache a fim de reduzir a latência média para acesso a memória principal, através da alocação do conjunto de dados da aplicação dentro do chip. Essas memórias cache tem sido projetadas tradicionalmente para explorar a localidade temporal usando políticas de substituição inteligentes e localidade espacial buscando todos os dados da linha da cache após uma falta de dados. Entretanto, estudos recentes mostraram que o número de sub-blocos dentro da linha da memória cache, que são realmente usados, costuma ser baixo, sendo que, os sub-blocos que são usados recebem poucos acessos antes de se tornarem mortos (isto é, nunca mais são acessados). Além disso, muitas da linhas da memória cache permanecem ligadas por longos períodos de tempo, mesmo que os dados não sejam usados novamente ou são inválidos. Para linhas de cache modificadas, a memória cache aguarda até que a linha seja expulsa para que esta seja gravada (write-back) de volta no próximo nível de memória. Essas escritas competem com as requisições de leitura (demanda do processador e prébusca da cache), aumentando a pressão no controlador de memória. Por essas razões, a eficiência energética e o desempenho das memórias cache não são ideais. Essa tese propõe a aplicação de preditores de uso de linhas da cache para aumentar a eficiência energética das memórias cache. São propostos os mecanismos Dead Sub-Block Predictor (DSBP) e Dead Line and Early Write-Back Predictor (DEWP) para permitir economia de energia sem que haja degradação do desempenho. DSBP é usado para prever quais sub-blocos da linha da cache serão usados e quantas vezes eles serão acessados de forma a trazer para a cache apenas os sub-blocos úteis e desliga-los após eles serem acessados pelo número de vezes previsto. DEWP prevê linhas de cache mortas assim que elas recebem o último acesso, desligando essas linhas. As linhas sujas são escalonadas para sofrerem write-back após a última operação de escrita, aumentando o potencial de salvar energia, reduzindo também a pressão no controlador de memória. Ambos os mecanismos propostos também reduzem a poluição nas memórias cache, dando prioridade para a expulsão de linhas mortas, melhorando as atuais políticas de substituição. Embora cada mecanismo apresentado seja capaz de funcionar separadamente dentro do sistema, ambos os mecanismos podem também ser misturados em uma mesma hierarquia de cache. Essa implementação mista é interessante pois a granularidade de sub-bloco é preferível para níveis de cache próximos do processador, onde as linhas de memória cache são expulsas rapidamente, enquanto o último nível de cache tende a usar toda a linha antes da sua expulsão. Com o intuito de avaliar os mecanismos propostos, é apresentado o Simulator of Non- Uniform Cache Architectures (SiNUCA). Esse simulador de microarquitetura com precisão de ciclos é validado em termos de desempenho e consumo de energia através da comparação com um processador real. Os resultados de desempenho foram obtidos executando aplicações das cargas de trabalho single-threaded do conjunto SPEC-CPU2006 e aplicações multi-threaded dos conjuntos SPEC-OMP2001 e NAS-NPB. Os resultados relativos a energia foram obtidos integrando o SiNUCA com as ferramentas de modelagem Multi-core Power, Area, and Timing (McPAT) e CACTI. Quando aplicados os mecanismos em todos os níveis de memória cache, observou-se em média uma redução de 36% no consumo de energia usando o DSBP, 25% usando o DEWP e 37% quando usou-se o DSBP nos níveis L1 e L2 e o DEWP no último nível. Todas essas reduções causaram uma perda desprezível de desempenho de menos de 4% em média.
Energy consumption is becoming more important for processor architectures, where the number of cores inside the chip is increasing and the total power budget is kept at the same level or even reduced. Thus, energy saving techniques such as frequency scaling options and automatic shutdown of sub-systems are being used to maintain the trade-off between power and performance. To deliver high performance, current Chip Multiprocessors (CMPs) integrate large caches in order to reduce the average memory access latency by allocating the applications’ working set on-chip. These cache memories have traditionally been designed to exploit temporal locality by using smart replacement policies, and spatial locality by fetching entire cache lines from memory on a cache miss. However, recent studies have shown that the number of sub-blocks within a line that are actually used is often low, and those sub-blocks that are used are accessed only a few times before becoming dead (that is, never accessed again). Additionally, many of the cache lines remain powered for a long period of time even if the data is not used again, or is invalid. For modified cache lines, the cache memory waits until the line is evicted to perform the write-back to next memory level. These write-backs compete with read requests (processor demand and cache prefetch), increasing the pressure on the memory controller. For these reasons, the energy efficiency and performance of cache memories are not ideal. This thesis introduces cache line usage predictors to increase the energy efficiency of cache memories. We propose the Dead Sub-Block Predictor (DSBP) and Dead Line and Early Write-Back Predictor (DEWP) mechanisms to enable energy savings without performance degradation. DSBP is used to predict which sub-blocks of a cache line will be actually accessed and how many times they will be used in order to bring into the cache only those sub-blocks that are necessary, and power them off after they are accessed the predicted number of times. DEWP predicts dead lines as soon as they receive the last access, and turns off these lines. Dirty lines are scheduled for write-back after the last write operation occurs, increasing the energy savings potential and also reducing the pressure on the memory controller. Both proposed mechanisms also reduce pollution in cache memories by prioritizing dead lines for eviction in the existing replacement policy. Although each introduced mechanism is capable of performing separately inside a system, both mechanisms can also be mixed in the same cache hierarchy. This mixed implementation is interesting because the sub-block granularity is more suitable for cache levels closer to the processor, where the cache lines are quickly evicted, while the Last- Level Cache (LLC) tends to use the whole cache line before its eviction. In order to evaluate our proposed mechanisms, we introduce the Simulator of Non- Uniform Cache Architectures (SiNUCA). This cycle-accurate microarchitecture simulator is validated in terms of performance and energy consumption by comparing it to a real processor. Our performance results were obtained executing single-threaded applications from SPEC-CPU2006 and multi-threaded applications from SPEC-OMP2001 and NASNPB benchmark suites. The energy related results were obtained by integrating SiNUCA with the Multi-core Power, Area, and Timing (McPAT) framework and the CACTI power modeling tool. When applying our mechanisms on all the cache levels, we observe on average a 36% energy reduction for DSBP, 25% energy reduction using DEWP and an average reduction of 37% in the energy consumption applying DSBP on L1 and L2 and DEWP on the LLC. All these reductions caused a negligible performance loss of less than 4% on average.
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Ciou, Wun-Fang, and 邱文芳. "Behaviors and Attitudes Toward English Reading, English Writing, Writer''s Block in English, and English Writing Apprehension–A Case Study of EFL Student Writers in Taiwan." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/79876c.

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碩士
淡江大學
英文學系碩士班
96
This study aims to investigate EFL English majors'' behaviors and attitudes toward their English writing,and to examine the interrelationships among the following issues such as English reading behaviors, English writing behaviors, English writing strategies, revision behaviors, writer''s block in English, and English writing apprehension. The research was conducted at Tamkang University in Taiwan. Participants of this study were 160 junior English majors from this university. Data were collected quantitatively and qualitatively by using three sets of questionnaires and interviews that focused on essay recalls. The result revealed that there was a significantly positive relationship between writer''s block in English and English writing strategies. Moreover, there was a significantly positive relationship between writer''s block in English and English writing apprehension. A significantly negative correlation existed between English writing apprehension and daily English writing hours. Based on the findings of this study, it was suggested that EFL instructors may avoid negative evaluations, and encourage their students to read more, to write more, and to use English writing strategies appropriately for alleviating their English writing anxiety or writer''s block in English.
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Books on the topic "Write blocker"

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Bryant, Roberta Jean. Anybody can write: A playful approach : ideas for the aspiring writer, the beginner, the blocked writer. Novato, Calif: New World Library, 1999.

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Rose, Mike. When a writer can't write: Studies in writer's block and other composing-process problems. New York: The GuildfordPress, 1985.

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Write: 10 days to overcoming writer's block : period. Avon, Mass: Adams Media, 2006.

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Bach, Richard. Writer ferrets: Chasing the muse. New York: Scribner, 2002.

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Sutton, Joseph. Write now: On the road to getting published or how I learned to sell my book. Berkeley, Calif: Mad dog publishing, 2008.

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The midnight disease: The drive to write, writer's block, and the creative brain. Boston: Houghton Mifflin, 2004.

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Keyes, Ralph. The courage to write: How writers transcend fear. New York: H. Holt, 2003.

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The courage to write: How writers transcend fear. New York: H. Holt, 1995.

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Writing from the inside out: Transforming your psychological blocks to release the writer within. New York: Wiley, 2000.

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When a Writer Can't Write: Studies in Writer's Block and Other Composing Problems. The Guilford Press, 1985.

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Book chapters on the topic "Write blocker"

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Dukats, Mara. "Chip Off the Old Block." In Reflect & Write, 144. New York: Routledge, 2021. http://dx.doi.org/10.4324/9781003237686-134.

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Johnson, W. Brad, and Carol A. Mullen. "Tackle Thoughts and Emotions that Block Productivity." In Write to the Top!, 145–57. New York: Palgrave Macmillan US, 2007. http://dx.doi.org/10.1057/9780230604780_9.

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Curthoys, Ann, and Ann McGrath. "How to avoid writer’s block." In How to Write History that People Want to Read, 101–16. London: Palgrave Macmillan UK, 2011. http://dx.doi.org/10.1007/978-0-230-30496-3_6.

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Yang, Otto O. "Starting to Write: Planning the Aims and Overcoming Writer’s Block." In Guide to Effective Grant Writing, 15–18. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-1-4614-1581-7_6.

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Wang, Yulin, Guangjun Li, Xiaojun Wu, and Shuisheng Lin. "An Efficient Cache Replacement Policy with Distinguishing Write Blocks from Read Blocks in Disk Arrays." In Parallel and Distributed Processing and Applications - ISPA 2005 Workshops, 120–29. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11576259_14.

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Beyer, Dirk, and Karlheinz Friedberger. "In-Place vs. Copy-on-Write CEGAR Refinement for Block Summarization with Caching." In Leveraging Applications of Formal Methods, Verification and Validation. Verification, 197–215. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-03421-4_14.

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Monazzah, Amir Mahdi Hosseini, Amir M. Rahmani, Antonio Miele, and Nikil Dutt. "Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories." In Dependable Embedded Systems, 505–26. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_21.

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AbstractDue to the consistent pressing quest of larger on-chip memories and caches of multicore and manycore architectures, Spin Transfer Torque Magnetic RAM (STT-MRAM or STT-RAM) has been proposed as a promising technology to replace classical SRAMs in near-future devices. Main advantages of STT-RAMs are a considerably higher transistor density and a negligible leakage power compared with SRAM technology. However, the drawback of this technology is the high probability of errors occurring especially in write operations. Such errors are asymmetric and transition-dependent, where 0 → 1 is the most critical one, and is high subjected to the amount and current (voltage) supplied to the memory during the write operation. As a consequence, STT-RAMs present an intrinsic trade-off between energy consumption vs. reliability that needs to be properly tuned w.r.t. the currently running application and its reliability requirement. This chapter proposes FlexRel, an energy-aware reliability improvement architectural scheme for STT-RAM cache memories. FlexRel considers a memory architecture provided with Error Correction Codes (ECCs) and a custom current regulator for the various cache ways and conducts a trade-off between reliability and energy consumption. FlexRel cache controller dynamically profiles the number of 0 → 1 transitions of each individual bit write operation in a cache block and based on that selects the most-suitable cache way and current level to guarantee the necessary error rate threshold (in terms of occurred write errors) while minimizing the energy consumption. We experimentally evaluated the efficiency of FlexRel against the most efficient uniform protection scheme from reliability, energy, area, and performance perspectives. Experimental simulations performed by using gem5 has demonstrated that while FlexRel satisfies the given error rate threshold, it delivers up to 13.2% energy saving. From the area footprint perspective, FlexRel delivers up to 7.9% cache ways’ area saving. Furthermore, the performance overhead of the FlexRel algorithm which changes the traffic patterns of the cache ways during the executions is 1.7%, on average.
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"Building Blocks of Sentences." In The Learning-to-write Process in Elementary Classrooms, 207–8. Routledge, 2012. http://dx.doi.org/10.4324/9780203399996-28.

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Cole, Jean Lee. "Rising from the Gutter." In How the Other Half Laughs, 67–92. University Press of Mississippi, 2020. http://dx.doi.org/10.14325/mississippi/9781496826527.003.0003.

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This chapter shows how the early comic strip was developed and then came to influence comic fiction in the early twentieth century. As the editor of the New York Journal‘s comic supplement, Rudolph Block regularized the use of panels, repetitive storylines, and caricature, resulting in the multi-panel format that defines the comic-strip genre. Block’s role in the development of the comic strip has gone largely unrecognized; as a writer of Jewish American literature, Block has been forgotten. Using the pseudonym Bruno Lessing, Block published nearly a hundred stories between 1905 and 1920 in popular magazines. These humorous stories, full of rich dialect and accompanied by vibrant illustrations, translated the multiethnic culture of the Lower East Side for a mainstream, English-speaking audience. Block represented dialect and caricature as opportunities for negotiation and play, providing ways to display identity in multiple and shifting forms.
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Cartwright, Nathaniel Knox, and Petros Carvounis. "Write short notes on the side effects of β-blockers." In Short Answer Questions for the MRCOphth Part 1, 14. CRC Press, 2018. http://dx.doi.org/10.1201/9781315375526-9.

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Conference papers on the topic "Write blocker"

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Tobin, Patrick, Nhien-An Le-Khac, and M.-Tahar Kechadi. "A lightweight software write-blocker for virtual machine forensics." In 2016 Sixth International Conference on Innovative Computing Technology (INTECH). IEEE, 2016. http://dx.doi.org/10.1109/intech.2016.7845141.

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Mingardi, William B., and Gustavo M. D. Vieira. "Characterizing Synchronous Writes in Stable Memory Devices." In XVIII Workshop em Desempenho de Sistemas Computacionais e de Comunicação. Sociedade Brasileira de Computação - SBC, 2019. http://dx.doi.org/10.5753/wperformance.2019.6458.

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Distributed algorithms that operate in the fail-recovery model rely on the state stored in stable memory to guarantee the irreversibility of operations even in the presence of failures. The performance of these algorithms lean heavily on the performance of stable memory. Current storage technologies have a defined performance profile: data is accessed in blocks of hundreds or thousands of bytes, random access to these blocks is expensive and sequential access is somewhat better. File system implementations hide some of the perfor- mance limitations of the underlying storage devices using buffers and caches. However, fail-recovery distributed algorithms bypass some of these techniques and perform synchronous writes to be able to tolerate a failure during the write itself. Assuming the distributed system designer is able to buffer the algorithm’s writes, we ask how buffer size and latency complement each other. In this paper we start to answer this question by characterizing the performance (throughput and latency) of typical stable memory devices using a representative set of current file systems.
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Cheon, Seungyong, and Youjip Won. "Exploiting Multi-Block Atomic Write in SQLite Transaction." In the International Conference. New York, New York, USA: ACM Press, 2017. http://dx.doi.org/10.1145/3069593.3069616.

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Guneysu, Tim, and Christof Paar. "Transforming write collisions in block RAMs into security applications." In 2009 International Conference on Field-Programmable Technology (FPT 2009). IEEE, 2009. http://dx.doi.org/10.1109/fpt.2009.5377631.

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Weixing Ji, Feng Shi, Baojun Qiao, and Hong Song. "Multi-port Memory Design Methodology Based on Block Read and Write." In 2007 IEEE International Conference on Control and Automation. IEEE, 2007. http://dx.doi.org/10.1109/icca.2007.4376358.

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Chang, Li-Pin, Sheng-Min Huang, and Wen-Ping Li. "Optimizing FTL mapping cache for random-write workloads using adaptive block partitioning." In SAC 2014: Symposium on Applied Computing. New York, NY, USA: ACM, 2014. http://dx.doi.org/10.1145/2554850.2554939.

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Chen, Yuze, and Seokin Hong. "Proactive Dead Block Eviction for Reducing Write Latency in STT-MRAM Caches." In 2021 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2021. http://dx.doi.org/10.1109/iceic51217.2021.9369729.

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Debnath, B., S. Subramanya, D. Du, and D. J. Lilja. "Large Block CLOCK (LB-CLOCK): A write caching algorithm for solid state disks." In amp; Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE, 2009. http://dx.doi.org/10.1109/mascot.2009.5366737.

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Zhang, Yu, Ke Zhou, Ping Huang, Hua Wang, Jianying Hu, Yangtao Wang, Yongguang Ji, and Bin Cheng. "A Machine Learning Based Write Policy for SSD Cache in Cloud Block Storage." In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020. http://dx.doi.org/10.23919/date48585.2020.9116539.

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Liu, Hsin-I., Brian Richards, Avideh Zakhor, and Borivoje Nikolic. "Hardware implementation of Block GC3 lossless compression algorithm for direct-write lithography systems." In SPIE Advanced Lithography, edited by Daniel J. C. Herr. SPIE, 2010. http://dx.doi.org/10.1117/12.846447.

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Reports on the topic "Write blocker"

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Black, Paul E. Software write block testing support tools validation :. Gaithersburg, MD: National Institute of Standards and Technology, 2005. http://dx.doi.org/10.6028/nist.ir.7207a.

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Black, Paul E. Software write block testing support tools validation :. Gaithersburg, MD: National Institute of Standards and Technology, 2005. http://dx.doi.org/10.6028/nist.ir.7207b.

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