Journal articles: 'Write Noise'

1

Madison, M. R. "A model of write noise in magneto‐optical media." Journal of Applied Physics 73, no. 10 (1993): 5782–84. http://dx.doi.org/10.1063/1.353571.

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2

Zhang, J., R. Kemshetti, E. A. Salhi, et al. "Write frequency dependence of popcorn noise in GMR heads." IEEE Transactions on Magnetics 36, no. 5 (2000): 2530–32. http://dx.doi.org/10.1109/20.908495.

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3

Makino, H., S. Nakata, H. Suzuki, et al. "Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield." IET Circuits, Devices & Systems 6, no. 4 (2012): 260. http://dx.doi.org/10.1049/iet-cds.2012.0090.

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Melianas, A., T. J. Quill, G. LeCroy, et al. "Temperature-resilient solid-state organic artificial synapses for neuromorphic computing." Science Advances 6, no. 27 (2020): eabb2958. http://dx.doi.org/10.1126/sciadv.abb2958.

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Devices with tunable resistance are highly sought after for neuromorphic computing. Conventional resistive memories, however, suffer from nonlinear and asymmetric resistance tuning and excessive write noise, degrading artificial neural network (ANN) accelerator performance. Emerging electrochemical random-access memories (ECRAMs) display write linearity, which enables substantially faster ANN training by array programing in parallel. However, state-of-the-art ECRAMs have not yet demonstrated stable and efficient operation at temperatures required for packaged electronic devices (~90°C). Here, we show that (semi)conducting polymers combined with ion gel electrolyte films enable solid-state ECRAMs with stable and nearly temperature-independent operation up to 90°C. These ECRAMs show linear resistance tuning over a >2× dynamic range, 20-nanosecond switching, submicrosecond write-read cycling, low noise, and low-voltage (±1 volt) and low-energy (~80 femtojoules per write) operation combined with excellent endurance (>109 write-read operations at 90°C). Demonstration of these high-performance ECRAMs is a fundamental step toward their implementation in hardware ANNs.

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Islam, Aminul, and Mohd Hasan. "VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY." IIUM Engineering Journal 12, no. 1 (2011): 13–30. http://dx.doi.org/10.31436/iiumej.v12i1.25.

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This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM).

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6

Lee, S. Y., J. L. Pressesky, D. Williams, and N. Heiman. "Write current dependence of transition noise in thin film media." IEEE Transactions on Magnetics 26, no. 1 (1990): 121–23. http://dx.doi.org/10.1109/20.50509.

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Sachdeva, Ashish, and V. K. Tomar. "Design of a Stable Low Power 11-T Static Random Access Memory Cell." Journal of Circuits, Systems and Computers 29, no. 13 (2020): 2050206. http://dx.doi.org/10.1142/s0218126620502060.

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In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [Formula: see text] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

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8

Chao, Shiuh, and Tsong-Yo Yang. "Artificial noise in read-write simulation of optical disk and drive." SIMULATION 56, no. 6 (1991): 403–12. http://dx.doi.org/10.1177/003754979105600612.

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9

Mansore, S. R., R. S. Gamad, and D. K. Mishra. "A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability." Journal of Circuits, Systems and Computers 29, no. 05 (2019): 2050067. http://dx.doi.org/10.1142/s021812662050067x.

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Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

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10

Miyamoto, N., H. Fukui, T. Ohtsu, and Y. Karakama. "Relationship of Exciting Current to Noise-after-Write of Thin Film Head." Journal of the Magnetics Society of Japan 16, no. 2 (1992): 91–94. http://dx.doi.org/10.3379/jmsjmag.16.91.

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11

Sugiyama, Y., H. Ohmori, T. Kobayashi, et al. "Read/write characteristics and noise properties of a thin film VCR head." IEEE Transactions on Magnetics 32, no. 1 (1996): 172–77. http://dx.doi.org/10.1109/20.477569.

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12

Liu, F. H., P. Ryan, X. Shi, and M. H. Kryder. "Correlation between noise-after-write and magnetization dynamics in thin film heads." IEEE Transactions on Magnetics 28, no. 5 (1992): 2100–2102. http://dx.doi.org/10.1109/20.179409.

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13

Miyamoto, N., H. Fukui, T. Ohtsu, and Y. Karakama. "Relationship of Exciting Current to Noise-after-Write of Thin Film Head." IEEE Translation Journal on Magnetics in Japan 7, no. 10 (1992): 768–72. http://dx.doi.org/10.1109/tjmj.1992.4565497.

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14

Crittenden, Lorri J., Newton C. Ellis, and Rodger J. Koppa. "Considerations of Noise for the Use of Compressed Speech in a Cockpit Environment." Proceedings of the Human Factors Society Annual Meeting 33, no. 2 (1989): 38–42. http://dx.doi.org/10.1177/154193128903300208.

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This research investigated the feasibility of using time compressed speech in a cockpit environment by examining the effect of cockpit noise on the intelligibility and comprehensibility of compressed speech. Research participants listened to cockpit-oriented verbal messages and were required to write them down afterwards. Results revealed a significant difference in compression levels between the environment without the ambient cockpit noise and the noise environment. The primary finding of this study was an interaction between noise and compression level. Implications of this research are made for the design of advanced crew systems.

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15

Sharma, Neha, and Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS." International Journal of Modeling, Simulation, and Scientific Computing 12, no. 04 (2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.

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With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32[Formula: see text]nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.

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16

Kumar, Vinod, and Ram Murti Rawat. "Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins." International Journal of Security and Privacy in Pervasive Computing 13, no. 2 (2021): 16–28. http://dx.doi.org/10.4018/ijsppc.2021040102.

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This paper examines the factors that affect the static noise margin (SNM) of static random access memories which focus on optimizing read and write operation of 8T SRAM cell which is better than 6T SRAM cell using swing restoration for dual node voltage. New 8T SRAM technique on the circuit or architecture level is required. In this paper, comparative analysis of 6T and 8T SRAM cells with improved read and write margin is done for 130nm technology with cadence virtuoso schematics tool.

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17

Chao, Fei, Fuhai Chen, Yunhang Shen, et al. "Robotic Free Writing of Chinese Characters via Human–Robot Interactions." International Journal of Humanoid Robotics 11, no. 01 (2014): 1450007. http://dx.doi.org/10.1142/s0219843614500078.

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Implementation of robotic writing ability is recognized as a difficult task, which involves complicated image processing and robotic control algorithms. This paper introduces a novel approach to robotic writing by using human–robot interactions. The method applies a motion sensing input device to capture a human demonstrator's arm trajectories, uses a gesture determination algorithm to extract a Chinese character's strokes from these trajectories, and employs noise filtering and curve fitting methods to optimize the strokes. The approach displays real-time captured trajectories to the human demonstrator; therefore, the human demonstrator is able to adjust his/her gesture to achieve a better character writing effect. Then, our robot writes the human-gestured character by using the robotic arm's joint values. The inverse kinematics algorithm generates the joint values from the stroke trajectories. Experimental analysis shows that the proposed approach can allow a human to naturally and conveniently control the robot in order to write many Chinese characters. Additionally, this approach allows the robot to achieve a satisfactory writing quality for characters with a simple structure, with the potential to write more complex characters.

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18

Rawat, Ram Murti, and Vinod Kumar. "Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 2 (2021): 130. http://dx.doi.org/10.11591/ijres.v10.i2.pp130-136.

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<span>This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.</span>

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19

Chaidaungsri, Nuttapon, Arkom Kaewrawang, Komkrit Chooruang, and Damrongsak Tongsomporn. "Investigation of Perpendicular Magnetic Recording Footprint by Spin-Stand Microscopy." Applied Mechanics and Materials 781 (August 2015): 215–18. http://dx.doi.org/10.4028/www.scientific.net/amm.781.215.

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The characteristics of magnetic recording are necessary to understand in order to increase the areal densities and improve the perfermance of recording system. Therefore, experimental tools must be developed to help researchers to carry out signal and noise recording experiments on different heads and media combinations. In this paper, the perpendicular magnetic recording footprint using spin-stand microscopy is demonstrated. It was found experimentally that the magnetic footprint can precisely catch some recording dynamics of the write heads during the write gate off conditions and also provide useful insight information of the recording performance.

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20

Chen, Xianlong, Weifeng Lü, Bo Liu, Tiejun Du, and Mi Lin. "Performance Evaluation of Negative-Capacitance Fin-Type Field Effect Transistor-Based Static Random-Access Memory with Mixed-Mode Simulation." Journal of Nanoelectronics and Optoelectronics 16, no. 3 (2021): 414–19. http://dx.doi.org/10.1166/jno.2021.2964.

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Electrical characteristics of fin-type field-effect transistor with negative capacitance effect (NCFinFET) are investigated coupled with the Landau-Khalatnikov equation for ferroelectric materials in this study. Moreover, Technology Computer Aided Design (TCAD) mixed-mode simulation is carried out to evaluate and compare the performance of NCFinFET-based static random access memory cell (NC-SRAM) with a traditional FinFETbased SRAM one. It is shown NC-SRAM has higher static noise margin (SNM) and better anti-interference capability than conventional SRAM with the same supply voltage. The static read, hold, and write noise margins (RSNM, HSNM, and WSNM, respectively) for NC-SRAM increased by 10%, 30%, and 15%, respectively, and the access disturb stability improved by 80%. Simulation results also reveal that the read stability increases with increasing ferroelectric layer thickness, while the write stability exhibits a non-monotonic trend with ferroelectric layer thickness for NC-SRAM.

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21

Wasala, Sahan, Yutong Xue, Lon Stevens, Ted Wiegandt, and Tim Persoons. "Numerical simulations of flow induced noise from a dual rotor cooling fan used in electronic cooling systems." INTER-NOISE and NOISE-CON Congress and Conference Proceedings 263, no. 5 (2021): 1308–19. http://dx.doi.org/10.3397/in-2021-1809.

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Hard Disk Drive (HDD) system enclosures in a data center require effective cooling systems to avoid HDD overheating. These systems often rely on air cooling because of their cost effciency and maintainability. Air cooling systems typically consist of an array of axial fans which push or pull the air through the system. These fans emit high level tonal noise particularly at high tip speed ratios. High-capacity HDDs, on the other hand, are sensitive to high acoustic noise, which consequently increases the risk of read/write error and deteriorates drive performance. Therefore, cooling fan noise adversely affects the function of the HDD enclosure systems which emphasizes the need to understand the noise sources and develop methods to mitigate HDD noise exposure.

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22

Panayotov, Stanimir. "Black noise ruins: Notes after Locrian’s Rain of Ashes." Metal Music Studies 7, no. 1 (2021): 103–14. http://dx.doi.org/10.1386/mms_00034_1.

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In this article-cum-essay, I scrutinize the particulars surrounding Locrian’s release Rain of Ashes. The text opens with a reflection on quiddity and what I call curity (whyness) to situate the musicians aural potentialities, and move towards articulating what I define as ‘black noise’. In the context of black noise, I claim Locrian perform the ruins of black noise. I attempt to write alongside the music by replicating some of the music’s qualities and galvanize those qualities by using commentaries, reviews of the release and interviews with the band’s members while trying to analyse the push-and-pull aura of Rain of Ashes for the listener.

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23

Birla, Shilpi. "FinFET SRAM cell with improved stability and power for low power applications." Journal of Integrated Circuits and Systems 14, no. 2 (2019): 1–8. http://dx.doi.org/10.29292/jics.v14i2.57.

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In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV.At subthreshold operation also, it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Impact of process variation on cell stability also been analyzed.

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24

Jagadale, Sanket, Aniket Phapale, T. V. Sai Varun Sasthry, and V. S. Kanchana Bhaaskaran. "Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit." International Journal of Engineering & Technology 7, no. 4.5 (2018): 645. http://dx.doi.org/10.14419/ijet.v7i4.5.21177.

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Lowering power consumption and increasing the noise margin have become the two most important aspects to be considered in SRAM design. Additionally, a stable operation with good memory retention capability has gained greater importance in obtaining good yield at low-voltage and low-power SRAM designs, due to the fact that parameter variations play a major role in scaled technologies. In this paper, the 6T SRAM, 7T low power SRAM and 7T multi threshold low power SRAM designs are designed, to incorporate power gating technique. The architecture of each of the SRAM designs and their working are analyzed thoroughly. The outputs of the read, write and hold operations with transient response are observed and the power dissipation and static noise margin (SNM) of the each of the SRAM cells is calculated and compared. The paper also presents new power reduction solution through the cell control circuit which reduces the unwanted and spurious switching activities during read and writes operations. The paper demonstrates the reduction of the power con- sumption through the use of cell control circuit.

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25

VanZandt, T., R. Browning, Sang Y. Lee, et al. "SEMPA studies of CoNiCr and its correlation with noise at different write currents (abstract)." Journal of Applied Physics 69, no. 8 (1991): 4748. http://dx.doi.org/10.1063/1.348268.

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26

Urakami, Y., N. Ito, H. Katada, et al. "Analysis of Track-Edge Noise From the Viewpoint of Write Heads With Different Dimensions." IEEE Transactions on Magnetics 45, no. 10 (2009): 3656–59. http://dx.doi.org/10.1109/tmag.2009.2022953.

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27

Gupta, Priya, Anu Gupta, and Abhijit Asati. "Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region." International Journal of Reconfigurable Computing 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/749816.

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The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in hold mode. The proposed 8T SRAM cell shows improvements in terms of 7.735x narrower spread in average standby power, 2.61x less in averageTWA(write access time), and 1.07x less in averageTRA(read access time) at supply voltage varying from 0.3 V to 0.5 V as compared to 6T SRAM equivalent at 45 nm technology node. Thus, comparative analysis shows that the proposed design has a significant improvement, thereby achieving high cell stability at 45 nm technology node.

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Kumar, Vinod, and Ram Murti Rawat. "Restoration circuits for Low power Reduce Swing of 6T and 8T SRAM Cell With Improved Read and Write Margins." WSEAS TRANSACTIONS ON ACOUSTICS AND MUSIC 7 (March 1, 2021): 22–34. http://dx.doi.org/10.37394/232019.2020.7.4.

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A paper that examines the factors thataffect the Static Noise Margin (SNM) of a StaticRandom Access memories. At an equivalent time,they specialise in optimizing Read and Writeoperation of 8T SRAM cell which is best than 6TSRAM cell Using Swing Restoration Dual NodeVoltage. The read and Write operation and improveStability analysis. This SRAM technique on thecircuit or architecture level is required to improveread and write operation. during this paperComparative Analysis of 6T and 8T SRAM Cellswith Improved Read and Write Margin is completedfor 180 nm Technology with Cadence Virtuososchematics Tool.This Paper is organized as follows: thecharacteristics of 6T SRAM cell are described arerepresented in section VIII. In section IX, proposed8T SRAM cell is described. In section X, Standard8T SRAM cell is described. Section XI includes thesimulation results which give comparison of variousparameters of 6T and 8T SRAM cells. In Section XIISimulation Results and DC analysis and sectionXIII conclusion the work.

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Kobayashi, K. "Correlation between Noise-after-Write and Magnetic Domain in Thin-Film Heads by Electron Microscopy." Journal of the Magnetics Society of Japan 18, no. 2 (1994): 103–8. http://dx.doi.org/10.3379/jmsjmag.18.103.

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Wang, Yao, Jun Yao, and B. V. K. Vijaya Kumar. "2-D Write/Read Channel Model for Bit-Patterned Media Recording With Large Media Noise." IEEE Transactions on Magnetics 51, no. 12 (2015): 1–11. http://dx.doi.org/10.1109/tmag.2015.2464786.

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Kobayashi, K. "Correlation between Noise-after-Write and Magnetic Domain in Thin-Film Heads by Electron Microscopy." IEEE Translation Journal on Magnetics in Japan 9, no. 6 (1994): 210–17. http://dx.doi.org/10.1109/tjmj.1994.4565982.

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Amara-Dababi, S., H. Béa, R. C. Sousa, C. Baraduc, and B. Dieny. "Correlation between write endurance and electrical low frequency noise in MgO based magnetic tunnel junctions." Applied Physics Letters 102, no. 5 (2013): 052404. http://dx.doi.org/10.1063/1.4788816.

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Sheu, Ming-Hwa, S. M. Salahuddin Morsalin, Chang-Ming Tsai, et al. "Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement." Electronics 10, no. 6 (2021): 685. http://dx.doi.org/10.3390/electronics10060685.

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To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology.

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Ivanov, Dmitriy V., Ilya L. Sandler, and Natalya V. Chertykovtseva. "Estimation of Parameters of Hyperbolic Functions with Additive Noise." Advances in Science and Technology 105 (April 2021): 302–8. http://dx.doi.org/10.4028/www.scientific.net/ast.105.302.

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Hyperbolic functions are widely used to write solutions to ordinary differential equations and partial differential equations. These functions are nonlinear in parameters, which makes it difficult to estimate the parameters of these functions. In the paper, two-step algorithms for estimating the parameters of hyperbolic sine and cosine (sinh and cosh) in the presence of measurement errors are proposed. At the first step, the hyperbolic function is transformed into a linear difference equation (autoregression) of the second order. Estimation in the presence of noise of observation of autoregression parameters using ordinary least square (OLS) gives biased estimates. Modifications of the two-stage estimation algorithm based on the use of the method of total least squares (TLS) and the method of extended instrumental variables (EIV), hyperbolic sine and cosine in the presence of errors in measurements are proposed. Numerical experiments have shown that the accuracy of the parameter estimation using the proposed modifications is higher than the accuracy of the estimate obtained using the ordinary least squares method (OLS).

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Natarajamoorthy, Mathan, Jayashri Subbiah, Nurul Ezaila Alias, and Michael Loong Peng Tan. "Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design." Journal of Nanotechnology 2020 (April 30, 2020): 1–7. http://dx.doi.org/10.1155/2020/7608279.

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The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

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BOTELHO, LUIZ C. L. "TURBULENT COLD PLASMA: AN EXACTLY PATH INTEGRAL SOLUTION IN A ZERO DIMENSIONAL MODEL AND ITS GENERALIZATIONS TO THE THREE-DIMENSIONAL-CASE." International Journal of Modern Physics B 13, no. 13 (1999): 1663–74. http://dx.doi.org/10.1142/s0217979299001648.

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We write path integrals exact solutions for a 0-dimensional noise (turbulent) force equation for an electronic plasma. We obtain that the equilibrium limit of the plasma tensor magneto conductivity coincides with the classical non-turbulent result in our 0-dimensional proposed model. Additionally, we show the usefulness of our reduced model by writing exact path integrals solutions for the probabilistic turbulent plasma occupation times. Finally, we point out three-dimensional generalizations of our path integral studies in two appendix.

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Fujitsu (Kobayashi). "Correlation Between Noise-After-Write and Magnetic Domain Structure Conversions in Thin-Film Heads by Electron Microscopy." Journal of the Magnetics Society of Japan 18, S_2_PMRC_94_2 (1994): S2_21–21. http://dx.doi.org/10.3379/jmsjmag.18.s2_21.

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Xing, X., and H. N. Bertram. "Analysis of the effect of write head field rise time on signal, noise, and nonlinear transition shift." Journal of Applied Physics 85, no. 8 (1999): 5861–63. http://dx.doi.org/10.1063/1.369941.

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Kobayashi, K. "Correlation between noise-after-write and magnetic domain structure conversions in thin-film heads by electron microscopy." IEEE Transactions on Magnetics 30, no. 6 (1994): 3933–35. http://dx.doi.org/10.1109/20.333948.

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Jiang, Wen, Gautam Khera, Roger Wood, Mason Williams, Neil Smith, and Yoshihiro Ikeda. "Cross-track noise profile measurement for adjacent-track interference study and write-current optimization in perpendicular recording." Journal of Applied Physics 93, no. 10 (2003): 6754–56. http://dx.doi.org/10.1063/1.1557716.

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Shim, Wonbo, Jae-sun Seo, and Shimeng Yu. "Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine." Semiconductor Science and Technology 35, no. 11 (2020): 115026. http://dx.doi.org/10.1088/1361-6641/abb842.

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Bota, Sebastià A., Jaume Verd, Xavier Gili, et al. "Design Issues for NEM-Relay-Based SRAM Devices." MATEC Web of Conferences 210 (2018): 01005. http://dx.doi.org/10.1051/matecconf/201821001005.

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We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays. Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays. Impact on important memory cell parameters such as various reliability metrics like static noise margin and write noise margin and power consumption are evaluated from circuit simulations using a Verilog-A compact model of the nanomechanical relay. We found that the use of relays involve a new challenge in the design of SRAM hybrid devices as the readability and writeability of the resulting cells manifests a strong dependence with the value of the contact resistance of the NEM relay, a parameter that can experience important variations with the continued operation of the device.

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RATHOD, S. S., A. K. SAXENA, and S. DASGUPTA. "DG-FINFET-BASED SRAM CONFIGURATIONS FOR INCREASED SEU IMMUNITY." Journal of Circuits, Systems and Computers 21, no. 04 (2012): 1250032. http://dx.doi.org/10.1142/s0218126612500326.

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In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to radiation. This is primarily due to the modification of the source potential used to reduce the effect of SEU without affecting normal operation. Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) and Power Delay Product (PDP) are the performance metrics computed for each type of SRAM cell. Effect of back gate voltage and back gate oxide thickness variation on device characteristic show detrimental effects on radiation hardened capabilities of a device. Benchmarking is done against DICE latch and it is found that as compared to DICE latch proposed DG-FinFET SRAM has low transistor count, less area, low recovery time and fault tolerance to internal as well as external nodes.

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Kawamura, S., Y. Okamoto, Y. Nakamura, H. Osawa, Y. Kanai, and H. Muraoaka. "Performance evaluation of signal dependent noise predictive maximum likelihood detector for two-dimensional magnetic recording read/write channel." Journal of Applied Physics 117, no. 17 (2015): 17D112. http://dx.doi.org/10.1063/1.4908145.

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Sharifkhani, Mohammad, and Manoj Sachdev. "An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 $\mu$m CMOS." IEEE Journal of Solid-State Circuits 44, no. 2 (2009): 620–30. http://dx.doi.org/10.1109/jssc.2008.2010815.

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Joshi, Shital, and Umar Alabawi. "Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM." Journal of Nanotechnology 2017 (2017): 1–9. http://dx.doi.org/10.1155/2017/4575013.

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CMOS technology below 10 nm faces fundamental limits which restricts its applicability for future electronic application mainly in terms of size, power consumption, and speed. In digital electronics, memory components play a very significant role. SRAM, due to its unique ability to retain data, is one of the most popular memory elements used in most of the digital devices. With aggressive technology scaling, the design of SRAM is seriously challenged in terms of delay, noise margin, and stability. This paper compares the performance of various CNTFET based SRAM cell topologies like 6T, 7T, 8T, 9T, and 10T cell with respect to static noise margin (SNM), write margin (WM), read delay, and power consumption. To consider the nonidealities of CNTFET, variations in tube diameter and effect of metallic tubes are considered for various structures with respect to various performance metrics like SNM, WM, read delay, and power consumption.

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Lin, Wei, Yan Yuan Zhang, and Zhan Huai Li. "A Real-Time Flash Memory Storage System in Embedded Environment." Advanced Materials Research 341-342 (September 2011): 807–10. http://dx.doi.org/10.4028/www.scientific.net/amr.341-342.807.

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Recently, flash memory is becoming a popular data storage device in most of the electronic consumer devices. It has lots of attractive features such as small size and light weight nature, zero noise, solid-state reliability, low power consumption, and better shock resistant. To make it suitable for real-time embedded applications, this paper presents the design of an object based file system that uses parallel operations to guarantee bounded read-write access latencies to real-time tasks, in the presence of requests from non real-time tasks. The proposed scheme requires minimal support from the underlying operating system.

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Calvia, Alessandro. "Stochastic filtering and optimal control of pure jump Markov processes with noise-free partial observation." ESAIM: Control, Optimisation and Calculus of Variations 26 (2020): 25. http://dx.doi.org/10.1051/cocv/2019020.

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We consider an infinite horizon optimal control problem for a pure jump Markov process X, taking values in a complete and separable metric space I, with noise-free partial observation. The observation process is defined as Yt = h(Xt), t ≥ 0, where h is a given map defined on I. The observation is noise-free in the sense that the only source of randomness is the process X itself. The aim is to minimize a discounted cost functional. In the first part of the paper we write down an explicit filtering equation and characterize the filtering process as a Piecewise Deterministic Process. In the second part, after transforming the original control problem with partial observation into one with complete observation (the separated problem) using filtering equations, we prove the equivalence of the original and separated problems through an explicit formula linking their respective value functions. The value function of the separated problem is also characterized as the unique fixed point of a suitably defined contraction mapping.

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Renukarani, S., Bhavana Godavarthi, SK Bia Roshini, and Mohammad Khadir. "A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array." International Journal of Engineering & Technology 7, no. 2.20 (2018): 109. http://dx.doi.org/10.14419/ijet.v7i2.20.12185.

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A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to sub-nanometer engineering technology.

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Kumar, Brijesh, Brajesh Kumar Kaushik, and Yuvraj Singh Negi. "Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAM cell." Microelectronics Reliability 54, no. 12 (2014): 2801–12. http://dx.doi.org/10.1016/j.microrel.2014.08.012.

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Journal articles on the topic 'Write Noise'

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