Relevant bibliographies by topics / Writer synchronization

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Writer synchronization'

Author: Grafiati
Published: 4 June 2021
Last updated: 13 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Writer synchronization.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Writer synchronization"

1

Mellor-Crummey, John M., and Michael L. Scott. "Scalable reader-writer synchronization for shared-memory multiprocessors." ACM SIGPLAN Notices 26, no. 7 (1991): 106–13. http://dx.doi.org/10.1145/109626.109637.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Brandenburg, Björn B., and James H. Anderson. "Spin-based reader-writer synchronization for multiprocessor real-time systems." Real-Time Systems 46, no. 1 (2010): 25–87. http://dx.doi.org/10.1007/s11241-010-9097-2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Maryanto, Ahmad, Nugroho Widijatmiko, Wismu Sunarmodo, Muhammad Soleh, and Rahmat Arief. "DEVELOPMENT OF PUSHBROOM AIRBORNE CAMERA SYSTEM USING MULTISPECTRUM LINE SCAN INDUSTRIAL CAMERA." International Journal of Remote Sensing and Earth Sciences (IJReSES) 13, no. 1 (2017): 27. http://dx.doi.org/10.30536/j.ijreses.2016.v13.a2701.

Full text
Abstract:
One of the steps on mastery the remote sensing technology (inderaja) for satellite was the development of aerial camera prototype that could be an alternative for LAPAN light cargo aircraft mission (LAPAN Surveillance Aircraft, LSA-01). This system was expected could be operated to fulfill the emptiness or change the remote sensing data of optical satellite as the observer of vegetation covered by cloud. On this research, it was developed a prototype of pushbroom airborne camera 4-channels spectrum with very high resolution that worked on wavelength range seem near infra-red/ NIR used simple components that were available in the commercial market (commercial off-the-shelf/ COTS components). This research also developed georeference imagery software module used method of direct georeference rigorous model that had been applied on SPOT satellite. For this one, it was installed supported sensory for GPS and IMU as the writer of location coordinate and camera behavior while doing the imagery exposure or acquisition. The testing result gave confirmation that COTS components, such as industry camera LQ-200CL, and lower class GPS and IMU could be integrated became a cheaper remote sensing system, which its imagery product could be corrected systematically. The corrected data product showed images with GSD 0.4m still had positioning mistakes on average 157m (400 pixel) from the original position on GoogleEarth. On spectro-radiomatic aspect, the used camera had much higher sensitivity of NIR channel than the looked-channel so it caused bored faster. On the future, this system needed to be fixed by increasing the rate of GPS/ IMU data updates, and increased enough time resolution system so that the synchronization process and the availability supported data for completing more accurate georeference process. Besides, the sensitivity of NIR channel needed to be lower down to make it balance to the looked-channel.
APA, Harvard, Vancouver, ISO, and other styles
4

Yawshing Tang, Kiseok Moon, and Hyung Jai Lee. "Write Synchronization in Bit-Patterned Media." IEEE Transactions on Magnetics 45, no. 2 (2009): 822–27. http://dx.doi.org/10.1109/tmag.2008.2010642.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Kawash, Jalal. "Process Synchronization with Readers and Writers Revisited." Journal of Computing and Information Technology 13, no. 1 (2005): 43. http://dx.doi.org/10.2498/cit.2005.01.04.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Gao, Jintao, Wenjie Liu, and Zhanhuai Li. "A Strategy of Data Synchronization in Distributed System with Read Separating from Write." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 38, no. 1 (2020): 209–15. http://dx.doi.org/10.1051/jnwpu/20203810209.

Full text
Abstract:
Read separating from write is a strategy that NewSQL adopts to incorporate the advantages of traditional relation database and NoSQL database. Under this architecture, baseline data is split into multiple partitions stored at distributed physical nodes, while delta data is stored at single transaction node. For reducing the pressure of transaction node and improving the query performance, delta data needs to be synchronized into storage nodes. The current strategies trigger the procedure of data synchronization per partition, meaning that unchanged partitions will also participate in data synchronization, which consumes extra network cost, local IO and space resources. For improving the efficiency of data synchronization meanwhile mitigating space utilization, the fine-grained data synchronization strategy is proposed, whose main idea includes that fine-grained logical partitions upon original coarse-grained partitions is established, providing more correct synchronized unit; the delta data sensing strategy is introduced, which records the mapping between changed partitions and its delta data; instead of partition driven, the data synchronization through the delta-broadcasting mechanism is driven, constraining that only changed partitions can participate in data synchronization. The fine-grained data synchronization strategy on Oceanbase is implemented, which is a distributed database with read separating from write, and the results show that our strategy is better than other strategies in efficiency of data synchronizing and space utilization.
APA, Harvard, Vancouver, ISO, and other styles
7

Hara, Akihiro, Hiroaki Muraoka, and Simon J. Greaves. "Write synchronization for position-correlated granular media." Journal of Applied Physics 117, no. 17 (2015): 17A909. http://dx.doi.org/10.1063/1.4916497.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Lin, M. Y., J. W. M. Bergmans, G. Mathew, and S. W. Foo. "Characterization with embedded synchronization for read-write channels." IEEE Transactions on Magnetics 37, no. 4 (2001): 1953–56. http://dx.doi.org/10.1109/20.951019.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

WU, Jian-jun. "Distributed bus synchronization algorithm based on read/write characteristics." Journal of Computer Applications 28, no. 1 (2008): 11–13. http://dx.doi.org/10.3724/sp.j.1087.2008.00011.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Lin, Maria Yu, Kheong Sann Chan, Melissa Chua, Songhua Zhang, Cai Kui, and Moulay Rachid Elidrissi. "Modeling for write synchronization in bit patterned media recording." Journal of Applied Physics 111, no. 7 (2012): 07B918. http://dx.doi.org/10.1063/1.3679022.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Writer synchronization"

1

Vallejo, Gutiérrez Enrique. "Soporte arquitectónico a la sincronización imparcial de lectores y escritores en computadores paralelos." Doctoral thesis, Universidad de Cantabria, 2010. http://hdl.handle.net/10803/10637.

Full text
Abstract:
La evolución tecnológica en el diseño de microprocesadores ha conducido a sistemas paralelos con múltiples hilos de ejecución. Estos sistemas son más difíciles de programar y presentan overheads mayores que los sistemas uniprocesadores tradicionales, que pueden limitar su rendimiento y escalabilidad: sincronización, coherencia, consistencia y otros mecanismos requeridos para garantizar una ejecución correcta. La programación paralela tradicional se basa en primitivas de sincronización como barreras y locks de lectura/escritura, con alta tendencia a fallos de programación. La Memoria Transaccional (TM) oculta estos problemas de sincronización al programador; sin embargo, múltiples sistemas TM aún se basan en locks, y se beneficiarían de una implementación eficiente de los mismos.Esta tesis presenta nuevas técnicas hardware para acelerar la ejecución de estos programas paralelos. Proponemos un sistema TM híbrido basado en locks de lectura/escritura, que minimiza los overheads del software cuando la aceleración hardware está presente. Desarrollamos un mecanismo para garantizar fairness entre transacciones hardware y software. Introducimos un mecanismo distribuido de aceleración de locks de lectura/escritura, llamado Lock Control Unit. Finalmente, proponemos una organización de multiprocesadores basadas en Kilo-Instruction Processors que garantiza Consistencia Secuencial y permite especulación en secciones críticas.<br>Technological evolution in microprocessor design has led to parallel systems with multiple execution threads. These systems are more difficult to program and present higher performance overheads than the traditional uniprocessor systems, what may limit their performance and scalability: synchronization, coherence, consistency and other mechanisms required to guarantee a correct execution. Traditional parallel programming is based on synchronization primitives such as barriers, critical sections and reader/writer locks, highly prone to programming errors. Transactional Memory (TM) removes the synchronization problems from the programmer. However, many TM systems still rely on reader/writer locks, and would get benefited from an efficient implementation.This thesis presents new hardware techniques to accelerate the execution of such parallel programs. We propose a Hybrid TM system based on reader/writer locks, which minimizes the software overheads when acceleration hardware is present, still allowing for correct software-only execution. We propose a mechanism to guarantee fairness between hardware and software transactions is provided. We introduce a low-cost distributed mechanism named the Lock Control Unit to handle fine-grain reader-writer locks. Finally, we propose an organization of a mutiprocessor based on Kilo-Instruction Processors, which guarantees Sequential Consistency while allowing for speculation in critical sections.
APA, Harvard, Vancouver, ISO, and other styles
2

Rajaram, Bharghava. "Efficient, scalable, and fair read-modify-writes." Thesis, University of Edinburgh, 2015. http://hdl.handle.net/1842/10530.

Full text
Abstract:
Read-Modify-Write (RMW) operations, or atomics, have widespread application in (a) synchronization, where they are used as building blocks of various synchronization constructs like locks, barriers, and lock-free data structures (b) supervised memory systems, where every memory operation is effectively an RMW that reads and modifies metadata associated with memory addresses and (c) profiling, where RMW instructions are used to increment shared counters to convey meaningful statistics about a program. In each of these scenarios, the RMWs pose a bottleneck to performance and scalability. We observed that the cost of RMWs is dependent on two major factors – the memory ordering enforced by the RMW, and contention amongst processors performing RMWs to the same memory address. In the case of both synchronization and supervised memory systems, the RMWs are expensive due to the memory ordering enforced due to the atomic RMW operation. Performance overhead due to contention is more prevalent in parallel programs which frequently make use of RMWs to update concurrent data structures in a non-blocking manner. Such programs also suffer from a degradation in fairness amongst concurrent processors. In this thesis, we study the cost of RMWs in the above applications, and present solutions to obtain better performance and scalability from RMW operations. Firstly, this thesis tackles the large overhead of RMW instructions when used for synchronization in the widely used x86 processor architectures, like in Intel, AMD, and Sun processors. The x86 processor architecture implements a variation of the Total-Store-Order (TSO) memory consistency model. RMW instructions in existing TSO architectures (we call them type-1 RMW) are ordered like memory fences, which makes them expensive. The strong fence-like ordering of type-1 RMWs is unnecessary for the memory ordering required by synchronization. We propose weaker RMW instructions for TSO consistency; we consider two weaker definitions: type-2 and type-3, each causing subtle ordering differences. Type-2 and type-3 RMWs avoid the fence-like ordering of type-1 RMWs, thereby reducing their overhead. Recent work has shown that the new C/C++11 memory consistency model can be realized by generating type-1 RMWs for SC-atomic-writes and/or SC-atomic-reads. We formally prove that this is equally valid for the proposed type-2 RMWs, and partially for type-3 RMWs. We also propose efficient implementations for type-2 (type-3) RMWs. Simulation results show that our implementation reduces the cost of an RMW by up to 58.9% (64.3%), which translates into an overall performance improvement of up to 9.0% (9.2%) for the programs considered. Next, we argue the case for an efficient and correct supervised memory system for the TSO memory consistency model. Supervised memory systems make use of RMW-like supervised memory instructions (SMIs) to atomically update metadata associated with every memory address used by an application program. Such a system is used to help increase reliability, security and accuracy of parallel programs by offering debugging/monitoring features. Most existing supervised memory systems assume a sequentially consistent memory. For weaker consistency models, like TSO, correctness issues (like imprecise exceptions) arise if the ordering requirement of SMIs is neglected. In this thesis, we show that it is sufficient for supervised instructions to only read and process their metadata in order to ensure correctness. We propose SuperCoP, a supervised memory system for relaxed memory models in which SMIs read and process metadata before retirement, while allowing data and metadata writes to retire into the write-buffer. Our experimental results show that SuperCoP performs better than the existing state-of-the-art correct supervision system by 16.8%. Finally, we address the issue of contention and contention-based failure of RMWs in non-blocking synchronization mechanisms. We leverage the fact that most existing lock-free programs make use of compare-and-swap (CAS) loops to access the concurrent data structure. We propose DyFCoM (Dynamic Fairness and Contention Management), a holistic scheme which addresses both throughput and fairness under increased contention. DyFCoM monitors the number of successful and failed RMWs in each thread, and uses this information to implement a dynamic backoff scheme to optimize throughput. We also use this information to throttle faster threads and give slower threads a higher chance of performing their lock-free operations, to increase fairness among threads. Our experimental results show that our contention management scheme alone performs better than the existing state-of-the-art CAS contention management scheme by an average of 7.9%. When fairness management is included, our scheme provides an average of 3.4% performance improvement over the constant backoff scheme, while showing increased fairness values in all cases (up to 43.6%).
APA, Harvard, Vancouver, ISO, and other styles
3

Howard, Philip William. "Extending Relativistic Programming to Multiple Writers." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/114.

Full text
Abstract:
For software to take advantage of modern multicore processors, it must be safely concurrent and it must scale. Many techniques that allow safe concurrency do so at the expense of scalability. Coarse grain locking allows multiple threads to access common data safely, but not at the same time. Non-Blocking Synchronization and Transactional Memory techniques optimistically allow concurrency, but only for disjoint accesses and only at a high performance cost. Relativistic programming is a technique that allows low overhead readers and joint access parallelism between readers and writers. Most of the work on relativistic programming has assumed a single writer at a time (or, in partitionable data structures, a single writer per partition), and single writer solutions cannot scale on the write side. This dissertation extends prior work on relativistic programming in the following ways: 1) It analyses the ordering requirements of lock-based and relativistic programs in order to clarify the differences in their correctness and performance characteristics, and to define precisely the behavior required of the relativistic programming primitives. 2) It shows how relativistic programming can be used to construct efficient, scalable algorithms for complex data structures whose update operations involve multiple writes to multiple nodes. 3) It shows how disjoint access parallelism can be supported for relativistic writers, using Software Transactional Memory, while still allowing low-overhead, linearly-scalable, relativistic reads.
APA, Harvard, Vancouver, ISO, and other styles
4

Baier, Christel, Benjamin Engel, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, and Marcus Völp. "A Probabilistic Quantitative Analysis of Probabilistic-Write/Copy-Select." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-129917.

Full text
Abstract:
Probabilistic-Write/Copy-Select (PWCS) is a novel synchronization scheme suggested by Nicholas Mc Guire which avoids expensive atomic operations for synchronizing access to shared objects. Instead, PWCS makes inconsistencies detectable and recoverable. It builds on the assumption that, for typical workloads, the probability for data races is very small. Mc Guire describes PWCS for multiple readers but only one writer of a shared data structure. In this paper, we report on the formal analysis of the PWCS protocol using a continuous-time Markov chain model and probabilistic model checking techniques. Besides the original PWCS protocol, we also considered a variant with multiple writers. The results were obtained by the model checker PRISM and served to identify scenarios in which the use of the PWCS protocol is justified by guarantees on the probability of data races. Moreover, the analysis showed several other quantitative properties of the PWCS protocol.
APA, Harvard, Vancouver, ISO, and other styles
5

Radovic, Zoran. "Software Techniques for Distributed Shared Memory." Doctoral thesis, Uppsala University, Department of Information Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-6058.

Full text
Abstract:
<p>In large multiprocessors, the access to shared memory is often nonuniform, and may vary as much as ten times for some distributed shared-memory architectures (DSMs). This dissertation identifies another important nonuniform property of DSM systems: <i>nonuniform communication architecture</i>, NUCA. High-end hardware-coherent machines built from large nodes, or from chip multiprocessors, are typical NUCA systems, since they have a lower penalty for reading recently written data from a neighbor's cache than from a remote cache. This dissertation identifies <i>node affinity</i> as an important property for scalable general-purpose locks. Several software-based hierarchical lock implementations exploiting NUCAs are presented and evaluated. NUCA-aware locks are shown to be almost twice as efficient for contended critical sections compared to traditional lock implementations.</p><p>The shared-memory “illusion”' provided by some large DSM systems may be implemented using either hardware, software or a combination thereof. A software-based implementation can enable cheap cluster hardware to be used, but typically suffers from poor and unpredictable performance characteristics.</p><p>This dissertation advocates a new software-hardware trade-off design point based on a new combination of techniques. The two low-level techniques, fine-grain deterministic coherence and synchronous protocol execution, as well as profile-guided protocol flexibility, are evaluated in isolation as well as in a combined setting using all-software implementations. Finally, a minimum of hardware trap support is suggested to further improve the performance of coherence protocols across cluster nodes. It is shown that all these techniques combined could result in a fairly stable performance on par with hardware-based coherence.</p>
APA, Harvard, Vancouver, ISO, and other styles
6

Golab, Wojciech. "Constant-RMR Implementations of CAS and Other Synchronization Primitives Using Read and Write Operations." Thesis, 2010. http://hdl.handle.net/1807/26182.

Full text
Abstract:
We consider asynchronous multiprocessors where processes communicate only by reading or writing shared memory. We show how to implement consensus, all comparison primitives (such as CAS and TAS), and load-linked/store-conditional using only a constant number of remote memory references (RMRs), in both the cache-coherent and the distributed-shared-memory models of such multiprocessors. Our implementations are blocking, rather than wait-free: they ensure progress provided all processes that invoke the implemented primitive are live. Our results imply that any algorithm using read and write operations, comparison primitives and load-linked/store-conditional, can be simulated by an algorithm that uses read and write operations only, with at most a constant-factor increase in RMR complexity.
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Writer synchronization"

1

Gustedt, Jens, and Emmanuel Jeanvoine. "Relaxed Synchronization with Ordered Read-Write Locks." In Euro-Par 2011: Parallel Processing Workshops. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-29737-3_43.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Thomas, Roshan K., and Ravi S. Sandhu. "Concurrency, Synchronization, and Scheduling to Support High-assurance Write-up in Multilevel Object-based Computing." In Security for Object-Oriented Systems. Springer London, 1994. http://dx.doi.org/10.1007/978-1-4471-3858-7_16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Krishna, Siddharth, Michael Emmi, Constantin Enea, and Dejan Jovanović. "Verifying Visibility-Based Weak Consistency." In Programming Languages and Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-44914-8_11.

Full text
Abstract:
AbstractMultithreaded programs generally leverage efficient and thread-safe concurrent objects like sets, key-value maps, and queues. While some concurrent-object operations are designed to behave atomically, each witnessing the atomic effects of predecessors in a linearization order, others forego such strong consistency to avoid complex control and synchronization bottlenecks. For example, contains (value) methods of key-value maps may iterate through key-value entries without blocking concurrent updates, to avoid unwanted performance bottlenecks, and consequently overlook the effects of some linearization-order predecessors. While such weakly-consistent operations may not be atomic, they still offer guarantees, e.g., only observing values that have been present.In this work we develop a methodology for proving that concurrent object implementations adhere to weak-consistency specifications. In particular, we consider (forward) simulation-based proofs of implementations against relaxed-visibility specifications, which allow designated operations to overlook some of their linearization-order predecessors, i.e., behaving as if they never occurred. Besides annotating implementation code to identify linearization points, i.e., points at which operations’ logical effects occur, we also annotate code to identify visible operations, i.e., operations whose effects are observed; in practice this annotation can be done automatically by tracking the writers to each accessed memory location. We formalize our methodology over a general notion of transition systems, agnostic to any particular programming language or memory model, and demonstrate its application, using automated theorem provers, by verifying models of Java concurrent object implementations.
APA, Harvard, Vancouver, ISO, and other styles
4

Smith, Ronnie W., and D. Richard Hipp. "System Implementation." In Spoken Natural Language Dialog Systems. Oxford University Press, 1995. http://dx.doi.org/10.1093/oso/9780195091878.003.0008.

Full text
Abstract:
Without development of an actual working system it is impossible to empirically validate the proposed computational model. Thus, the architecture introduced in section 3.1 has been implemented on a Sun 4 workstation and later ported to a Spare II workstation. The majority of the code is written in Quintus Prolog while the parser is written in C. The system software is available via anonymous FTP as described in appendix C. The overall hardware configuration is illustrated in figure 6.1. Speech recognition is performed by a Verbex 6000 user-dependent connected-speech recognizer running on an IBM PC. The vocabulary is currently restricted to the 125 words given in table 7.1. Users are required to begin each utterance with the word “verbie” and end with the word “over” (e.g. “verbie, the switch is up, over”). The Verbex speech recognizer acknowledges each input with a small beep. These sentinel interactions act as a synchronization mechanism for the user arid the machine. Speech output is performed by a DECtalk DTCO1 text-to-speech converter. This chapter discusses the following technical aspects of the implementation. • The various knowledge representation formalisms. • The implemented domain processor, an expert system for assisting in simple circuit repair. • The implemented generation component. • The basic physical resource utilization of the system. The basis for the implementation has been the logic programming language, Prolog. Clocksin and Mellish [CM87] provide an introduction to this language. Pereira and Shieber [PS87] arid McCord [McC87] can be consulted for a discussion of the usage of Prolog for natural language analysis. Prolog allows the expression of rules and facts in a subset of first-order logic called Horn clauses. Prolog is supplemented with non-logical features that aid in efficient computation as well, but as a representational formalism, its utility in representing rules and facts in a declarative format provides a basis for the representation of knowledge and rules within the model. The Goal and Action Description Language was introduced in section 3.2.2. A detailed description is provided in appendix A. It is used as a standard formalism for representing goals that may be accomplished during a task.
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Writer synchronization"

1

Bhatt, Vibhor, and Prasad Jayanti. "Constant RMR solutions to reader writer synchronization." In Proceeding of the 29th ACM SIGACT-SIGOPS symposium. ACM Press, 2010. http://dx.doi.org/10.1145/1835698.1835803.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Mellor-Crummey, John M., and Michael L. Scott. "Scalable reader-writer synchronization for shared-memory multiprocessors." In the third ACM SIGPLAN symposium. ACM Press, 1991. http://dx.doi.org/10.1145/109625.109637.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Brandenburg, Björn B., and James H. Anderson. "Reader-Writer Synchronization for Shared-Memory Multiprocessor Real-Time Systems." In 2009 21st Euromicro Conference on Real-Time Systems (ECRTS). IEEE, 2009. http://dx.doi.org/10.1109/ecrts.2009.14.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Nakamura, Shigenari, Dilewaer Duolikun, Ailixier Aikebaier, Tomoya Enokido, and Makoto Takizaw. "Read-Write Abortion (RWA) Based Synchronization Protocols to Prevent Illegal Information Flow." In 2014 17th International Conference on Network-Based Information Systems (NBiS). IEEE, 2014. http://dx.doi.org/10.1109/nbis.2014.48.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Fatourou, Panagiota. "Low-contention depth-first scheduling of parallel computations with write-once synchronization variables." In the thirteenth annual ACM symposium. ACM Press, 2001. http://dx.doi.org/10.1145/378580.378639.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Golab, Wojciech, Vassos Hadzilacos, Danny Hendler, and Philipp Woelfel. "Constant-RMR implementations of CAS and other synchronization primitives using read and write operations." In the twenty-sixth annual ACM symposium. ACM Press, 2007. http://dx.doi.org/10.1145/1281100.1281105.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Ahmad, Noraziah, Roslina Mohd Sidek, Mohammad Fadel Jamil Klaib, and Tito Lamat Jayan. "A Novel Algorithm of Managing Replication and Transaction through Read-one-Write-All Monitoring Synchronization Transaction System (ROWA-MSTS)." In 2010 Second International Conference on Network Applications Protocols and Services (NETAPPS). IEEE, 2010. http://dx.doi.org/10.1109/netapps.2010.11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Writer synchronization' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography