Relevant bibliographies by topics / Xilinx

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Xilinx'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Xilinx"

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Tyler, Neil. "Xilinx Unveils Versal." New Electronics 51, no. 18 (2018): 9. http://dx.doi.org/10.12968/s0047-9624(23)60681-9.

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Tyler, Neil. "Xilinx Unveils Unified Software Platform." New Electronics 51, no. 18 (2019): 7. http://dx.doi.org/10.12968/s0047-9624(22)61426-3.

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Tyler, Neil. "Xilinx Unveils Adaptable Accelerator Card." New Electronics 52, no. 15 (2019): 9. http://dx.doi.org/10.12968/s0047-9624(22)61404-4.

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Tyler, Neil. "Xilinx Unveils Space-Grade FPGA." New Electronics 53, no. 10 (2020): 7. http://dx.doi.org/10.12968/s0047-9624(22)61249-5.

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Anthony Prathap, Joseph, T. S.Anandhi, K. Ramash Kumar, and B. Srikanth. "Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA." International Journal of Engineering & Technology 7, no. 2.8 (2018): 570. http://dx.doi.org/10.14419/ijet.v7i2.8.10523.

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This paper proposes the design of 64-Quadrature Amplitude Modulation using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and XILINX SPARTAN Field Programmable Gate Array (FPGA) real-time implementation for validation. QAM is used in modern digital communication applications like set-top box, satellite TV, wireless and cellular technology etc. In this paper, 64-QAM is implemented and compared with three different XILINX SPARTAN FPGA devices say 3A DSP, 3E and 6E. The power, current and thermal parameters are performed and compared. The power consumed for the
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Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse
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Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

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<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switchi
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R., Palanisamy, S. Boopathi C., Selvakumar K., and Vijayakumar K. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1722–27. https://doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse
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Тарасов, И. "АРХИТЕКТУРА И ОБЛАСТИ ПРИМЕНЕНИЯ ПЛИС XILINX VERSAL". ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 211, № 10 (2021): 136–40. http://dx.doi.org/10.22184/1992-4178.2021.211.10.136.140.

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Рассмотрены ПЛИС Xilinx Versal. Отмечено, что их особенностью является добавление на кристалл матрицы процессоров с архитектурой VLIW. Приведена информация об архитектуре, характеристиках и областях применения ПЛИС Xilinx Versal.
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ADHYANA, GUPTA. "HARDWARE SOFTWARE CO-SIMULATION FOR TRAFFIC LOAD COMPUTATION USING MATLAB SIMULINK MODEL BLOCKSET." International Journal of Computational Science and Information Technology (IJCSITY) 1, May (2013): 1–12. https://doi.org/10.5281/zenodo.3597180.

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<strong>ABSTRACT</strong> Due to increase in number of vehicles, Traffic is a major problem faced in urban areas throughout the world. This document presents a newly developed Matlab Simulink model to compute traffic load for real time traffic signal control. Signal processing, video and image processing and Xilinx Blockset have been extensively used for traffic load computation. The approach used is Edge detection operation, wherein, Edges are extracted to identify the number of vehicles. The developed model computes the results with greater degrees of accuracy and is capable of being used to
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Dissertations / Theses on the topic "Xilinx"

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Möhrke, Ulrich, Paul Herrmann, and Marco Schmidt. "Das Xilinx-LCA-Format." Universität Leipzig, 1996. https://ul.qucosa.de/id/qucosa%3A34507.

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Es wird eine kurze Beschreibung des LCA-Formats gegeben. Dateien dieses Formats werden im Design Flow des XACT Systems von Xilinx als Ausgabe der Plazier- und Verdrahtungsprogramme APR bzw. PPR erzeugt. Bei der hier gegebenen kurzen Beschreibung stehen die Angaben zur Verdrahtung im Vordergrund.
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Fandén, Petter. "Evaluation of Xilinx System Generator." Thesis, Linköping University, Department of Science and Technology, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1033.

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<p>This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG) and blockset for Matlab. XSG is a module to simulink developed by Xilinx in order to generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm. </p><p>In order to investigate the performance of this new module XSG to simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without
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Krohn, Jørgen, and Jørgen Linnerud. "MPEG Transcoder for Xilinx Spartan." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8896.

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<p>In this project the focus has been on developing an MPEG transcoder that can be used as a demonstration module for the AHEAD system, Ambient Hardware: Embedded Architecture on Demand. AHEAD is a collaboration project between NTNU and SINTEF in Trondheim that is aiming to develop a method of doing run-time reconfiguration of hardware. The AHEAD system will in the future use an FPGA in a tag that is able to reconfigure itself with hardware description that it receives from a hand-held device, e.g. a PDA, or downloads from the Internet. The tag will then be able to be operating as a co-process
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Yue, Xi. "Rapid Overlay Builder for Xilinx FPGAs." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/50907.

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A field-programmable gate array (FPGA) is a type of programmable hardware, where a logic designer must create a specific hardware design and then "compile" it into a bitstream that "configures" the device for a specific function at power-up. This compiling process, known as place-and-route (PAR), can take hours or even days, a duration which discourages the use of FPGAs for solving compute-oriented problems. To help mitigate this and other problems, overlays are emerging as useful design patterns in solving compute-oriented problems. An overlay consists of a set of compiler-like tools and an a
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Nyman, Jeremia. "High Speed IO using Xilinx Aurora." Thesis, Linköpings universitet, Institutionen för systemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102424.

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A VHDL evaluation platform and interface to the Xilinx Aurora 8b/10b IP has been designed, tested and evaluated. The evaluation platform takes an arbitrary amount of data sources and sends the data over 1,2,4 or 8 multi gigabit serial lanes, using the Aurora 8b/10b protocol. A lightweight communications protocol for point-to-point data transfer, error detection and recovery is used to maintain a reliable and efficient transmission scheme. Priority between sources sharing the serial link is also a part of the platform. The Aurora 8b/10b IP is a lightweight protocol and transceiver interface for
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Жданова, Ю. В., та І. В. Свид. "Огляд сьомої серії FPGA компанії Xilinx". Thesis, Кременчуцький льотний коледж, 2019. http://openarchive.nure.ua/handle/document/9371.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://doi.org/10.35598/mcfpga.2019.008.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-008.

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Morford, Casey Justin. "BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/36198.

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With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level
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Eriksson, Henrik. "Datorstödd implementering med hjälp av Xilinx System Generator." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2159.

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<p>The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. </p><p>Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. </p><p>The testcases are selected to represent the FPGA designs ma
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Books on the topic "Xilinx"

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Churiwala, Sanjay, ed. Designing with Xilinx® FPGAs. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-42438-5.

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Ferry, Pierre-Marie. Cache simulator on a Xilinx. University of Manchester, Department of Computer Science, 1996.

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inc, Prentice Hall, ed. The practical XILINX designers lab book. Prentice Hall, 1997.

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Chaoying, Wang, ed. Digital electronics laboratory experiments: Using the Xilinx XC95108 CPLD with Xilinx design and simulation software. 2nd ed. Pearson/Prentice Hall, 2004.

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Yeh, David Chun-Chin. A multiprocessor Viterbi decoder using Xilinx FPGAs. National Library of Canada, 1995.

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Chu, Pong P. FPGA prototyping by VHDL examples: Xilinx Spartan-3 version. Wiley-Interscience, 2008.

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Zotov, Valerij Ûr'evič. Proektirovanie cifrovyh ustrojstv na osnove plis firmy XILINX v SAPR WebPACK ISE. Gorâčaâ liniâ - Telekom, 2003.

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Sari, Mehmet. Designing fast Golay encoder/decoder in Xilinx XACT with Mentor Graphics CAD interface. Naval Postgraduate School, 1997.

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Inc, Xilinx. The programmable gate array data book. Xilinx, Inc., 1992.

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Ge, Peng. Xu Xilin. Jin lan chu ban she, 1985.

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Book chapters on the topic "Xilinx"

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Jayaraman, Rajeev. "ICCAD and Xilinx." In The Best of ICCAD. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0292-0_58.

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Meyer-Baese, Uwe. "Xilinx MicroBlaze Embedded Microprocessor." In Embedded Microprocessor System Design using FPGAs. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-50533-2_10.

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Meyer-Baese, Uwe. "Xilinx MicroBlaze Embedded Microprocessor." In Embedded Microprocessor System Design using FPGAs. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-82822-5_10.

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Taraate, Vaibbhav. "Design Implementation Using Xilinx Vivado." In PLD Based Design with VHDL. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3296-7_11.

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Deschamps, Jean-Pierre, Gustavo D. Sutter, and Enrique Cantó. "Partial Reconfiguration on Xilinx FPGAs." In Lecture Notes in Electrical Engineering. Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-2987-2_16.

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Hartenstein, Reiner W., Michael Herz, and Frank Gilbert. "Designing for Xilinx XC6200 FPGAs." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0055230.

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Gangadharan, Sridhar, Sanjay Churiwala, and Frederic Revenu. "XDC: Xilinx Extensions to SDC." In Constraining Designs for Synthesis and Timing Analysis. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-3269-2_17.

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Taylor, Brad. "State-of-the-Art Programmable Logic." In Designing with Xilinx® FPGAs. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-42438-5_1.

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Mackay, Duncan. "C-Based Design." In Designing with Xilinx® FPGAs. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-42438-5_10.

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Bandopadhyay, Saikat. "Simulation." In Designing with Xilinx® FPGAs. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-42438-5_11.

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Conference papers on the topic "Xilinx"

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Rajeev, Renju. "Modeling Xilinx Ultrascale FPGA Fabric with FABulous." In 2024 Eighth International Conference on Parallel, Distributed and Grid Computing (PDGC). IEEE, 2024. https://doi.org/10.1109/pdgc64653.2024.10984091.

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Freeman, Ross, James V. Barnett, and Bernard V. Vonderschmitt. "Xilinx Edge Processors." In 2021 IEEE Hot Chips 33 Symposium (HCS). IEEE, 2021. http://dx.doi.org/10.1109/hcs52781.2021.9567521.

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Voogel, Martin, Yohan Frans, Matt Ouellette, et al. "Xilinx Versal™ Premium." In 2020 IEEE Hot Chips 32 Symposium (HCS). IEEE, 2020. http://dx.doi.org/10.1109/hcs49909.2020.9220682.

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Gaide, Brian, Dinesh Gaitonde, Chirag Ravishankar, and Trevor Bauer. "Xilinx Adaptive Compute Acceleration Platform." In FPGA '19: The 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2019. http://dx.doi.org/10.1145/3289602.3293906.

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Kathail, Vinod. "Xilinx Vitis Unified Software Platform." In FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2020. http://dx.doi.org/10.1145/3373087.3375887.

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Jorge, Carlos Antonio, Alexandre Nery, and Alba Melo. "Uma implementação do algoritmo LCS em FPGA usando High-Level Synthesis." In XX Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2019. http://dx.doi.org/10.5753/wscad.2019.8679.

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Este trabalho apresenta uma implementação do algoritmo Longest Common Subsequence (LCS) para comparação de duas sequências biológicas utilizando linguagem de alto nı́vel High Level Synthesis (HLS) para FPGAs. Foram comparados resultados entre a execução em uma CPU Intel Core i73770 e uma FPGA Xilinx® ADM-PCIE-KU3 que possui uma Xilinx Kintex® UltraScale XCKU060-2. Os resultados mostraram que a implementação em CPU consumiu 6,8x mais energia em relação à FPGA.
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Xiang, Zong Jie, Liheng Wang, Lanlai Wang, Xiaohai Hu, and Junjun Wan. "Carry Chain Test of Xilinx FPGA." In 2019 IEEE 2nd International Conference on Electronics and Communication Engineering (ICECE). IEEE, 2019. http://dx.doi.org/10.1109/icece48499.2019.9058523.

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"Tutorial T7: Designing with Xilinx SDSoC." In 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID). IEEE, 2017. http://dx.doi.org/10.1109/vlsid.2017.97.

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Svyd, Iryna, Oleksandr Maltsev, Liliia Saikivska, and Oleg Zubkov. "Review of Seventh Series FPGA Xilinx." In Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs. Kharkiv National University of Radio Electronics, 2019. http://dx.doi.org/10.35598/mcfpga.2019.008.

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Fifield, Jeff, Ronan Keryell, Hervé Ratigner, Henry Styles, and Jim Wu. "Optimizing OpenCL applications on Xilinx FPGA." In IWOCL '16: The 4th International Workshop on OpenCL. ACM, 2016. http://dx.doi.org/10.1145/2909437.2909447.

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Reports on the topic "Xilinx"

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Tripp, Justin, Robert Clanton, Robert Merl, Paul Graham, and Zachary Baker. LANL SpaceVPX Xilinx KU060 Processor. Office of Scientific and Technical Information (OSTI), 2021. http://dx.doi.org/10.2172/1781358.

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Jin, Zheming, Hal Finkel, Kazutomo Yoshii, and Franck Cappello. Evaluation of the FIR Example using Xilinx Vivado High-Level Synthesis Compiler. Office of Scientific and Technical Information (OSTI), 2017. http://dx.doi.org/10.2172/1375449.

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Diehl, William, and Edward Viveiros. Xilinx RF System-on-Chip (RFSoC) 100 Gigabit Ethernet Loop-back Demonstration. DEVCOM Army Research Laboratory, 2022. http://dx.doi.org/10.21236/ad1156777.

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RADDER, JERAHMIE WILLIAM. Implementation of a High Throughput Variable Decimation Pane Filter Using the Xilinx System Generator. Office of Scientific and Technical Information (OSTI), 2003. http://dx.doi.org/10.2172/808628.

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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Office of Scientific and Technical Information (OSTI), 2011. http://dx.doi.org/10.2172/1013229.

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Learn, Mark Walter. Evaluation of the Leon3 soft-core processor within a Xilinx radiation-hardened field-programmable gate array. Office of Scientific and Technical Information (OSTI), 2012. http://dx.doi.org/10.2172/1035332.

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