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Relevant bibliographies by topics / Xilinx ARTIX 7

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Academic literature on the topic 'Xilinx ARTIX 7'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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Journal articles on the topic "Xilinx ARTIX 7"

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Alshehry, Awwad H., Saleh M. Alshahry, Abdullah K. Alhazmi, and Vamsy P. Chodavarapu. "A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters." Sensors 23, no. 18 (2023): 7672. http://dx.doi.org/10.3390/s23187672.

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We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stabilit

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Putra, Agfianto Eko, Oskar Natan, and Jazi Eko Istiyanto. "Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques." IIUM Engineering Journal 26, no. 1 (2025): 240–53. https://doi.org/10.31436/iiumej.v26i1.3328.

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Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/O

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Ranganadh, Narayanam. "NOVEL QUAD PARALLELIZED ARCHITECTURE FOR DIGITAL IMAGE PROCESSING CONVOLUTION ON FPGAs." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 9, no. 4 (2020): 162–67. https://doi.org/10.5281/zenodo.3778567.

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The Digital Image Processing convolution is core block for Convolution Neural Networks (CNN) which is used in Deep CNNs and is used for advanced applications of feature extraction, image recognition etc. This paper introduces 2 novel hardware architectures for convolution process one of them is hardware Quad parallelized architecture. Performance comparison is done and I proved that parallelization is highly useful. This parallel one can speed up the process of convolution filtered image data transmission through telemedicine communication network etc. Implementation is done for 64 by 64 size

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Gupta, Ramji, Alpana Pandey, and R. K.Baghel. "Efficient design of chaos based 4 bit true random number generator on FPGA." International Journal of Engineering & Technology 7, no. 3 (2018): 1783. http://dx.doi.org/10.14419/ijet.v7i3.16586.

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True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified

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Yuniati, Yetti. "I Implementasi Sistem Hermitian Generalized LED Index Modulation (H-GLIM-OFDM) pada Board FPGA Xilinx Arty Artix-7." Electrician 14, no. 3 (2020): 100–111. http://dx.doi.org/10.23960/elc.v14n3.2153.

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Abstrak— Komunikasi nirkabel menjadi jenis komunikasi yang digunakan secara luas, spektrum radio yang umumnya digunakan dalam komunikasi nirkabel menjadi tidak cukup untuk memenuhi tuntutan yang tinggi. Visible Light Communication (VLC) menjadi solusi untuk mengatasi kapasitas bandwidth yang kurang memadai ini. Orthogonal Frequency Division Multiplexing (OFDM) menjadi teknik yang dikembangkan untuk sistem komunikasi cahaya tampak karena pada teknik OFDM frekuensi yang digunakan saling orthogonal dan memungkinkan overlap antar frekuensi tanpa menimbulkan interferensi satu sama lain sehingga men

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Alharbi, Adel R., Hassan Tariq, Amer Aljaedi, and Abdullah Aljuhni. "Latency-Aware Accelerator of SIMECK Lightweight Block Cipher." Applied Sciences 13, no. 1 (2022): 161. http://dx.doi.org/10.3390/app13010161.

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This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on a field-programmable-gate-array (FPGA) platform with a block and key lengths of 32 and 64 bits. The critical features of our architecture include parallelism, pipelining, and a dedicated controller. Parallelism splits the digits of the key and data blocks into smaller segments. Then, we use each segmented key and data block in parallel for encryption and decryption computations. Splitting key and data blocks helps reduce the required clock cycles. A two-stage pipelining is used to shorten the cri

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Wu, Chenjie, Ying Tang, and Yi Wei. "A design of high-Speed SMS4 cipher circuit." Journal of Physics: Conference Series 2187, no. 1 (2022): 012013. http://dx.doi.org/10.1088/1742-6596/2187/1/012013.

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Abstract SMS4 cipher algorithm is a commercial cipher independently developed by china. This paper proposes a circuit design of high-speed SMS4 cipher algorithm, which adopts two-dimensional expansion and key path optimization technology. The round key generation module runs synchronously with the encryption module, and the running round is constant, which can effectively resist the side channel attack. Using Xilinx artix-7 for synthesis, the results show that the design function is correct, and achieves the balance of computing speed and resource occupation.

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Chen, Riguang, Ping Chen, Kuinian Li, and Hulin Liu. "Heterogeneous Tapped Delay-Line Time-to-Digital Converter on Artix-7 FPGA." Sensors 25, no. 9 (2025): 2923. https://doi.org/10.3390/s25092923.

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Time-to-Digital Converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) have become increasingly prevalent across a wide range of scientific and engineering disciplines, such as high-energy physics experiments, autonomous driving, robotic navigation, and medical imaging, owing to their cost-effectiveness, high precision, and rapid development cycles. This article presents a 3-tap heterogeneous tapped delay-line (TDL) architecture for a FPGA-based TDC that can be employed for multi-channel time-of-flight measurement. The TDC desgin is based on the open-source jTDC, featuring sin

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Dheeb, Khadija Omran, and Bayan Sabbar. "DIFFERENT FPGA PRODUCTS BASED IMPLEMENTATION OF LTE TURBO CODE." Iraqi Journal of Information & Communications Technology 3, no. 1 (2020): 40–51. http://dx.doi.org/10.31987/ijict.3.1.65.

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Abstract —In the long-term evolution (LTE) physical layer, using turbo code is considered as the paramount one in error-correcting coding. This paper presents an implementation of LTE turbo decoding using the Log- Maximum a posteriori (MAP) algorithm with reduced number of required cycles approximately by 75% based on serial to parallel operation. Also an improvement for this algorithm based on polynomial regression function to reduce the implementation complexity. All this system implementation design with 40 bit block size of the input using Xilinx System Generator (XSG). This system impleme

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Ranganadh, Narayanam*1 &. SSSP Rao2. "IMPLEMENTATION OF A HIGHLY EFFICIENT NOVEL FREQUENCY DOMAIN SNR HARDWARE USING XILINX FPGAs." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 12 (2017): 413–26. https://doi.org/10.5281/zenodo.1116789.

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Now a days at the receiving end in the applications of Cognitive Radio, Tele medicine, wireless networking, and in receiving system of multiple channels Electro Encephalo Gram (EEG) collected data, Wireless Brain Machine Interfacing Radio Frequency (RF) wireless data receiver system, and in RF Radar communication systems receiver’s noise performance is very critical. For noise performance Signal to Noise Ratio (SNR) is a Key parameter. SNR has to be calculated right after the receiving of the data, or at the intermediary stages of the Digital Signal Processing of the system. In many of s

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Dissertations / Theses on the topic "Xilinx ARTIX 7"

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Жданова, Ю. В., та І. В. Свид. "Огляд сьомої серії FPGA компанії Xilinx". Thesis, Кременчуцький льотний коледж, 2019. http://openarchive.nure.ua/handle/document/9371.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://doi.org/10.35598/mcfpga.2019.008.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-008.

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Book chapters on the topic "Xilinx ARTIX 7"

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Galimberti, Andrea. "FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM." In Special Topics in Information Technology. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-51500-2_3.

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AbstractPost-quantum cryptography aims to design cryptosystems that can be deployed on traditional computers and resist attacks from quantum computers, which are widely expected to break the currently deployed public-key cryptography solutions in the upcoming decades. Providing effective hardware support is crucial to ensuring a wide adoption of post-quantum cryptography solutions, and it is one of the requirements set by the USA’s National Institute of Standards and Technology within its ongoing standardization process. This research delivers a configurable FPGA-based hardware architecture to

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Liu, Bingkun, Dashuai Wang, and Jianhua Liu. "Image Acquisition and Storage System of Binocular Camera Based on FPGA." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2023. http://dx.doi.org/10.3233/faia230859.

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In order to better solve the problem that image processing technology is strict in real-time and stability, a binocular camera image acquisition and storage system based on FPGA is designed with the advantage of FPGA parallel processing. The system uses Xilinx ARTIX-7 XC7A35T as the master chip to control the CMOS camera as the image sensor for image acquisition, stores the acquired images in DDR3 SDRAM, and displays the images in the host computer by reading the memory data. The results show that the system has good real-time performance and stability, and meets the requirements of image tran

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Sheik Althaf, M., K. P. Ray, Nethravathi K A, Bhishm Tripathi, and Ashish K. Adiga. "Computational Challenges in Firmware Implementation of Beamforming Techniques and Enhancement." In Advances in Transdisciplinary Engineering. IOS Press, 2022. http://dx.doi.org/10.3233/atde220729.

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Adaptive beamforming has been studied extensively from a simulation point of view. While existing works compare various techniques based on their simulation output performance, their emulation on hardware systems and the prerequisite analysis of firmware viability remain relatively unexplored. The work presented in this paper addresses two issues. One is the firmware implementation of adaptive beamforming and the analysis of the Hardware Description Language implementation of the Least Mean Squares (LMS) Algorithm. It begins with the development of the algorithm on MATLAB Simulation Environmen

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Conference papers on the topic "Xilinx ARTIX 7"

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Damanik, Yulihade D., Ronaldo I. P. Siregar, Sella V. Simangunsong, and Good Fried Panggabean. "Implementation of Ground-Based SAR Echo Generator on Xilinx Artix-7 FPGA." In 2023 29th International Conference on Telecommunications (ICT). IEEE, 2023. http://dx.doi.org/10.1109/ict60153.2023.10374049.

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Samijayani, Octarina Nur, Dessy Indah Savitri, Dwi Astharini, Korry Azrina, Suci Rahmatia, and Rahmayati Alindra. "Implementation of Visible Light Communication using PAM on Xilinx Artix 7 35T FPGA." In 2018 IEEE 5th International Conference on Engineering Technologies and Applied Sciences (ICETAS). IEEE, 2018. http://dx.doi.org/10.1109/icetas.2018.8629156.

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Lin, Chi-En, Hao-Ren Chen, and Paul C. P. Chao. "Predicting Luminance Decay of a Micro-LED Display via Machine Learning on Temperature Distribution and LED Degradation With Implementation by FPGA." In ASME 2023 32nd Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2023. http://dx.doi.org/10.1115/isps2023-110557.

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Abstract A new method for predicting the luminance decay of Micro Light Emitting Diode (Micro-LED) displays by machine learning models is proposed herein with experiments of temperature distribution and degradation established. Although Micro-LEDs can be used as a direct light source for large outdoor advertising billboards, harsh outdoor conditions may lead to the degradation of Micro-LED displays. As a result, a temperature model is first built to predict the temperature distribution for the surface of a Micro-LED display based on illuminated patterns and the temperature sensors installed on

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Sun, Yi, Pao-Ying Cheng, and Paul C. P. Chao. "A Low-Area Hardware Realization of 2-Shares Threshold Implementation AES for IoT Biosensor Device." In ASME 2023 32nd Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2023. http://dx.doi.org/10.1115/isps2023-110546.

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Abstract A novel 2-shares Threshold Implementation Advanced Encryption Standard (TI-AES) is proposed to secure sensitive data collected by portable Biosensor Devices. These devices transmit data such as blood pressure, blood oxygen, and heartbeat directly to the Internet of Things. To protect personal information, symmetric encryption is used. However, the lightweight symmetric encryption used by IoT edge devices to enhance transmission efficiency and reduce device size makes them vulnerable to side-channel analysis (SCA), which poses a potential threat to data security. Our proposal incorpora

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