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Journal articles on the topic 'Xilinx ARTIX 7'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Alshehry, Awwad H., Saleh M. Alshahry, Abdullah K. Alhazmi, and Vamsy P. Chodavarapu. "A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters." Sensors 23, no. 18 (2023): 7672. http://dx.doi.org/10.3390/s23187672.

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We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stabilit

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Putra, Agfianto Eko, Oskar Natan, and Jazi Eko Istiyanto. "Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques." IIUM Engineering Journal 26, no. 1 (2025): 240–53. https://doi.org/10.31436/iiumej.v26i1.3328.

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Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/O

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Ranganadh, Narayanam. "NOVEL QUAD PARALLELIZED ARCHITECTURE FOR DIGITAL IMAGE PROCESSING CONVOLUTION ON FPGAs." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 9, no. 4 (2020): 162–67. https://doi.org/10.5281/zenodo.3778567.

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The Digital Image Processing convolution is core block for Convolution Neural Networks (CNN) which is used in Deep CNNs and is used for advanced applications of feature extraction, image recognition etc. This paper introduces 2 novel hardware architectures for convolution process one of them is hardware Quad parallelized architecture. Performance comparison is done and I proved that parallelization is highly useful. This parallel one can speed up the process of convolution filtered image data transmission through telemedicine communication network etc. Implementation is done for 64 by 64 size

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Gupta, Ramji, Alpana Pandey, and R. K.Baghel. "Efficient design of chaos based 4 bit true random number generator on FPGA." International Journal of Engineering & Technology 7, no. 3 (2018): 1783. http://dx.doi.org/10.14419/ijet.v7i3.16586.

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True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified

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Yuniati, Yetti. "I Implementasi Sistem Hermitian Generalized LED Index Modulation (H-GLIM-OFDM) pada Board FPGA Xilinx Arty Artix-7." Electrician 14, no. 3 (2020): 100–111. http://dx.doi.org/10.23960/elc.v14n3.2153.

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Abstrak— Komunikasi nirkabel menjadi jenis komunikasi yang digunakan secara luas, spektrum radio yang umumnya digunakan dalam komunikasi nirkabel menjadi tidak cukup untuk memenuhi tuntutan yang tinggi. Visible Light Communication (VLC) menjadi solusi untuk mengatasi kapasitas bandwidth yang kurang memadai ini. Orthogonal Frequency Division Multiplexing (OFDM) menjadi teknik yang dikembangkan untuk sistem komunikasi cahaya tampak karena pada teknik OFDM frekuensi yang digunakan saling orthogonal dan memungkinkan overlap antar frekuensi tanpa menimbulkan interferensi satu sama lain sehingga men

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Alharbi, Adel R., Hassan Tariq, Amer Aljaedi, and Abdullah Aljuhni. "Latency-Aware Accelerator of SIMECK Lightweight Block Cipher." Applied Sciences 13, no. 1 (2022): 161. http://dx.doi.org/10.3390/app13010161.

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This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on a field-programmable-gate-array (FPGA) platform with a block and key lengths of 32 and 64 bits. The critical features of our architecture include parallelism, pipelining, and a dedicated controller. Parallelism splits the digits of the key and data blocks into smaller segments. Then, we use each segmented key and data block in parallel for encryption and decryption computations. Splitting key and data blocks helps reduce the required clock cycles. A two-stage pipelining is used to shorten the cri

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Wu, Chenjie, Ying Tang, and Yi Wei. "A design of high-Speed SMS4 cipher circuit." Journal of Physics: Conference Series 2187, no. 1 (2022): 012013. http://dx.doi.org/10.1088/1742-6596/2187/1/012013.

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Abstract SMS4 cipher algorithm is a commercial cipher independently developed by china. This paper proposes a circuit design of high-speed SMS4 cipher algorithm, which adopts two-dimensional expansion and key path optimization technology. The round key generation module runs synchronously with the encryption module, and the running round is constant, which can effectively resist the side channel attack. Using Xilinx artix-7 for synthesis, the results show that the design function is correct, and achieves the balance of computing speed and resource occupation.

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8

Chen, Riguang, Ping Chen, Kuinian Li, and Hulin Liu. "Heterogeneous Tapped Delay-Line Time-to-Digital Converter on Artix-7 FPGA." Sensors 25, no. 9 (2025): 2923. https://doi.org/10.3390/s25092923.

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Time-to-Digital Converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) have become increasingly prevalent across a wide range of scientific and engineering disciplines, such as high-energy physics experiments, autonomous driving, robotic navigation, and medical imaging, owing to their cost-effectiveness, high precision, and rapid development cycles. This article presents a 3-tap heterogeneous tapped delay-line (TDL) architecture for a FPGA-based TDC that can be employed for multi-channel time-of-flight measurement. The TDC desgin is based on the open-source jTDC, featuring sin

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Dheeb, Khadija Omran, and Bayan Sabbar. "DIFFERENT FPGA PRODUCTS BASED IMPLEMENTATION OF LTE TURBO CODE." Iraqi Journal of Information & Communications Technology 3, no. 1 (2020): 40–51. http://dx.doi.org/10.31987/ijict.3.1.65.

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Abstract —In the long-term evolution (LTE) physical layer, using turbo code is considered as the paramount one in error-correcting coding. This paper presents an implementation of LTE turbo decoding using the Log- Maximum a posteriori (MAP) algorithm with reduced number of required cycles approximately by 75% based on serial to parallel operation. Also an improvement for this algorithm based on polynomial regression function to reduce the implementation complexity. All this system implementation design with 40 bit block size of the input using Xilinx System Generator (XSG). This system impleme

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Ranganadh, Narayanam*1 &. SSSP Rao2. "IMPLEMENTATION OF A HIGHLY EFFICIENT NOVEL FREQUENCY DOMAIN SNR HARDWARE USING XILINX FPGAs." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 12 (2017): 413–26. https://doi.org/10.5281/zenodo.1116789.

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Now a days at the receiving end in the applications of Cognitive Radio, Tele medicine, wireless networking, and in receiving system of multiple channels Electro Encephalo Gram (EEG) collected data, Wireless Brain Machine Interfacing Radio Frequency (RF) wireless data receiver system, and in RF Radar communication systems receiver’s noise performance is very critical. For noise performance Signal to Noise Ratio (SNR) is a Key parameter. SNR has to be calculated right after the receiving of the data, or at the intermediary stages of the Digital Signal Processing of the system. In many of s

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Wojciechowski, Andrzej A., Krzysztof Marcinek, and Witold A. Pleskacz. "Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA." Electronics 12, no. 20 (2023): 4297. http://dx.doi.org/10.3390/electronics12204297.

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Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multipl

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Mohamed, Hasan Abdel Aziz, and Mohamed A. Yakout. "An Efficient AES Design and Implementation Using FPGA." International Journal of Emerging Science and Engineering 13, no. 3 (2025): 21–26. https://doi.org/10.35940/ijese.e9506.13030225.

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The more technology develops, the greater the amount of digital information. This requires that information be secure and free from hacking, so we use encryption algorithms. One of the most famous is the Advanced Encryption Standard (AES). This paper deals with the hardware implementation of the AES Rijndael Encryption Algorithm using Xilinx Virtex-6 & Artix-7 FPGA. The work aims for a balanced design between speed, area, and power. The S-Box hardware design is based on pre-calculated look-up tables (LUTs). This method is characterized by less time and less architectural complexity. The mi

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Hasan, Abdel Aziz Mohamed. "An Efficient AES Design and Implementation Using FPGA." International Journal of Emerging Science and Engineering (IJESE) 13, no. 3 (2025): 21–26. https://doi.org/10.35940/ijese.E9506.13030225.

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<strong>Abstract: </strong>The more technology develops, the greater the amount of digital information. This requires that information be secure and free from hacking, so we use encryption algorithms. One of the most famous is the Advanced Encryption Standard (AES). This paper deals with the hardware implementation of the AES Rijndael Encryption Algorithm using Xilinx Virtex-6 & Artix-7 FPGA. The work aims for a balanced design between speed, area, and power. The S-Box hardware design is based on pre-calculated look-up tables (LUTs). This method is characterized by less time and less archi

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Huang, Zhengwu, Sizhe Chen, Pengyue Sun, Ding Deng, and Guangfu Sun. "An Efficient and Low-Cost Design of Modular Reduction for CRYSTALS-Kyber." Electronics 14, no. 11 (2025): 2309. https://doi.org/10.3390/electronics14112309.

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After being selected as a standard for Post-Quantum Cryptography Key Encapsulation Mechanisms by NIST, CRYSTALS-Kyber has driven the transformation of the information security field toward new standards. In CRYSTALS-Kyber, modular reduction is crucial for performance optimization. This paper proposes a bitwise modular reduction design based on Dadda tree compression arrays, achieving higher parallelism through a strategy that combines bitwise modular reduction with hybrid compression arrays. As our experiments show, it only costs 91 LUTs when implemented on Xilinx Artix-7 FPGA. Compared with t

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Aviña-Zuñiga, Mario Salvador, Miguel Angel Estudillo-Valdez, Gilberto Enrico Vazquez-Alcaraz, Andrés Calvillo-Téllez, and Jose Cruz Nuñez-Perez. "Emulación en FPGA de un sistema transceptor de RF basado en radio definida por software." Pädi Boletín Científico de Ciencias Básicas e Ingenierías del ICBI 10, Especial4 (2022): 181–89. http://dx.doi.org/10.29057/icbi.v10iespecial4.9141.

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La Radio Definida por Software SDR utiliza técnicas digitales para reemplazar el hardware de radio tradicional como mezcladores, moduladores, demoduladores y circuitos analógicos relacionados, el resultado es una radio flexible que puede ser rápidamente reconfigurada. En este artículo se desarrolla y emula un sistema de radiocomunicaciones completo, es decir el transmisor-receptor, usando SDR. Para lograr lo anterior se usa la técnica de DSSS y el System Generator for DSP de Xilinx en Matlab-Simulink. Se compila el modelo y se obtiene el código VHDL para emularlo en una tarjeta de FPGA Artix-7

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Cintra, R. J., Paulo Martinez, André Leite, et al. "Gaussian Kernel Approximations Require Only Bit-Shifts." Information 15, no. 10 (2024): 618. http://dx.doi.org/10.3390/info15100618.

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An approach to approximate the 2D Gaussian filter for all possible kernel sizes based on the binary optimization technique is introduced. The approximate filter coefficients are designed as negative powers of two, allowing hardware implementation with remarkable savings in the chip area. The proposed approximate filters were evaluated and compared with competing methods using both similarity analysis and edge detection applications. The proposed method and the competing works for masks of size 3×3, 5×5, and 7×7 were implemented in a Xilinx Artix-7 FPGA. The proposed method showed up to a 60.0%

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Parrilla, Luis, Antonio García, Encarnación Castillo, Juan Antonio López-Villanueva, and Uwe Meyer-Baese. "Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications." Cryptography 7, no. 2 (2023): 26. http://dx.doi.org/10.3390/cryptography7020026.

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The generation of random numbers is crucial for practical implementations of cryptographic algorithms. In this sense, hardware security modules (HSMs) include true random number generators (TRNGs) implemented in hardware to achieve good random number generation. In the case of cryptographic algorithms implemented on FPGAs, the hardware implementation of RNGs is limited to the programmable cells in the device. Among the different proposals to obtain sources of entropy and process them to implement TRNGs, those based in ring oscillators (ROs), operating in parallel and combined with XOR gates, p

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Asha Devi, Dharmavaram, Chintala Sandeep, and Sai Sugun L. "Design of Power Efficient 32-Bit Processing Unit." International Journal of Engineering & Technology 7, no. 2.16 (2018): 52. http://dx.doi.org/10.14419/ijet.v7i2.16.11415.

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The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit. The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these

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Olaru, A. I., and G. Predusca. "Application Development on the Nexys 4 DDR Platform: Techniques And Implementations." Scientific Bulletin of Electrical Engineering Faculty 25, no. 1 (2025): 1–8. https://doi.org/10.2478/sbeef-2025-0001.

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Abstract The article explores the application of digital circuits, such as logic gates, logic functions, flip-flop, and automata, using the Nexys 4 DDR platform from Xilinx and the Vivado software. The Nexys 4 DDR, featuring the Artix-7 FPGA, provides a robust environment for designing and testing digital systems. It allows for efficient implementation of various digital functions through hardware programming and simulation. The use of Vivado software eases the creation, simulation, and deployment of custom digital circuits, highlighting the versatility and power of FPGA technology in real-wor

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Sanket, Dessai, and G. Sandeep. "Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator." International Journal of Reconfigurable and Embedded Systems 7, no. 1 (2018): 21–33. https://doi.org/10.11591/ijres.v7.i1.pp21-33.

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This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to  a USB controller with DDR mem

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Pandey, Bishwajeet, Geetam S. Tomar, Rajina R. Mohamed, D. M. Akbar Hussain, and Amit Kant Pandit. "Energy Efficient Design on 16 nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate." Journal of Computational and Theoretical Nanoscience 17, no. 11 (2020): 5122–24. http://dx.doi.org/10.1166/jctn.2020.9351.

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Scientists in 2010 were using a 40 nanometer Process based FPGA called Virtex-6 and 45 nm Process Technology based FPGA called Spartan-6. After 2010, researchers shifted their focus towards 28 nm technology based 7 series FPGA (Artix-7, Kintex-7, and Virtex-7) due to their intrinsic capability of low power consumption than both 40 nm and 45 nm technology based FPGA. In December, 2013, Xilinx introduced the 20 nm process technology based UltraScale series: Virtex UltraScale and Kintex UltraScale families. But now in 2020, researchers are using 16 nm technology based UltraScale+ FPGA. In our wor

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Guerrero Ramírez, Esteban Osvaldo, Alberto Martínez Barbosa, Enrique Guzmán Ramírez, Jesús Linares Flores, and Hebertt Sira Ramírez. "Control del Convertidor CD/CD Reductor–Paralelo Implementado en FPGA." Revista Iberoamericana de Automática e Informática industrial 15, no. 3 (2018): 309. http://dx.doi.org/10.4995/riai.2018.8925.

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El presente artículo documenta el diseño e implementación de un controlador robusto para el convertidor CD/CD Reductor–Paralelo, bajo la perspectiva de la planitud diferencial y la técnica del control por rechazo activo de perturbaciones basado en un observador GPI. Los objetivos principales del controlador propuesto son: regular la tensión de salida y equilibrar las corrientes de los convertidores en paralelo. Para el modelado de la arquitectura hardware de este controlador se utiliza una herramienta con alto nivel de abstracción de hardware y se implementa en un FPGA Artix–7 de la compañía X

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Vaidyanathan, Sundarapandian, Aceng Sambas, Esteban Tlelo-Cuautle, Ciro Fabian Bermudez-Marquez, Khaled Benkouider, and Samy Abdelwahab Safaan. "A New Hyperchaotic Two-Scroll System: Bifurcation Study, Multistability, Circuit Simulation, and FPGA Realization." Discrete Dynamics in Nature and Society 2022 (September 22, 2022): 1–17. http://dx.doi.org/10.1155/2022/6604684.

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With the swift advancement of chaos theory, the modeling, chaotic oscillations, and engineering applications of chaotic and hyperchaotic systems are important topics in research. In this research paper, we elucidate our findings of a new four-dimensional two-scroll hyperchaotic system having only two quadratic nonlinearities and carry out a detailed bifurcation study of the proposed dynamical model. Also, an electronic circuit has been constructed for the new system using MultiSim (Version 14). The implementation of the new 4-D hyperchaotic system in a field-programmable gate array (FPGA) is p

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Sahin, Suhap, and Mehmet Ali Cavuslu. "FPGA Implementation of Wavelet Neural Network Training with PSO/iPSO." Journal of Circuits, Systems and Computers 27, no. 06 (2018): 1850098. http://dx.doi.org/10.1142/s0218126618500986.

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In this study, field-programmable gate array (FPGA)-based hardware implementation of the wavelet neural network (WNN) training using particle swarm optimization (PSO) and improved particle swarm optimization (iPSO) algorithms are presented. The WNN architecture and wavelet activation function approach that is proper for the hardware implementation are suggested in the study. Using the suggested architecture and training algorithms, test operations are implemented on two different dynamic system recognition problems. From the test results obtained, it is observed that WNN architecture generaliz

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sundhar, shyam. "Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures." International Scientific Journal of Engineering and Management 03, no. 04 (2024): 1–9. http://dx.doi.org/10.55041/isjem01526.

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The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulatio

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Bibilo, P. N., Yu Yu Lankevich, and V. I. Romanov. "Logical minimization for combinatorial structure in FPGA." Informatics 18, no. 1 (2021): 7–24. http://dx.doi.org/10.37661/1816-0301-2021-18-1-7-24.

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The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological

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Afolabi, Opeyemi-Micheal, Vincent-Ademola Adeyemi, Esteban Tlelo-Cuautle, and Jose-Cruz Nuñez-Perez. "FPGA Realization of a Fractional-Order Model of Universal Memory Elements." Fractal and Fractional 8, no. 10 (2024): 605. http://dx.doi.org/10.3390/fractalfract8100605.

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This paper addresses critical gaps in the digital implementations of fractional-order memelement emulators, particularly given the challenges associated with the development of solid-state devices using nanomaterials. Despite the potentials of these devices for industrial applications, the digital implementation of fractional-order models has received limited attention. This research contributes to bridging this knowledge gap by presenting the FPGA realization of the memelements based on a universal voltage-controlled circuit topology. The digital emulators successfully exhibit the pinched hys

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Choi, Soyeon, and Hoyoung Yoo. "Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado." Electronics 13, no. 6 (2024): 1100. http://dx.doi.org/10.3390/electronics13061100.

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SRAM-based FPGA(Field Programmable Logic Arrays) requires external memory since its internal memory gets erased when power is cut off. The process of transmitting the circuit netlist in bitstream from external memory during power-up in FPGA is vulnerable to malicious attacks such as bitstream theft and tampering. Previous FPGA reverse-engineering methods focus on FPGAs, supported by ISE (ISE Design Suite). This is because ISE provides XDLRC (Xilinx Design Language Routing Configurable logic) and XDL (Xilinx Design language) files, which are essential for reverse engineering. However, Vivado De

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Mispan, Mohd Syafiq, Mohammad Haziq Ishak, Aiman Zakwan Jidin, and Nasir Haslinah Mohd. "FPGA implementation of artificial neural network for PUF modeling." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 200–207. https://doi.org/10.11591/ijres.v14.i1.pp200-207.

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Field-programmable gate array (FPGA) is a prominent device in developing the internet of things (IoT) application since it offers parallel computation, power efficiency, and scalability. The identification and authentication of these FPGAbased IoT applications are crucial to secure the user-sensitive data transmitted over IoT networks. Physical unclonable function (PUF) technology provides a great capability to be used as device identification and authentication for FPGAbased IoT applications. Nevertheless, conventional PUF-based authentication suffers a huge overhead in storing the challenge-

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Serrano, Ronaldo, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, and Cong-Kha Pham. "A Unified PUF and Crypto Core Exploiting the Metastability in Latches." Future Internet 14, no. 10 (2022): 298. http://dx.doi.org/10.3390/fi14100298.

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Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations. In addition, a hardware implementation can provide the possibility of unifying the functionality with some secure primitive, for example, a true random number generator (TRNG) or a physical unclonable function (PUF). This paper presents a unified PUF-ChaCha20 in a field-programmable gate-array (FPGA) implementation. The problems and solutions of the PUF implementation are described, exploiting the metastability i

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Srinivasulu, P., and Kumar Dharmireddy Ajay. "Chirp scaling algorithm for enhanced SAR data processing using FPGA." i-manager's Journal on Communication Engineering and Systems 14, no. 1 (2025): 1. https://doi.org/10.26634/jcs.14.1.21606.

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Synthetic aperture radar (SAR) imaging is known for its high computational demands, which complicates its use in real- time applications. This paper introduces the chirp-scaling algorithm (CSA) tailored for real-time SAR applications, leveraging advanced field programmable gate array (FPGA) processors. The algorithm employs range Doppler techniques to compress a generated chirp signal, with MATLAB used for validation purposes. To facilitate the computationally demanding tasks like Fast Fourier Transform (FFT) and complex data multiplication, hardware acceleration is essential. Xilinx Vivado is

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Nguyen, Phu, Hung Nguyen, Kim Anh Phan Vo, and Linh Tran. "Towards High-Performance FPGA Implementation of ECDSA for Koblitz Curve: An Instruction-Set Approach." Engineering, Technology & Applied Science Research 15, no. 3 (2025): 23546–52. https://doi.org/10.48084/etasr.11040.

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This paper presents a novel instruction-set-based hardware implementation of the Elliptic Curve Digital Signature Algorithm (ECDSA) for a 256-bit Koblitz curve on FPGA. The research contribution under consideration utilizes the integration of Koggle-Stone Adders (KSAs) into the modified structure of modular multiplication and inversion units, thereby enabling high-speed performance in modular computation architecture. Furthermore, by employing an instruction-set-based approach for the control unit instead of the conventional finite state machine for the implementations of ECDSA and point multi

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Nguyen, Toan, Hoang Anh Pham, Hung Nguyen, Trang Hoang, and Linh Tran. "Efficient number theoretic transform accelerator for CRYSTALS-Kyber." Indonesian Journal of Electrical Engineering and Computer Science 33, no. 2 (2024): 795–803. https://doi.org/10.11591/ijeecs.v33.i2.pp795-803.

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The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT (INTT) b

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Della Sala, Riccardo, and Giuseppe Scotti. "A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability." Cryptography 7, no. 2 (2023): 18. http://dx.doi.org/10.3390/cryptography7020018.

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In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply vol

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Nguyen, Toan, Hoang Anh Pham, Hung Nguyen, Trang Hoang, and Linh Tran. "Efficient number theoretic transform accelerator for CRYSTALS-Kyber." Indonesian Journal of Electrical Engineering and Computer Science 33, no. 2 (2024): 795. http://dx.doi.org/10.11591/ijeecs.v33.i2.pp795-803.

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<p>The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT

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Nuñez-Perez, Jose Cruz, Vincent Ademola Adeyemi, Yuma Sandoval-Ibarra, F. Javier Pérez-Pinal, and Esteban Tlelo-Cuautle. "FPGA Realization of Spherical Chaotic System with Application in Image Transmission." Mathematical Problems in Engineering 2021 (April 13, 2021): 1–16. http://dx.doi.org/10.1155/2021/5532106.

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This paper considers a three-dimensional nonlinear dynamical system capable of generating spherical attractors. The main activity is the realization of a spherical chaotic attractor on Intel and Xilinx FPGA boards, with a focus on implementation of a secure communication system. The first major contribution is the successful synchronization of two chaotic spherical systems, in VHDL program, in a master-slave topology using Hamiltonian forms. The synchronization errors show that the two spherical chaotic systems synchronize in a very short time after which the error signals become zero. The sec

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Mispan, Mohd Syafiq, Mohammad Haziq Ishak, Aiman Zakwan Jidin, and Haslinah Mohd Nasir. "FPGA implementation of artificial neural network for PUF modeling." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 200. https://doi.org/10.11591/ijres.v14.i1.pp200-207.

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<p>Field-programmable gate array (FPGA) is a prominent device in developing the internet of things (IoT) application since it offers parallel computation, power efficiency, and scalability. The identification and authentication of these FPGAbased IoT applications are crucial to secure the user-sensitive data transmitted over IoT networks. Physical unclonable function (PUF) technology provides a great capability to be used as device identification and authentication for FPGAbased IoT applications. Nevertheless, conventional PUF-based authentication suffers a huge overhead in storing the c

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Baraskar, Savita. "Power System Harmonics Estimation by the SWPT-Based Digital Design Implemented on FPGA Platform." Advanced Engineering Forum 54 (January 20, 2025): 147–59. https://doi.org/10.4028/p-57cydq.

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The quick and accurate estimation of time-varying harmonics is crucial for online monitoring, analysis, and control of the electrical power system. This research paper presents a stationary wavelet packet transform (SWPT) based digital design implemented on the FPGA platform for efficient and fast amplitude estimation of the power system harmonics. The time-invariant property of the SWPT technique plays a crucial role in ensuring the accurate amplitude estimation of harmonic components. The efficiency and accuracy of the proposed SWPT-based digital design have been assessed with synthetic and

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Garzetti, Fabio, Nicola Lusardi, Nicola Corna, et al. "High-Precision Digital-to-Time Converter with High Dynamic Range for 28 nm 7-Series Xilinx FPGA and SoC Devices." Electronics 13, no. 23 (2024): 4825. https://doi.org/10.3390/electronics13234825.

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Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise. Skew compensation and camera shutter operation represent just a few examples of such applications. The advantages of adopting a flexible and rapid time-to-market strategy focused on fast prototyping using programmable logic devices—such as field-programmable gate arrays (FPGAs) and system-on-chip (SoC)—have become increasingly evident. These benefits outweigh those of

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Kumar, A. Hemanth. "Design and Implementation of a 3-bit ALU with Integrated 7-Segment Display on FPGA." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 11 (2024): 1–6. http://dx.doi.org/10.55041/ijsrem38905.

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This paper describes the design and implementation of a 3-bit Arithmetic Logic Unit (ALU) with integrated 7-segment display output, deployed on an FPGA platform. The objective of this project is to efficiently perform and display basic arithmetic and logic operations, including addition, subtraction, AND, OR, XOR, and NOT, with an FPGA-based ALU. A control signal selects the operation, and the ALU's 3-bit result is decoded and displayed on a 7-segment interface for clear output visualization. The ALU design is coded in Verilog and includes logic to manage carry and overflow in arithmetic funct

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Wang, Shikai, Haibo Yang, Yapeng Zhang, Xiaoqiang Zhou, Maogen Su, and Chengxin Zhao. "A cosmic ray muons telescope based on bar plastic scintillator detectors." Journal of Instrumentation 19, no. 11 (2024): C11004. http://dx.doi.org/10.1088/1748-0221/19/11/c11004.

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Abstract A cosmic ray muons telescope (CORMT) was designed to monitor the distribution of cosmic ray muons in the environment. CORMT is made of three main components: the mechanical structure, the detector, and the readout electronics. The mechanical structure consists of a support structure and a rotating moving platform that ensures the stability and accuracy of the test. The detector consists of four bar-shaped plastic scintillators each coupled with a silicon photomultiplier (SiPM). The readout electronics design uses Xilinx Artix 7 series field-programmable gate array (FPGA), combined wit

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Patil, Ankita Natujirao, Vaishali V. Ingale, Fatema A. Dalal, and Vanita Agarwal. "Implementation of Robust and Secure Watermarking Algorithm on FPGA using DCT." WSEAS TRANSACTIONS ON SIGNAL PROCESSING 20 (October 25, 2024): 54–59. http://dx.doi.org/10.37394/232014.2024.20.6.

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Digital watermarking deals with embedding digital content in a cover signal so that it becomes indiscernible to make it robust against different security threats. This work demonstrates the implementation of a robust and secure watermarking technique on a Field Programmable Gate Array (FPGA) using Discrete Cosine Transform (DCT). Block by block DCT of the cover image was computed and watermark pixels in each of the blocks were hidden using middle-frequency band coefficients. Security is ensured by encrypting the watermarkwith a secret key and Arnold transform. The resultant watermark image is

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Alshahry, Saleh M., Awwad H. Alshehry, Abdullah K. Alhazmi, and Vamsy P. Chodavarapu. "A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method." Sensors 23, no. 14 (2023): 6621. http://dx.doi.org/10.3390/s23146621.

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We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union ty

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Nguyen, Hung, Trang Hoang, and Linh Tran. "Efficient Hardware Implementation of Elliptic-Curve Diffie–Hellman Ephemeral on Curve25519." Electronics 12, no. 21 (2023): 4480. http://dx.doi.org/10.3390/electronics12214480.

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Hardware architecture optimized for implementing the elliptic-curve Diffie–Hellman ephemeral (ECDHE) on 256-bit Montgomery elliptic curves presents unique challenges, particularly for resource-constrained IoT and mobile devices. This work aims to provide an efficient hardware implementation of ECDHE on Curve25519, including a dedicated finite state machine (FSM) designed to handle point multiplication and ECDHE operations, utilizing constant-time algorithms and a unified memory block for resource management. Additionally, we introduce an optimized modular computation unit that covers modular a

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Waris, Ayesha, Arshad Aziz, and Bilal Muhammad Khan. "Area-time efficient pipelined number theoretic transform for CRYSTALS-Kyber." PLOS One 20, no. 5 (2025): e0323224. https://doi.org/10.1371/journal.pone.0323224.

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CRYSTALS-Kyber has been standardized by the National Institute of Standards and Technology (NIST) as a quantum-resistant algorithm in the post-quantum cryptography (PQC) competition. The bottleneck in performance of Kyber is the polynomial multiplication based on Number Theoretic transform (NTT). This work presents two parallel architectures adopting Multi-Path Delay Commutator (MDC) approach on target FPGA platform. Resource sharing technique is adopted to perform PWM operations using MDC NTT/INTT architecture. Moreover, we propose various optimizations at architectural level to minimize reso

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Megha, Hegde, and Sivakumar P.Agalya. "Development and Implementation of VLSI Reconfigurable Architecture for Gabor Filter in Medical Imaging Application." International Journal of Engineering and Management Research 8, no. 3 (2018): 71–76. https://doi.org/10.31033/ijemr.8.3.10.

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The Gabor filter is a very effective tool in visual search approaches and multimedia applications. This filter provides high resolution in time-frequency domains and thus finds use in object recognition, character recognition and pattern recognition applications. Medical Image analysis using image processing algorithms is one of the best ways of diagnosing diseases inside human body. The Gabor wavelets resemble the visual cortex cell operation of mammalian brains and hence are best suited for biological image analysis. A Tonsillitis detection system is proposed here using Gabor filtering appro

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Researcher. "DESIGN AND IMPLEMENTATION OF LOW POWER PIPELINED FFT ARCHITECTURE FOR DSP APPLICATION." International Journal of Advanced Research in Engineering and Technology (IJARET) 15, no. 4 (2024): 86–94. https://doi.org/10.5281/zenodo.13166453.

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The swift advancements in signal analysis applications have heightened the need for efficient, high-performance architectures to execute complex algorithms like the Quick Fourier Transform (FFT). This study introduces a VLSI implementation of a pipelined FFT architecture customized for DSP applications, addressing challenges in real-time processing, power consumption, and resource utilization. By exploiting the parallelism of the FFT algorithm and using pipelining techniques, our design achieves high throughput and low latency with minimal area overhead and power consumption. Implemented throu

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Tynymbayev, Sakhybay, Margulan Ibraimov, Timur Namazbayev, and Sergiy Gnatyuk. "Development of pipelined polynomial multiplier modulo irreducible polynomials for cryptosystems." Eastern-European Journal of Enterprise Technologies 1, no. 4 (115) (2022): 37–43. http://dx.doi.org/10.15587/1729-4061.2022.251913.

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In this paper, we consider a schematic solution of the pipeline multiplier modulo, where multiplication begins with the analysis of the lowest order of the polynomial multiplier, which can serve as an operating unit for high-speed encryption and decryption of data by hardware implementation of cryptosystems based on a non-positional polynomial notation. The functional diagram of the pipeline and the structure of its logical blocks, as well as an example of performing the operation of multiplying polynomials modulo, are given. The correct functioning of the developed circuit was checked by mode

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Sakhybay, Tynymbayev, Ibraimov Margulan, Namazbayev Timur, and Gnatyuk Sergiy. "Development of pipelined polynomial multiplier modulo irreducible polynomials for cryptosystems." Eastern-European Journal of Enterprise Technologies 1, no. 4 (115) (2022): 37–43. https://doi.org/10.15587/1729-4061.2022.251913.

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In this paper, we consider a schematic solution of the pipeline multiplier modulo, where multiplication begins with the analysis of the lowest order of the polynomial multiplier, which can serve as an operating unit for high-speed encryption and decryption of data by hardware implementation of cryptosystems based on a non-positional polynomial notation. The functional diagram of the pipeline and the structure of its logical blocks, as well as an example of performing the operation of multiplying polynomials modulo, are given. The correct functioning of the developed circuit was checked by mode

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Smith, Farouk, and Joshua Omolo. "Experimental verification of the effectiveness of a new circuit to mitigate single event upsets in a Xilinx Artix-7 field programmable gate array." Microprocessors and Microsystems 79 (November 2020): 103327. http://dx.doi.org/10.1016/j.micpro.2020.103327.

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