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Journal articles on the topic 'Xilinx.Floating Point Subtractor'

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Published: 3 June 2025

Last updated: 19 July 2025

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1

Ms., Anuja A. Bhat* &. Prof. Mangesh N. Thakare. "DESIGN OF FLOATING POINT MULTIPLIER BASED ON BOOTH ALGORITHM USING VHDL." INTERNATIONAL JOURNAL OF RESEARCH SCIENCE & MANAGEMENT 4, no. 5 (2017): 55–62. https://doi.org/10.5281/zenodo.572573.

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In this paper, we have presented of High Speed, low power and less delay 32-bit IEEE 754 Floating Point Subtractor and Multiplier using Booth Multiplier. Multiplication is an important fundamental function in many Digital Signal Processing (DSP) applications such as Fast Fourier Transform (FFT). Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. The main objective of this research is to reduce delay, power and to increase the speed. The coding is done in VHDL, synthesis and simulation has been done using Xilinx ISE simulator.

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Ms., Anuja A. Bhat* &. Prof. Rutuja Warbhe. "DESIGN OF FLOATING POINT MULTIPLIER BASED ON BOOTH ALGORITHM USING VHDL." INTERNATIONAL JOURNAL OF RESEARCH SCIENCE & MANAGEMENT 4, no. 5 (2017): 123–30. https://doi.org/10.5281/zenodo.580862.

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In this paper, high Speed, low power and less delay 32-bit IEEE 754 Floating PointSubtractor andMultiplierispresented using Booth Multiplier. Multiplication is an important fundamental function in many Digital Signal Processing (DSP) applications such as Fast Fourier Transform (FFT). Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. The main objective of this researchis to reduce delay, power and to increase the speed.The coding is done in VHDL, synthesis and simulationhas been done using Xilinx ISE simulator. The modules des

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Xiao, Feibao, Feng Liang, Bin Wu, Junzhe Liang, Shuting Cheng, and Guohe Zhang. "Posit Arithmetic Hardware Implementations with The Minimum Cost Divider and SquareRoot." Electronics 9, no. 10 (2020): 1622. http://dx.doi.org/10.3390/electronics9101622.

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As a substitute for the IEEE 754-2008 floating-point standard, Posit, a new kind of number system for floating-point numbers, was put forward recently. Hitherto, some studies have proven that Posit is a better floating-point style than IEEE 754-2008 in some fields. However, most of these studies presented the advantages of Posit from the arithmetical aspect, but none of them suggested it had a better hardware implementation than that of IEEE 754-2008. In this paper, we propose several hardware implementations that contain the Posit adder/subtractor, multiplier, divider, and square root. Our go

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Naginder, Singh, and Parihar Kapil. "Comparative study of single precision floating point division using different computational algorithms." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 3 (2023): 336–44. https://doi.org/10.11591/ijres.v12.i3pp336-344.

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This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed an

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Singh, Naginder, and Kapil Parihar. "Comparative study of single precision floating point division using different computational algorithms." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 3 (2023): 336. http://dx.doi.org/10.11591/ijres.v12.i3.pp336-344.

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<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computatio

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Teymourzadeh, Rozita. "On-chip Implementation of High Resolution High Speed Low Area Floating point Adder Subtractor for OFDM Applications." American Journal of Engineering and Applied Sciences ISSN: 1941-7020. 3, no. 1 (2010): 25–30. https://doi.org/10.5281/zenodo.1239895.

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Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high-resolution high-speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for Floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critica

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Bhagya, Prof, Ramanagowda G. S, Rohan S, Soundarya D. R, and Yogitha K. "Implementation of Pipelined Multi_Precision (1, 2 and 4) Floating-point Arithmetic Operations." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (2023): 3141–43. http://dx.doi.org/10.22214/ijraset.2023.50739.

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Abstract: The implementation of pipelined multi-precision-based arithmetic operations are carried out. In the existing system, the floating-point operation is based on single precision and is implemented on a divider. The proposed design has been implemented using single, double and quad precision using the universal piece-wise linear (PWL) approximation method and a modified Goldschmidt algorithm. The proposed design performs addition, subtraction, multiplication, and division using the universal PWL method to reduce maximum error. Small multipliers are used in the modified Goldschmidt algori

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Baesler, Malte, and Sven-Ole Voigt. "Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs." International Journal of Reconfigurable Computing 2013 (2013): 1–16. http://dx.doi.org/10.1155/2013/453173.

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Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the q

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ÖZKILBAÇ, Bahadır. "Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform." Brilliant Engineering 1, no. 1 (2019): 26–32. http://dx.doi.org/10.36937/ben.2020.001.005.

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FPGAs have capabilities such as low power consumption, multiple I/O pins, and parallel processing. Because of these capabilities, FPGAs are commonly used in numerous areas that require mathematical computing such as signal processing, artificial neural network design, image processing and filter applications. From the simplest to the most complex, all mathematical applications are based on multiplication, division, subtraction, addition. When calculating, it is often necessary to deal with numbers that are fractional, large or negative. In this study, the Arithmetic Logic Unit (ALU), which use

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Prahlada, P. Udupa, and B. Ramesh K. "VLSI Design and Verification of a Multi-Function Arithmetic Logic Unit." Journal of VLSI Design and its Advancement 7, no. 3 (2024): 37–47. https://doi.org/10.5281/zenodo.13709349.

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<em>Exploring an ALU Design in the VLSI Domain - Within modern processors like CPUs, FPUs, and GPUs, the Arithmetic Logic Unit (ALU) serves as a critical building block. In this review paper, we delve into the Very Large Scale Integration (VLSI) design of an ALU, exploring its functionality through meticulous simulation and testing. Leveraging the Xilinx ISE design suite 14.7, the study validates the proposed ALU's gate-level and chip-level implementation, ensuring its ability to execute nine essential operations: addition, subtraction, multiplication, shifting, comparison, AND, OR, NOT, and X

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Kavya, Nagireddy. "Design and Implementation of Floating-Point Addition and Floating-Point Multiplication." International Journal for Research in Applied Science and Engineering Technology 10, no. 1 (2022): 98–101. http://dx.doi.org/10.22214/ijraset.2022.39742.

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Abstract: In this paper, we present the design and implementation of Floating point addition and Floating point Multiplication. There are many multipliers in existence in which Floating point Multiplication and Floating point addition offers a high precision and more accuracy for the data representation of the image. This project is designed and simulated on Xilinx ISE 14.7 version software using verilog. Simulation results show area reduction and delay reduction as compared to the conventional method. Keywords: FIR Filter, Floating point Addition, Floating point Multiplication, Carry Look Ahe

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Singamsetti, Mrudula, Sadulla Shaik, and T. Pitchaiah. "Merged Floating Point Multipliers." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 178–82. http://dx.doi.org/10.35940/ijeat.a1042.1291s519.

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Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recogn

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Kashyap, Anirudh, Kusuma Keerthi, and Dr Shilpa D.R. "Boundary Scan Architecture for a Double Precision Floating Point Subtractor." Journal of University of Shanghai for Science and Technology 23, no. 06 (2021): 521–29. http://dx.doi.org/10.51201/jusst/21/05285.

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The boundary scan logic for testing was developed in order to make the process of testing easier for System-on-Chip (SoC) [1] architectures. The proposed work focuses on designing a boundary scan logic for a 64-bit floating-point subtractor unit. The TAP controller designed is capable of executing the three mandatory Joint Test Action Group (JTAG) instructions of the IEEE 1149 standard. The testing architecture has the potential to not only test the functionality of the core logic but also to test single stuck-at faults for all the inputs and outputs of the core logic. A provision for bypassin

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Albert, Anitha Juliette, and Seshasayanan Ramachandran. "NULL Convention Floating Point Multiplier." Scientific World Journal 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/749569.

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Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power cons

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B. VENKATA VINOD, KUMAR, and BASHA SK. MAHABOOB. "Design and Simulation of Single-Precision Inexact Floating-Point Adder/Subtractor." i-manager’s Journal on Electronics Engineering 6, no. 4 (2016): 7. http://dx.doi.org/10.26634/jele.6.4.8087.

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Miss., Supriya Sunil Phalle, and M.R.Jadhav Prof. "MPLEMENTATION OF HALF PRECISION FLOATING POINT ARITHMETIC OPERATIONS FOR DSP APPLICATIONS." JournalNX - a Multidisciplinary Peer Reviewed Journal RIT PG Con-18 (April 22, 2018): 280–83. https://doi.org/10.5281/zenodo.1413808.

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For dealing with digital signals in real time, parameters like, speed of operation, hardware requirement, power and area, must take into consideration. Implementation of FFT, with less number of logic gates which helps to reduce area and power required for the design. With this motto multipliers are replaced with pass logic. To represent twiddle factors, standard IEEE floating point format is used. By considering The end user application, twiddle factors are represented in half precision format. So that it helps to increase the speed of application. FFT is completed with complex floating point

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Ramya Rani, N. "Implementation of Embedded Floating Point Arithmetic Units on FPGA." Applied Mechanics and Materials 550 (May 2014): 126–36. http://dx.doi.org/10.4028/www.scientific.net/amm.550.126.

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:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper,

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Mishra, Raj Gaurav, and Amit Kumar Shrivastava. "Implementation of Custom Precision Floating Point Arithmetic on FPGAs." HCTL Open International Journal of Technology Innovations and Research (IJTIR) 1, January 2013 (2013): 10–26. https://doi.org/10.5281/zenodo.160887.

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Floating point arithmetic is a common requirement in signal processing, image processing and real time data acquisition & processing algorithms. Implementation of such algorithms on FPGA requires an efficient implementation of floating point arithmetic core as an initial process. We have presented an empirical result of the implementation of custom-precision floating point numbers on an FPGA processor using the rules of IEEE standards defined for single and double precision floating point numbers. Floating point operations are difficult to implement on FPGAs because of their complexity in

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19

M. Rane, Sonali, Mrs Trupti Wagh, and Dr Mrs P. Malathi. "An Implementation of Double precision Floating point Adder & Subtractor Using Verilog." IOSR Journal of Electrical and Electronics Engineering 9, no. 4 (2014): 01–05. http://dx.doi.org/10.9790/1676-09430105.

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T.Govinda, Rao, Pradeep P.Devi, and P.Kalyanchakravarthi. "DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTOR SUPPORT." International Journal Of Microwave Engineering (JMICRO) 1, no. 2 (2022): 9. https://doi.org/10.5281/zenodo.7353323.

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This paper presents floating point multiplier capable of supporting wide range of application domains like scientific computing and multimedia applications and also describes an implementation of a floating point multiplier that supports the IEEE 754-2008 binary interchange format with methodology for estimating the power and speed has been developed. This Pipelined vectorized floating point multiplier supporting FP16, FP32, FP64 input data and reduces the area, power, latency and increases throughput. Precision can be implemented by taking the 128 bit input operands.The floating point units c

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Mohammed, Falih Hassan, Farhood Hussein Karime, and Al-Musawi Bahaa. "Design and implementation of fast floating point units for FPGAs." Indonesian Journal of Electrical Engineering and Computer Science 19, no. 3 (2022): 1480–89. https://doi.org/10.11591/ijeecs.v19.i3.pp1480-1489.

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Due to growth in demand for high-performance applications that require high numerical stability and accuracy, the need for floating-point FPGA has been increased. In this work, an open-source and efficient floating-point unit is implemented on a standard Xilinx Sparton-6 FPGA platform. The proposed design is described in a hierarchal way starting from functional block descriptions toward modules level design. Our implementation used minimal resources available on the targeting FPGA board, tested on the Sparton-6 FPGA platform and verified on ModelSim. The open-source framework can be embedded

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R., Bhuvanapriya, and T. Menakadevi. "Design and Implementation of FPU for Optimised Speed." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 3922–33. https://doi.org/10.35940/ijeat.C6444.029320.

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Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need

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Hassan, Mohammed Falih, Karime Farhood Hussein, and Bahaa Al-Musawi. "Design and implementation of fast floating point units for FPGAs." Indonesian Journal of Electrical Engineering and Computer Science 19, no. 3 (2020): 1480. http://dx.doi.org/10.11591/ijeecs.v19.i3.pp1480-1489.

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<p>Due to growth in demand for high-performance applications that require high numerical stability and accuracy, the need for floating-point FPGA has been increased. In this work, an open-source and efficient floating-point unit is implemented on a standard Xilinx Sparton-6 FPGA platform. The proposed design is described in a hierarchal way starting from functional block descriptions toward modules level design. Our implementation used minimal resources available on the targeting FPGA board, tested on Sparton-6 FPGA platform and verified on ModelSim. The open-source framework can be embe

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Neeraja, P. K., and Narayanadass Ramadass. "A Modified Fused Floating Point Three Term Adder." International Journal of Engineering and Advanced Technology (IJEAT) 10, no. 1 (2020): 415–19. https://doi.org/10.35940/ijeat.A1908.1010120.

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This paper is about a modified architecture for a fused floating point three term adder. The important feature of a fused floating-point three-term adder is its ability to do multiple additions in same block to get better performance as well as accuracy compared to a conventional discrete floating point adder. The parallel prefix adder is one amongst the fastest adders and out of which the han-carlson adder represents a blend of the kogge-stone adders and brent-kung adder. In this work, han carlson adder is used to enhance the performance of the three term adder along with various optimization

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SHARMA, SUBHASH KUMAR, SHRI PRAKASH DUBEY, and ANIL KUMAR MISHRA. "Development of Library Components for Floating Point Processor." Journal of Ultra Scientist of Physical Sciences Section A 33, no. 4 (2021): 42–50. http://dx.doi.org/10.22147/jusps-a/330402.

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This paper deals with development of an n-bit binary to decimal conversion, decimal to n bit binary conversion and decimal to IEEE-754 conversion for floating point arithmetic logic unit (FPALU) using VHDL. Normally most of the industries now a days are using either 4-bit conversion of ALU or 8-bit conversions of ALU, so we have generalized this, thus we need not to worry about the bit size of conversion of ALU. It has solved all the problems of 4-bit, 8-bit, 16-bit conversions of ALU’s and so on. Hence, we have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task

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Luсkij, Georgi, and Oleksandr Dolholenko. "Development of floating point operating devices." Technology audit and production reserves 5, no. 2(73) (2023): 11–17. http://dx.doi.org/10.15587/2706-5448.2023.290127.

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The paper shows a well-known approach to the construction of cores in multi-core microprocessors, which is based on the application of a data flow graph-driven calculation model. The architecture of such kernels is based on the application of the reduced instruction set level data flow model proposed by Yale Patt. The object of research is a model of calculations based on data flow management in a multi-core microprocessor. The results of the floating-point multiplier development that can be dynamically reconfigured to handle five different formats of floating-point operands and an approach to

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Mr., Anand S. Burud, and Pradip C. Bhaskar Dr. "Processor Design Using 32 Bit Single Precision Floating Point Unit." International Journal of Trend in Scientific Research and Development 2, no. 4 (2018): 198–202. https://doi.org/10.31142/ijtsrd12912.

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The floating point operations have discovered concentrated applications in the various different fields for the necessities for high precision operation because of its incredible dynamic range, high exactness and simple operation rules. High accuracy is needed for the design and research of the floating point processing units. With the expanding necessities for the floating point operations for the fast high speed data signal processing and the logical operation, the requirements for the high speed hardware floating point arithmetic units have turned out to be increasingly requesting. The ALU

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Sanivarapu, Rambabu, Mallikarjuna Rao Y., Venkataiah C., Linga Murthy M.K., Laith H. Alzubaidi, and Vyeshikha. "Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL." E3S Web of Conferences 391 (2023): 01184. http://dx.doi.org/10.1051/e3sconf/202339101184.

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Due to recent developments, the POSIT number system, winch has been planned as a successor for numbers that are expressed in IEEE floating-point, which are in the focus of advances in arithmetic. Although this format claims to deliver more precise outcomes with the same bit width as ordinary floating point, the duration of the operation fluctuation during posit field identification poses a hardware design problem. The POSIT-based MAC Unit is created using Verilog HDL in this study, and the designed architecture is evaluated for good operation before being implemented on an FPGA using Xilinx Vi

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Wu, Chen, Mingyu Wang, Xinyuan Chu, Kun Wang, and Lei He. "Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration." ACM Transactions on Reconfigurable Technology and Systems 15, no. 1 (2022): 1–21. http://dx.doi.org/10.1145/3474597.

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Low-precision data representation is important to reduce storage size and memory access for convolutional neural networks (CNNs). Yet, existing methods have two major limitations: (1) requiring re-training to maintain accuracy for deep CNNs and (2) needing 16-bit floating-point or 8-bit fixed-point for a good accuracy. In this article, we propose a low-precision (8-bit) floating-point (LPFP) quantization method for FPGA-based acceleration to overcome the above limitations. Without any re-training, LPFP finds an optimal 8-bit data representation with negligible top-1/top-5 accuracy loss (within

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Dharmavaram, Asha Devi, Suresh Babu M, and Prasad Acharya G. "CUSTOM IP DESIGN AND VERIFICATION FOR IEEE754 SINGLE PRECISION FLOATING POINT ARITHMETIC UNIT." ASEAN Engineering Journal 14, no. 2 (2024): 69–76. http://dx.doi.org/10.11113/aej.v14.20678.

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The compact and accurate way of representing numbers in a wide range is the advantage of floating-point (FP) representation and computation. The floating-point digital signal processors offer the IPs that should have the features of low power, high performance, and less area in cost-effective designs. The proposed paper demonstrates the design and implementation of a 32-bit floating-point arithmetic unit (FPAU). The arithmetic operations performed by the FPAU are in the IEEE 754 single precision format for FP numbers. Before performing the 32-bit FP arithmetic operations, the input operands ar

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Et. al., C. Padma,. "Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 10 (2021): 5248–56. http://dx.doi.org/10.17762/turcomat.v12i10.5319.

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There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butt

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Jin, Zheming, and Jason D. Bakos. "A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines." International Journal of Reconfigurable Computing 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/849545.

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We describe a heuristic scheduling approach for optimizing floating-point pipelines subject to input port constraints. The objective of our technique is to maximize functional unit reuse while minimizing the following performance metrics in the generated circuit: (1) maximum multiplexer fanin, (2) datapath fanout, (3) number of multiplexers, and (4) number of registers. For a set of systems biology markup language (SBML) benchmark expressions, we compare the resource usages given by our method to those given by a branch-and-bound enumeration of all valid schedules. Compared with the enumeratio

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Girija, Sanjeevaiah, and Bhandari Gajanan Sangeetha. "Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 1 (2023): 697–708. https://doi.org/10.11591/ijece.v13i1.pp697-708.

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The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with highperformance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP m

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Dec, Grzegorz Rafał. "LSTM Cell Implementation on FPGAs." Parallel Processing Letters 31, no. 02 (2021): 2150011. http://dx.doi.org/10.1142/s0129626421500110.

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This paper presents and discusses the implementation of an LSTM cell on an FPGA with an activation function inspired by the CORDIC algorithm. The realization is performed using both IEEE754 standard and 32-bit integer numbers. The case with floating-point arithmetic is analyzed with and without DSP blocks provided by the Xilinx design suite. The alternative implementation including the integer arithmetic was optimized for a minimal number of clock cycles. Presented implementation uses xc6slx150t-2fgg900 and achieves high calculations accuracy for both cases.

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Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Design Efficient Vedic-Multiplier for Floating-Point MAC Module." Iraqi Journal for Electrical and Electronic Engineering 20, no. 2 (2024): 182–89. http://dx.doi.org/10.37917/ijeee.20.2.15.

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Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced desi

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M, Lakshmi Kiran, Nikhileswar K, and Venkata Ramanaiah K. "FPGA IMPLEMENTATION OF CSD BASED NN IMAGE COMPRESSION ARCHITECTURE." ICTACT Journal on Microelectronics 6, no. 4 (2021): 1052–55. https://doi.org/10.21917/ijme.2021.0183.

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Complexity will be the critical issue in VLSI implementation of Image Compression Architectures. Especially it will be predominant issue while dealing with NN based image compression architectures. Due to the development of FPGA, dealing of NN Image Compression Architecture becomes smoother. Furthermore reducing power consumption of those architectures can be deal with CSD algorithms. NN based compression can be added to standard JPEG compression is proved be an efficient strategy for dealing images of high resolution in terms of speed and power. CSD algorithm is proved to provide low power co

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Cantó Navarro, Enrique, Rafael Ramos Lara, and Mariano López García. "Online Signature Verification Systems on a Low-Cost FPGA." Applied Sciences 12, no. 1 (2021): 378. http://dx.doi.org/10.3390/app12010378.

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This paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision floating-point IEEE 754 format. The double-precision computations are replaced by simpler formats, without affecting the biometrics performance, in order to permit efficient implementations on low-cost FPGA families. The first approach is an embedded system based on MicroBlaze, a 32-bit soft-core microprocessor designed for Xilinx FPGAs, which can be configured by incl

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Rubia, J. Jency, and GA Sathish Kumar. "A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm." International Journal of Electrical Engineering & Education 57, no. 4 (2018): 361–75. http://dx.doi.org/10.1177/0020720918813836.

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The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the

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Li, Jiao, Xinjing Zhou, Binbin Wang, Huaming Shen, and Feng Ran. "Design of Efficient Floating-Point Convolution Module for Embedded System." Electronics 10, no. 4 (2021): 467. http://dx.doi.org/10.3390/electronics10040467.

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The convolutional neural network (CNN) has made great success in many fields, and is gradually being applied in edge-computing systems. Taking the limited budget of the resources in the systems into consideration, the implementation of CNNs on embedded devices is preferred. However, accompanying the increasingly complex CNNs is the huge cost of memory, which constrains its implementation on embedded devices. In this paper, we propose an efficient, pipelined convolution module based on a Brain Floating-Point (BF16) to solve this problem, which is composed of a quantization unit, a serial-to-mat

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Sanjeevaiah, Girija, and Sangeetha Bhandari Gajanan. "Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 1 (2023): 697. http://dx.doi.org/10.11591/ijece.v13i1.pp697-708.

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<p><span>The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mant

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Shi, Kaisheng, Mingwei Wang, Xin Tan, Qianghua Li, and Tao Lei. "Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA." Information 14, no. 3 (2023): 194. http://dx.doi.org/10.3390/info14030194.

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This paper proposes an efficient dynamic reconfigurable CNN accelerator (EDRCA) for FPGAs to tackle the issues of limited hardware resources and low energy efficiency in the deployment of convolutional neural networks on embedded edge computing devices. First, a configuration layer sequence optimization method is proposed to minimize the configuration time overhead and improve performance. Second, accelerator templates for dynamic regions are designed to create a unified high-speed interface and enhance operational performance. The dynamic reconfigurable technology is applied on the Xilinx KV2

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Shinde, Vaishnavi, Zeba Karpude, Pooja Kolhe, and Alpesh Wadte. "Design and Simulation of 32-Bit RISC Architecture Based on MIPS using Verilog." International Scientific Journal of Engineering and Management 04, no. 03 (2025): 1–7. https://doi.org/10.55041/isjem02553.

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VERILOG Very High-Speed Integrated Circuits Hardware Description Language) is widely used for ASIC (Application Specific Integrated Circuits) emulation, as well as a solution for applications with high volatility. FPGA (Field Programmable Gate Array) give quick time to market, and its feature of re-programmability often makes them the main part of the system. This paper presents the design of a RISC (Reduced Instruction Set Computer) CPU architecture based on MIPS (Microprocessor Interlock Pipeline Stages) using Verilog. It also describes the instruction set, architecture and timing diagram of

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Teymourzadeh. "On-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDM." American Journal of Engineering and Applied Sciences 3, no. 1 (2010): 25–30. http://dx.doi.org/10.3844/ajeassp.2010.25.30.

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Ranjeeta, Yadav, Tripathi Rohit, and Yadav Sachin. "FPGA Implementation of Efficient FIR Filter." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 3410–12. https://doi.org/10.35940/ijeat.C6349.029320.

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Improve the functionality of an FIR Filter by modifying the internal components used to design a filter. These past years have seen some great improvements in the speed, power, and area of the filter. Here, we will, therefore, use an ALU-based algorithm to design our FIR filter. The internal components of the ALU block will be an Adder and a Multiplier. A Floating point Adder and a Floating Point Multiplier will be the basic backbone of the ALU block, which finally will be used to design and implement our FIR filter design. Therefore, the parameters of the area are our main target but we will

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Al-Musawi, Wisal Adnan, Wasan A. Wali, and Mohammed Abd Ali Al-Ibadi. "New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 1955. http://dx.doi.org/10.11591/ijece.v12i2.pp1955-1964.

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<p>This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement. The sec

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Wisal, Adnan Al-Musawi, A. Wali Wasan, and Abd Ali Al-Ibadi Mohammed. "New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 1955–64. https://doi.org/10.11591/ijece.v12i2.pp1955-1964.

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This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement

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Al-Musawi, Wisal Adnan, Mohammed Abd Ali Al-Ibadi, and Wasan A. Wali. "Artificial intelligence techniques for encrypt images based on the chaotic system implemented on field-programmable gate array." IAES International Journal of Artificial Intelligence (IJ-AI) 12, no. 1 (2023): 347. http://dx.doi.org/10.11591/ijai.v12.i1.pp347-356.

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<span lang="EN-US">Image encryption is an important issue in protecting the content of images and in the area of information security. This article proposes a novel method for image encryption and decryption using the structure of the artificial neural network (ANN)-based chua chaotic system (CCS). This structure was efficiently designed on a field-programmable gate array (FPGA) chip utilizing the xilinx system generator (XSG) tool with the IEEE-754-1985 32-bit floating-point number format. For ANN-based CCS design, a multilayer feed forward neural network (FFNN) structure with three inp

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Wisal, Adnan Al-Musawi, Abd Ali Al-Ibadi Mohammed, and A. Wali Wasan. "Artificial intelligence techniques for encrypt images based on the chaotic system implemented on field-programmable gate array." International Journal of Artificial Intelligence (IJ-AI) 12, no. 1 (2023): 347–56. https://doi.org/10.11591/ijai.v12.i1.pp347-356.

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Image encryption is an important issue in protecting the content of images and in the area of information security. This article proposes a novel method for image encryption and decryption using the structure of the artificial neural network (ANN)-based chua chaotic system (CCS). This structure was efficiently designed on a field-programmable gate array (FPGA) chip utilizing the xilinx system generator (XSG) tool with the IEEE-754-1985 32- bit floating-point number format. For ANN-based CCS design, a multilayer feed forward neural network (FFNN) structure with three inputs and three outputs wa

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Wang, Cheng C., Changchun Shi, Robert W. Brodersen, and Dejan Marković. "An Automated Fixed-Point Optimization Tool in MATLAB XSG/SynDSP Environment." ISRN Signal Processing 2011 (May 10, 2011): 1–17. http://dx.doi.org/10.5402/2011/414293.

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This paper presents an automated tool for floating-point to fixed-point conversion. The tool is based on previous work that was built in MATLAB/Simulink environment and Xilinx System Generator support. The tool is now extended to include Synplify DSP blocksets in a seamless way from the users' view point. In addition to FPGA area estimation, the tool now also includes ASIC area estimation for end-users who choose the ASIC flow. The tool minimizes hardware cost subject to mean-squared quantization error (MSE) constraints. To obtain more accurate ASIC area estimations with synthesized results, 3

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Benevenuti, Fabio, Fernanda Lima Kastensmidt, Ádria Barros de Oliveira, et al. "Robust Convolutional Neural Networks in SRAM-based FPGAs: a Case Study in Image Classification." Journal of Integrated Circuits and Systems 16, no. 2 (2021): 1–12. http://dx.doi.org/10.29292/jics.v16i2.504.

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This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for

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