Relevant bibliographies by topics / Xilinx ISE software

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Academic literature on the topic 'Xilinx ISE software'

Author: Grafiati
Published: 4 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Xilinx ISE software"

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SALEH, ANDHI RACHMAN, and SUNNY ARIEF SUDIRO. "CRC 8-bit Encoder-Decoder Component in FPGA using VHDL." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, no. 1 (2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

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AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i
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Rejab Khalil, Mazin, and Rafal Taha Mahmood. "Designing of Soft Core Processor System with Direct Memory Access (DMA) Mode." University of Thi-Qar Journal for Engineering Sciences 6, no. 2 (2015): 53–64. http://dx.doi.org/10.31663/utjes.v6i2.74.

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A soft core processor system is constructed using embedded design techniques and it is configured on Field Programmable Gate Arrays (FPGAs). The system is accommodated to act with Direct Memory Access (DMA) mode using suitable Xilinx Intellectual Property (IP) core. A dual data rate synchronous dynamic random access memory (DDR_SDRAM) with 64 Mbyte capacity is introduced to the system and accessed by the DMA controller.The controller is performed to transfer programmable quantity of data from source address to destination address without intervention of the processor. Spartan-3E slice is used and programmed using Xilinx Platform Studio (XPS)which is provided by Xilinx integrated software environment at (ISE 10.1). The system performance is tested by transferring data from matlab media to the DDR_SDRAM and vice-versa, mat lab 2012a version software is used for this type of data transfer.
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Bespalov, Nikolay, and Yury Goryachkin. "Device for Current Test Pulse Development Through a Diode in a Direct Direction." International Journal of Engineering & Technology 7, no. 3.19 (2018): 81. http://dx.doi.org/10.14419/ijet.v7i3.19.16991.

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The article is devoted to the development of a device that allows to generate control current pulses to determine the current-voltage characteristic of diodes in the forward direction. To implement the device, we use NI Digital Electronics FPGA Board, which includes FPGA XC3S500E Xilinx Spartan-3E FPGA and the Linear Technology LTC2624 chip, containing four 12-bit DACs. We consider the creation of a software module via VHDL language that generates 12-bit digital code to create rectangular voltage control pulses with a successively increasing amplitude and transmitted via SPI interface as the part of 32-bit data transfer protocol, using Xilinx WebPACK ISE software.
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Mahmoud, Mohamed Ibrahim, Sayed Mohamed El-Araby, Safey Ahmed Shehata, Refaat Mohamed Fikry AbouZaid, and Fathi Abd El-Samie. "Design and Implementation of a Fast General Purpose Fuzzy Processor." International Journal of System Dynamics Applications 2, no. 4 (2013): 1–18. http://dx.doi.org/10.4018/ijsda.2013100101.

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In this paper, a Fast Fuzzy processor (FP) is proposed. This processor, which is implemented using FPGA, has four inputs and one output with 8-bits width for each. The proposed processor is synthesized, functionally verified and implemented using Xilinx Integrated Software Environment (ISE) and is tested using Xilinx Spartan 3E starter kit. A PC Graphical User Interface (GUI) is programmed using C# programming language to select and download the parameters of the processor through the serial port communication. The proposed processor is experimentally tested through water sprinkler system example. The experimental results approve the excellent performance of the proposed processor.
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Radhika, Jindal. "DESIGN AND SYNTHESIS FOR DEEP LEARNING AND MULTILAYER NEURAL NETWORK ARCHITECTURE USING VHDL." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 9, no. 5 (2020): 191–95. https://doi.org/10.5281/zenodo.3865907.

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Artificial neural networks are extended on the basis of brain structure. Like the brain, ANNs can recognize patterns, handle facts and figures and be trained. They are prepared by artificial neurons which employ the quintessence of genetic neurons. In the research work, we have considered the 8 inputs ANN signal which is multiplied with their corresponding weights. The hardware chip is designed to support the system functionality in Xilinx ISE 14.2 software. The designed chip is simulated with Modelsim 10.0 software for test cases. The designed chip is also synthesized on SPARTAN-3E FPGA using VHDL programming and device hardware and timing parameters are also analyzed for the functionality of the chip.
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Agarwal, Charul, Ashutosh Gupta, and Haneet Rana. "Performance Analysis and FPGA Implementation of Digital PID Controller for Speed Control of DC Motor." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 3 (2013): 638–45. http://dx.doi.org/10.24297/ijct.v7i3.3443.

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This paper deals with the performance analysis and implementation of PID(Proportional-Integral-Derivative) Controller on FPGA platform.The hardware implementation has been done on Xilinx Spartan 3E FPGA board.The software implementation has been done using Xilinx ISE 8.1i as a tool and simulation is performed using ModelSim 5.4a as a simulator.The PWM signal is generated by FPGA board,which further given to dc motor for its speed control. A new technique has been introduced for the generation of the control input as a PWM signal for controlling the motor driver circuit and decoding the optical encoder data for using it for the speed feedback in the PID control loop. The VHDL algorithm for the proposed implementation has been presented in this paper. Performance analysis of PID controller using MATLAB software shows the effectiveness of the proposed method.
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Al-Gailani, M. F., and Alshaima Q. Al-Khafaji. "Loop Unrolling Implementation of an AES Algorithm using Xilinx System Generator." Iraqi Journal of Information & Communications Technology 2, no. 3 (2019): 38–45. http://dx.doi.org/10.31987/ijict.2.3.85.

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Cryptographic algorithm is a tool that is used to secure the transmitted data on the network. The current standard algorithm the Advanced Encryption Standard (AES) is used to maintain the security and reliability of the encrypted data whether these data are stored in computer or in transmit. AES can be implemented either in hardware or software, however hardware implementation is more sensible for high speed applications. In this paper, AES-128 algorithm is implemented in hardware in order to achieve a high-speed data processing. It is implemented on an FPGA platform using HLL language and Xilinx ISE software. The design is effectively optimized and Synthesizable with high accuracy using the conventional blocks of Xilinx System Generator. The results of implementation have enhanced the performance in terms of resource utilization, speed and power consumption as compared with other related works. The circuit operates at a maximum frequency of 800.000 MHz which offers a high throughput of 102.4 Gbps on virtex6 xc6vlx130t-3ff1156, in addition it occupies only 2,405 slices.
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Krim, Saber, Soufien Gdaim, Abdellatif Mtibaa, and Mohamed Faouzi Mimouni. "FPGA-Based Implementation Direct Torque Control of Induction Motor." International Journal of Power Electronics and Drive Systems (IJPEDS) 5, no. 3 (2015): 293. http://dx.doi.org/10.11591/ijpeds.v5.i3.pp293-304.

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<p>This paper proposes a digital implementation of the direct torque control (DTC) of an Induction Motor (IM) with an observation strategy on the Field Programmable Gate Array (FPGA). The hardware solution based on the FPGA is caracterised by fast processing speed due to the parallel processing. In this study the FPGA is used to overcome the limitation of the software solutions (Digital Signal Processor (DSP) and Microcontroller). Also, the DTC of IM has many drawbacks such as for example; The open loop pure integration has from the problems of integration especially at the low speed and the variation of the stator resistance due to the temperature. To tackle these problems we use the Sliding Mode Observer (SMO). This observer is used estimate the stator flux, the stator current and the stator resistance. The hardware implementation method is based on Xilinx System Generator (XSG) which a modeling tool developed by Xilinx for the design of implemented systems on FPGA; from the design of the DTC with SMO from XSG we can automatically generate the VHDL code. The model of the DTC with SMO has been designed and simulated using XSG blocks, synthesized with Xilinx ISE 12.4 tool and implemented on Xilinx Virtex-V FPGA.</p>
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T. Gadawe, Nour, and Sahar L. Qaddoori. "Design and implementation of smart traffic light controller using VHDL language." International Journal of Engineering & Technology 8, no. 4 (2019): 596. http://dx.doi.org/10.14419/ijet.v8i4.29478.

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The purpose of this paper is to design and implementation of smart traffic light controller system using VHDL language and FPGA. A structure of four road intersection has been selected. The intersection to be controlled is between a busy (main street), and somewhat less busy (side street), with sensor for the side street and walk request button. Also, the system contains switches to control the traffic light manually. The intersection uses four timing parameters with ability to change these parameters manually. The system has been successfully tested with VHDL using Xilinx ISE 14.7i software environment and Chip-Scope, while, it is implemented in hardware using Xilinx Spartan 3E FPGA. It is easy to use and the cost for the same is also less as compared to the others. The designed traffic light control system is presented to work correctly as predictable.
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Kirat, Pal Singh, and Dod Shiwani. "An Efficient Hardware design and Implementation of Advanced Encryption Standard (AES) Algorithm." International Journal of Recent Advances in Engineering & Technology 4, no. 2 (2016): 5–9. https://doi.org/10.5281/zenodo.48483.

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We propose an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES). The AES algorithm defined by the National Institute of Standard and Technology (NIST) of United States has been widely accepted. The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. This contribution investigates the AES encryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language (VHDL). Optimized and Synthesizable VHDL code is developed for the implementation of 128- bit data encryption process. AES encryption is designed and implemented in FPGA, which is shown to be more efficient than published approaches. Xilinx ISE 12.3i software is used for simulation. Each program is tested with some of the sample vectors provided by NIST and output results are perfect with minimal delay. The throughput reaches the value of 1609Mbit/sec for encryption process with Device XC6vlx240t of Xilinx Virtex Family.
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Book chapters on the topic "Xilinx ISE software"

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Sk, Kamarujjaman, Manali Mukherjee, and Mausumi Maitra. "FPGA-Based Re-Configurable Architecture for Window-Based Image Processing." In Advances in Computational Intelligence and Robotics. IGI Global, 2017. http://dx.doi.org/10.4018/978-1-5225-0889-2.ch001.

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In this proposed book chapter, a simple but efficient presentation of Median Filter, Switching Median Filter, Adaptive Median Filter and Decision-Based Adaptive Filtering Method and their hardware architecture for FPGA is described for removal of up to 99% impulse noise from Digital Images. For hardware architecture, simulation is done using Xilinx ISE 14.5 software of XILINX. For implementation, these approaches utilize Genesys VIRTEX V FPGA device of XC5VLX50T device family. In this approach, we proposed an efficient design for suppression of impulse noise from digital images corrupted by up to 99% impulse noise using decision based adaptive filtering method as well as preserve the details of image. The method works in two different stages – noise detection using switching technique and finally noise suppression and restoration. Experimental results show that our method perform better in terms of PSNR below 80% noise density but above 80% noise density it is almost comparable with the latest methods.
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Sk, Kamarujjaman, Manali Mukherjee, and Mausumi Maitra. "FPGA-Based Re-Configurable Architecture for Window-Based Image Processing." In Computer Vision. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-5204-8.ch011.

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In this proposed book chapter, a simple but efficient presentation of Median Filter, Switching Median Filter, Adaptive Median Filter and Decision-Based Adaptive Filtering Method and their hardware architecture for FPGA is described for removal of up to 99% impulse noise from Digital Images. For hardware architecture, simulation is done using Xilinx ISE 14.5 software of XILINX. For implementation, these approaches utilize Genesys VIRTEX V FPGA device of XC5VLX50T device family. In this approach, we proposed an efficient design for suppression of impulse noise from digital images corrupted by up to 99% impulse noise using decision based adaptive filtering method as well as preserve the details of image. The method works in two different stages – noise detection using switching technique and finally noise suppression and restoration. Experimental results show that our method perform better in terms of PSNR below 80% noise density but above 80% noise density it is almost comparable with the latest methods.
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Gharaee, Hossein, Abdolreza Nabavi, and Jalil ("Joe") Etminan. "Performance and Complexity Evaluation of OTR-UWB Receiver." In Networking and Telecommunications. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-986-1.ch123.

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This article presents a new transmitted reference UWB receiver, which utilizes the orthogonal property of even and odd order derivatives of Gaussian pulses in neighboring chips for synchronization. This system, referred to as orthogonal TR-UWB (OTR-UWB), employs only a single spreading code, which results in much lower mean detection time compared to DS-UWB systems. The hardware complexity for OTR-UWB receiver is significantly reduced against conventional TR-UWB systems. In addition, simulation results show that BER performance is improved, while the new system is capable of supporting higher data rates. Also, this article presents the FPGA implementation of OTR-UWB, with a bit-rate of 25Mb/s without using equalizer. In addition, we present the DSP algorithm of baseband. Hardware of this system is implemented on two different FPGAs from ALTERA and XILINX, CycloneII (EP2C35F672C6) and Spartan 3 (3s4000fg676-5). Gate estimation and power analysis are performed by Quartus II 7.2 (ALTERA) and ISE 8.1 (XILINX) softwares.
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Conference papers on the topic "Xilinx ISE software"

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Fadzilah Mokhtar, Nor, Afaf Rozan Mohd Radzol, and Suzana Ab Rahim. "Xilinx ISE software teaching aid for Diploma's students." In 2009 International Conference on Engineering Education (ICEED). IEEE, 2009. http://dx.doi.org/10.1109/iceed.2009.5490614.

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Lei, Shuliang, Andy Provenza, Alan Palazzolo, and Raymond Beach. "Implementation of Magnetic Suspension Control With FPGA." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-44057.

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This paper presents a methodology for an alternative implementation of DSP-based controllers typically used for magnetic bearing (MB) levitation and control on FPGA hardware. The approach takes s-domain transfer functions of the controller components and discretizes them using z-transform conversions into discrete time domain expressions. These expressions, which are essentially digital IIR filters, are synthesized and implemented to obtain downloadable bit-stream using Xilinx ISE software packages. In the example presented, the executable code was sent to configure the two FPGAs for control. An equivalent PD with notch filter FPGA-based controller was constructed to replicate an existing two-axis DSP controller used to control a radial magnetic bearing on a vertical rotor in the Dynamic Spin Rig Facility at NASA Glenn Research Center. The FPGA controller was successfully demonstrated on the NASA hardware.
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