Relevant bibliographies by topics / Xilinx / Dissertations / Theses
To see the other types of publications on this topic, follow the link: Xilinx.

Dissertations / Theses on the topic 'Xilinx'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'Xilinx.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Möhrke, Ulrich, Paul Herrmann, and Marco Schmidt. "Das Xilinx-LCA-Format." Universität Leipzig, 1996. https://ul.qucosa.de/id/qucosa%3A34507.

Full text
Abstract:
Es wird eine kurze Beschreibung des LCA-Formats gegeben. Dateien dieses Formats werden im Design Flow des XACT Systems von Xilinx als Ausgabe der Plazier- und Verdrahtungsprogramme APR bzw. PPR erzeugt. Bei der hier gegebenen kurzen Beschreibung stehen die Angaben zur Verdrahtung im Vordergrund.
APA, Harvard, Vancouver, ISO, and other styles
2

Fandén, Petter. "Evaluation of Xilinx System Generator." Thesis, Linköping University, Department of Science and Technology, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1033.

Full text
Abstract:
<p>This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG) and blockset for Matlab. XSG is a module to simulink developed by Xilinx in order to generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm. </p><p>In order to investigate the performance of this new module XSG to simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without
APA, Harvard, Vancouver, ISO, and other styles
3

Krohn, Jørgen, and Jørgen Linnerud. "MPEG Transcoder for Xilinx Spartan." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8896.

Full text
Abstract:
<p>In this project the focus has been on developing an MPEG transcoder that can be used as a demonstration module for the AHEAD system, Ambient Hardware: Embedded Architecture on Demand. AHEAD is a collaboration project between NTNU and SINTEF in Trondheim that is aiming to develop a method of doing run-time reconfiguration of hardware. The AHEAD system will in the future use an FPGA in a tag that is able to reconfigure itself with hardware description that it receives from a hand-held device, e.g. a PDA, or downloads from the Internet. The tag will then be able to be operating as a co-process
APA, Harvard, Vancouver, ISO, and other styles
4

Yue, Xi. "Rapid Overlay Builder for Xilinx FPGAs." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/50907.

Full text
Abstract:
A field-programmable gate array (FPGA) is a type of programmable hardware, where a logic designer must create a specific hardware design and then "compile" it into a bitstream that "configures" the device for a specific function at power-up. This compiling process, known as place-and-route (PAR), can take hours or even days, a duration which discourages the use of FPGAs for solving compute-oriented problems. To help mitigate this and other problems, overlays are emerging as useful design patterns in solving compute-oriented problems. An overlay consists of a set of compiler-like tools and an a
APA, Harvard, Vancouver, ISO, and other styles
5

Nyman, Jeremia. "High Speed IO using Xilinx Aurora." Thesis, Linköpings universitet, Institutionen för systemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102424.

Full text
Abstract:
A VHDL evaluation platform and interface to the Xilinx Aurora 8b/10b IP has been designed, tested and evaluated. The evaluation platform takes an arbitrary amount of data sources and sends the data over 1,2,4 or 8 multi gigabit serial lanes, using the Aurora 8b/10b protocol. A lightweight communications protocol for point-to-point data transfer, error detection and recovery is used to maintain a reliable and efficient transmission scheme. Priority between sources sharing the serial link is also a part of the platform. The Aurora 8b/10b IP is a lightweight protocol and transceiver interface for
APA, Harvard, Vancouver, ISO, and other styles
6

Жданова, Ю. В., та І. В. Свид. "Огляд сьомої серії FPGA компанії Xilinx". Thesis, Кременчуцький льотний коледж, 2019. http://openarchive.nure.ua/handle/document/9371.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://doi.org/10.35598/mcfpga.2019.008.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-008.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Morford, Casey Justin. "BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/36198.

Full text
Abstract:
With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level
APA, Harvard, Vancouver, ISO, and other styles
10

Eriksson, Henrik. "Datorstödd implementering med hjälp av Xilinx System Generator." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2159.

Full text
Abstract:
<p>The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. </p><p>Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. </p><p>The testcases are selected to represent the FPGA designs ma
APA, Harvard, Vancouver, ISO, and other styles
11

Moroz, Valentyna. "Application of Xilinx Series 7 on FPGA (XADC)." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-011.

Full text
Abstract:
FPGA systems development has long ceased to be limited to simply writing code in hardware description languages (HDL); and as the number of logical resources and the complexity of projects increase, approaches to designing systems on FPGAs have been repeatedly revised. One of the turns of development was the introduction of soft processors into projects — essentially ordinary microprocessors but assembled on FPGA resources. Unfortunately, despite the relative difficulty of developing software-processor systems, many trying to “raise” this topic face difficulties in mastering, because they do n
APA, Harvard, Vancouver, ISO, and other styles
12

Viktorin, Jan. "HW/SW Codesign for the Xilinx Zynq Platform." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236227.

Full text
Abstract:
This work describes a novel approach of HW/SW codesign on the Xilinx Zynq and similar platforms. It deals with interconnections between the Processing System (ARM Cortex-A9 MPCore) and the Programmable Logic (FPGA) to find an abstract and universal way to develop applications that are partially offloaded into the programmable hardware and that run in the Linux operating system. For that purpose a framework for HW/SW codesign on the Zynq and similar platforms is designed. No such framework is currently available.
APA, Harvard, Vancouver, ISO, and other styles
13

Nosko, Svetozár. "Akcelerace HDR tone-mappingu na platformě Xilinx Zynq." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255329.

Full text
Abstract:
This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zy
APA, Harvard, Vancouver, ISO, and other styles
14

Savory, Daniel Chase. "Power Side-Channel DAC Implementations for Xilinx FPGAs." BYU ScholarsArchive, 2014. https://scholarsarchive.byu.edu/etd/4038.

Full text
Abstract:
This thesis presents a novel power side-channel DAC (PS-DAC) which is constructed from user-controllable short circuits in FPGAs and which manipulate overall system power through dynamic power dissipation. Alternately, similar PS-DACs are created using shift-register primitives(SRL16E) which manipulate system power through switching logic, for means of comparison with short-circuit-based PS-DACs. PS-DACs are created of various sizes using both short-circuit-based and shift-register-based methods. These PS-DACs are characterized in terms of output linearity,monotonicity, and frequency distortio
APA, Harvard, Vancouver, ISO, and other styles
15

Hamre, Sverre. "Framework for self reconfigurable system on a Xilinx FPGA." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9012.

Full text
Abstract:
<p>Partial self reconfigurable hardware has not yet become main stream, even though the technology is available. Currently FPGA manufacturer like Xilinx has FPGA devices that can do partial self reconfiguration. These and earlier FPGA devices were used mostly for prototyping and testing of designs, before producing ASICS, since FPGA devices was to expensive to be used in final production designs. Now as prices for these devices are coming down, it is more and more normal to see them in consumer devices. Like routers and switches where protocols can change fast. Using a FPGA in these devices, t
APA, Harvard, Vancouver, ISO, and other styles
16

Zhang, Chi. "Tic-tac-toe game design based on Xilinx FPGA." Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-6135.

Full text
Abstract:
This design accomplished Tic-Tac-Toe game on Xilinx Spartan-IIE FPGA platformin VHDL. Firstly, designing the circuits and wiring on experiment board. Secondly,designing the algorithm and programming it in Active-HDL. Thirdly, synthesizingit in Synplicity Synplify Pro and then implementing it in Xilinx ISE developingsuite. Finally download it onto FPGA to run it. This design allows two players to play Tic-Tac-Toe game on the experiment board.Pressing the key, the corresponding LED will be light up to represent thechessman. There are two LEDs indicate whose turn next is. If the grid one wantsto
APA, Harvard, Vancouver, ISO, and other styles
17

Houška, David. "Poloautomatizovaný návrh vysoce výkonných číslicových obvodů s Xilinx FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2021. http://www.nusl.cz/ntk/nusl-442592.

Full text
Abstract:
Tato diplomová práce se zabývá návrhem sekvenčních digitálních obvodů s ohledem na optimalizaci zpoždění. V práci je popsána problematika dvou technik, které jsou běžně používané při optimalizaci – stručně je popsána technika tzv. synchronizace registrů (angl. retiming), větší pozornost je však věnována technice tzv. zřetězení (angl. pipelining). V rámci praktické části byla vypracována forma abstrakce sekvenčních digitálních obvodů pomocí acyklických orientovaných grafů. Obvod je tak přenesen do roviny, ve které je jednodušší jej transformovat. Zároveň je představen nástroj pro polo-automatic
APA, Harvard, Vancouver, ISO, and other styles
18

Babba, Belgacem. "Synthèse optimisée sur les réseaux programmables de la famille Xilinx." Phd thesis, Grenoble INPG, 1995. http://tel.archives-ouvertes.fr/tel-00346062.

Full text
Abstract:
Cette thèse se situe dans le cadre de la synthèse logique. Elle a pour objet la synthèse logique optimisée de circuits sur réseaux programmables à base de «tables de vérité» de type «Xilinx». Ces réseaux programmables ont été à l'origine du premier succès commercial des réseaux reprogrammables à faible granularité. Une première solution pratiquée industriellement a consisté à associer une bibliothèque équivalente de primitives logiques simples de type «cellule standard» à un réseau Xilinx. Une telle approche conduit à une très pauvre utilisation de la technologie cible car elle ne tire pas pro
APA, Harvard, Vancouver, ISO, and other styles
19

MacQueen, Daniel Montgomery. "Total ionizing dose effects on Xilinx field-programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ59840.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
20

Chamberlin, Stephen L. (Stephen Lee). "Design and implementation of a router using a Xilinx FPGA." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/12432.

Full text
Abstract:
Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1993.<br>Includes bibliographical references (leaves 64-65).<br>by Stephen L. Chamberlin.<br>B.S.
APA, Harvard, Vancouver, ISO, and other styles
21

Babba, Belgacem Saucier Gabrièle. "Synthèse optimisée sur les réseaux programmables de la famille Xilinx." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00346062.

Full text
APA, Harvard, Vancouver, ISO, and other styles
22

Lavin, Christopher Michael. "Using Hard Macros to Accelerate FPGA Compilation for Xilinx FPGAs." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/2933.

Full text
Abstract:
Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead o
APA, Harvard, Vancouver, ISO, and other styles
23

Kallam, Ramachandra. "Accelerated Frame Data Relocation on Xilinx Field Programmable Gate Array." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/655.

Full text
Abstract:
Emerging reconfiguration techniques that include partial dynamic reconfiguration and partial bitstream relocation have been addressed in the past in order to expose the flexibility of field programmable gate array at runtime. Partial bitstream relocation is a technique used to target a partial bitstream of a partial reconfigurable region (PRR) onto other identical reconfigurable regions inside an FPGA, while partial dynamic reconfiguration is used to target a single reconfigurable region. Prior works in this domain aim to minimize "relocation time" with the help of on-chip or on-line processin
APA, Harvard, Vancouver, ISO, and other styles
24

Farooq, Omer, and Bodiuzzaman Molla. "Observer Implementation in an FPGA Using Simulink and Xilinx System Generator." Thesis, Blekinge Tekniska Högskola, Sektionen för ingenjörsvetenskap, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4157.

Full text
Abstract:
In order to reduce the cost of the current switched resonant power converters, a state observer is introduced to provide the controller with the required information for the effective switching of the converter without the need of expensive sensory inputs from the resonant circuit. This Master&apos;s thesis investigates the usage of Matlab/Simulink and Xilinx System Generator as an implementation tool for Field Programmable Gate Array (FPGA) development of the Observer Model. The main aim is to keep the model size to a minimum while keeping the error within a reasonable range, allowing the obs
APA, Harvard, Vancouver, ISO, and other styles
25

Sohanghpurwala, Ali Asgar Ali Akbar. "OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36348.

Full text
Abstract:
The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology for creating rectangular partial reconfiguration modules that can be swapped in and out of a static baseline design with one or more PR slots. This thesis presents a new PR toolkit called OpenPR that, for starters, provides similar functionality to the Xilinx PR tool kits. The distinguishing feature of this toolkit is that it is being released as open source, and is intended to be customizable to the needs of researchers. OpenPR ha
APA, Harvard, Vancouver, ISO, and other styles
26

Boger, Timothy Jared. "Rhealstone Benchmarking of FreeRTOS and the Xilinx Zynq Extensible Processing Platform." Master's thesis, Temple University Libraries, 2013. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/216539.

Full text
Abstract:
Electrical and Computer Engineering<br>M.S.E.E.<br>Embedded system designers require deterministic, real-time operating system (RTOS) support for the commonly available processing hardware. The Xilinx Zynq Extensible Processing Platform (EPP) offers software, hardware, and input/output (I/O) programmability on a single chip. The Xilinx Zynq EPP features a Dual ARM Cortex-A9 MPCore, Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) interconnect, and Xilinx Kintex-7 series Programmable Logic (PL) which provide the requisite capabilities for the increasing de
APA, Harvard, Vancouver, ISO, and other styles
27

Красношапка, Т. Ю., та М. Г. Заворотна. "Эволюция ПЛИС серии Spartan на архитектуре FPGA". Thesis, ХНУРЕ, 2019. http://openarchive.nure.ua/handle/document/8472.

Full text
Abstract:
The evolution of the FPGA chips of the Spartan series is considered in the paper. Describes the relevance of the chip at the moment, as well as the distinctive features of each device. A comparative characteristic shown in graphical form. FPGA Spartan series is a family of programmable chips with built-in RAM by Xilinx. They are widespread. The FPGA Spartan series is the affordable prices of the XC400 series. The FPGA community in two ways. The first direction allows the implementation of efficient and technically complex architectures.
APA, Harvard, Vancouver, ISO, and other styles
28

Свид, І. В., О. С. Мальцев, О. В. Зубков, and Л. Ф. Сайківська. "Matlab Use in Design of Digital Systems on the FPGA in CAD Xilinx VIVADO." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-010.

Full text
Abstract:
Matlab is a high-level language and an interactive environment that can help to analyze data, develop algorithms, create models and applications. There are many extensions for Matlab. One of these extensions is the Xilinx System Generator for DSP, a key component of the Xilinx specialized digital signal processing platform, that allows to implement DSP algorithms with less time costs than traditional RTL design.
APA, Harvard, Vancouver, ISO, and other styles
29

Свид, І. В., О. С. Мальцев, О. В. Зубков, and Л. Ф. Сайківська. "Matlab Use in Design of Digital Systems on the FPGA in CAD Xilinx VIVADO." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-010.

Full text
Abstract:
Matlab is a high-level language and an interactive environment that can help to analyze data, develop algorithms, create models and applications. There are many extensions for Matlab. One of these extensions is the Xilinx System Generator for DSP, a key component of the Xilinx specialized digital signal processing platform, that allows to implement DSP algorithms with less time costs than traditional RTL design.
APA, Harvard, Vancouver, ISO, and other styles
30

Чумак, В. С., та І. В. Свид. "Створення модуля VHDL-опису при проектуванні цифрових систем на ПЛІС в Xilinx ISE Design Suite". Thesis, Дніпровський національний університет імені Олеся Гончара, 2019. http://openarchive.nure.ua/handle/document/10397.

Full text
Abstract:
When implementing large projects based on modern FPGAs, there are limitations to the circuitry method for describing digital devices, which are removed using high-level languages VHDL and Verilog. These limitations are most noticeable when using FPGA chips. Currently, the main means of representing digital devices in their design are HDL (Hardware Description Language). The use of high-level hardware description languages also increases the mobility of projects under development, since most design systems of various manufacturers support VHDL and Verilog standards.
APA, Harvard, Vancouver, ISO, and other styles
31

Кузнецов, М. В., та І. В. Свид. "Використання Matlab при проектуванні цифрових систем на ПЛІС у САПР Xilinx Vivado". Thesis, Кременчуцький льотний коледж, 2019. http://openarchive.nure.ua/handle/document/9375.

Full text
Abstract:
Matlab – це високорівнева мова й інтерактивне середовище для програмування, чисельних розрахунків, візуалізації результатів, технічних обчислень. Має велике число пакетів прикладних програм-розширень. За допомогою Matlab можна аналізувати дані, розробляти алгоритми, створювати моделі та додатки. Одним з таких розширень є пакет System Generator for DSP фірми Xilinx – це ключовий компонент спеціалізованих платформ для цифрової обробки сигналів (ЦОС) фірми Xilinx.
APA, Harvard, Vancouver, ISO, and other styles
32

Modi, Harmish Rajeshkumar. "In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55123.

Full text
Abstract:
FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an im
APA, Harvard, Vancouver, ISO, and other styles
33

White, Brad S. "Tincr: Integrating Custom CAD Tool Frameworks with the Xilinx Vivado Design Suite." BYU ScholarsArchive, 2014. https://scholarsarchive.byu.edu/etd/4338.

Full text
Abstract:
The field programmable gate array (FPGA) is appealing as a computational platform because of its ability to be repurposed for a number of different applications and its relatively low design cost. Traditionally, FPGA vendors provide a set of electronic design automation (EDA) tools to assist customers with the implementation of their designs. These tools are necessarily general purpose, and the resulting tool flow does not provide the user much in the way of customization. Frameworks such as RapidSmith and Torc allow for the creation of custom CAD tools that are able to target actual Xilinx FP
APA, Harvard, Vancouver, ISO, and other styles
34

Powell, Andrew Andre. "Performance of the Xilinx Zynq System-on-Chip Interconnect with Asymmetric Multiprocessing." Master's thesis, Temple University Libraries, 2014. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/306468.

Full text
Abstract:
Electrical and Computer Engineering<br>M.S.E.E.<br>For many applications, embedded designers need to construct systems that facilitate real-time constraints and thus require complete information on a processor's performance under specified parameters. An important and limiting factor in any processor's performance is how quickly components are able to intercommunicate over the system's bus. However, another important constraint, specific to real-time systems, is knowing precisely how long the data communication will require. A highly integrated system composed of multiple processing cores, ref
APA, Harvard, Vancouver, ISO, and other styles
35

Sari, Mehmet. "Designing fast Golay encoder/decoder in Xilinx XACT with Mentor Graphics CAD interface." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1997. http://handle.dtic.mil/100.2/ADA331926.

Full text
APA, Harvard, Vancouver, ISO, and other styles
36

Botvidzon, Johan. "Modellering av ett OFDM system för IEEE 802.11a med hjälp av Xilinx blockset." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1390.

Full text
Abstract:
<p>Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även
APA, Harvard, Vancouver, ISO, and other styles
37

Gustafsson, Kristian. "Implementation of a Digital Radio Frequency Memory in a Xilinx Virtex-4 FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5423.

Full text
Abstract:
<p>Digital Radio Frequency Memory (DRFM) is a technique widely used by the defense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sampling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made
APA, Harvard, Vancouver, ISO, and other styles
38

Iqbal, Rashid. "Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6355.

Full text
Abstract:
<p>This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Commun
APA, Harvard, Vancouver, ISO, and other styles
39

Burger, Roelof Jacobus. "Developing a decentralized peripheral Profibus core for a Xilinx FPGA / Roelof Jacobus Burger." Thesis, North-West University, 2010. http://hdl.handle.net/10394/4848.

Full text
Abstract:
The McTronX research group of the North–West University has over some years established a knowledge base in active magnetic bearing (AMB) systems. In 2009, an AMB system that met industrial standards in being robust, reliable and economical was developed by the research group. The digital control of the AMB system was implemented with the use of a dedicated single–board computer and communication hardware that interface with the motor drive electronics, power amplifiers and sensor drive units of the AMB system. A Xilinx® field programmable gate array (FPGA), connected to the single–board compu
APA, Harvard, Vancouver, ISO, and other styles
40

Савкин, Л. В. "Варианты проектных обликов регенеративных электронных систем на базе ПЛИС Xilinx семейства Virtex-7". Thesis, Сумский государственный университет, 2016. http://essuir.sumdu.edu.ua/handle/123456789/46432.

Full text
Abstract:
Работа посвящена разработке и исследованию способов аппаратнопрограммного построения регенеративных электронных систем (РегЭС) [1] в целях интеграции, унификации и повышения надежности функционирования бортовой аппаратуры современных космических систем и комплексов.
APA, Harvard, Vancouver, ISO, and other styles
41

Dobson, Christopher Vaness. "An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications." Thesis, Virginia Tech, 2014. http://hdl.handle.net/10919/49579.

Full text
Abstract:
The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software defined radio applications. The addition of FPGAs to these flexible systems has resulted in platforms that can address a multitude of applications with performance levels that were once only known to ASICs. This work presents an embedded heterogeneous scalable cluster platform with software defined radio applications. The Xilinx Zynq chip provides a hybrid platform consisting of an embedded ARM general-purpose processing core and a low-power FPGA. The ARM core provides
APA, Harvard, Vancouver, ISO, and other styles
42

Betti, Francesco. "Progetto di un'unità di elaborazione per una telecamera stereo basata su FPGA Xilinx." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2011. http://amslaurea.unibo.it/2596/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
43

Townsend, Thomas James. "Vivado Design Interface: Enabling CAD-Tool Design for Next Generation Xilinx FPGA Devices." BYU ScholarsArchive, 2017. https://scholarsarchive.byu.edu/etd/6492.

Full text
Abstract:
The popularity of field-programmable gate arrays (FPGA) has grown in recent years due to their potential performance advantages over sequential software, and as a prototyping platform for application-specific integrated circuits (ASIC). Vendors such as Xilinx offer automated tool suites that can be used to program FPGAs based on a RTL description. These tool suites are sufficient forgeneral users, but they usually don't provide the opportunity to integrate custom computer-aideddesign (CAD) tools into the regular design flow. Xilinx first offered this capability in their ISE tool suite with the
APA, Harvard, Vancouver, ISO, and other styles
44

Свид, І. В., О. В. Литвиненко та О. Г. Білоцерківець. "Особливості проектування цифрових пристроїв на базі FPGA Xilinx в САПР Vivado HLx Design Suite". Thesis, ХНУРЕ, 2019. http://openarchive.nure.ua/handle/document/7923.

Full text
Abstract:
The new generation of CAD Vivado HLx Design Suite is designed to assist developers in solving the problem - the high complexity of obtaining FPGA tracing with a volume of hundreds of thousands and millions of logic cells in a reasonable time frame and with high quality.
APA, Harvard, Vancouver, ISO, and other styles
45

Quesenberry, Joshua Daniel. "Communication Synthesis for MIMO Decoder Matrices." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/51149.

Full text
Abstract:
The design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom hardware design language and communication synthesis. The framework is designed to optimize performance with matrix-type mathematical operations. The largest matrices used in this process are 4x4 matrices. The primary example modeled in this work is MIMO decoding. Making this possible are 16 functional unit containers within the framework, with generalized interfaces, which can hold custom user hardware and IP cores. <p> This framework, which
APA, Harvard, Vancouver, ISO, and other styles
46

Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-191286.

Full text
Abstract:
Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfig
APA, Harvard, Vancouver, ISO, and other styles
47

Tsakiris, Nicholas, and n. tsakiris@internode on net. "Enabling Gigabit IP for Embedded Systems." Flinders University. Computer Science, Engineering and Mathematics, 2009. http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821.

Full text
Abstract:
For any practical implementation of chip design, there needs to be a hardware platform available for the purpose of prototyping and implementation of FPGA-based programs, whether they are written in VHDL or Verilog. Communication between the platform and a computer is a useful feature of many hardware solutions as it allows for the capability of regular data transmission between the two devices. Furthermore, the ability to communicate between the platform and a computer at high-speeds requires a specially constructed interface, one that can be modified by the designer at their choosing. There
APA, Harvard, Vancouver, ISO, and other styles
48

Couch, Jacob Donald. "Applications of TORC: An Open Toolkit for Reconfigurable Computing." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/34624.

Full text
Abstract:
Two research projects are proposed that rely on Tools for open Reconfigurable Computing (TORC) and the openness of the Xilinx tool chain. The first project, the Embedded FPGA Transmitter, relies on the ability to add arbitrary routes to a physical FPGA which serve no obvious purpose. These routes can then mimic an antenna and transmit directly from the FPGA. This mechanism is not supported utilizing standard hardware description languages; however, the Embedded FPGA Transmitter requires measurements on a real FPGA to determine success. The second project is a back-end tools accelerator desi
APA, Harvard, Vancouver, ISO, and other styles
49

Steiner, Neil Joseph. "A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/35014.

Full text
Abstract:
Modern FPGAs contain routing resources easily exceeding millions of wires. While mainstream design flows and place-and-route tools make very good use of these routing resources, they do so at the cost of very significant processing time. A well established alternative scheme is to modify or generate configuration bitstreams directly, resulting in more dynamic designs and shorter processing times. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to the JBits API. The databases ca
APA, Harvard, Vancouver, ISO, and other styles
50

Chaubal, Aditya Prakash. "Design and Implementation of an FPGA-based Partially Reconfigurable Network Controller." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/10098.

Full text
Abstract:
There is currently a strong trend towards embedding Internet capabilities into electronics and everyday appliances. Most network controllers used in small appliances or for specialized purposes are built using micro controllers. However there are many applications where a hardware-oriented approach using Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) is more suitable. One of the features of FPGAs that cannot be integrated into ASICs is runtime reconfiguration in which, certain portions of the chip are reconfigured at runtime while the other parts con
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the bibliographies on the topic 'Xilinx' for other source types:
Journal articles Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography