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Journal articles on the topic 'Xilinx'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Tyler, Neil. "Xilinx Unveils Versal." New Electronics 51, no. 18 (2018): 9. http://dx.doi.org/10.12968/s0047-9624(23)60681-9.

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2

Tyler, Neil. "Xilinx Unveils Unified Software Platform." New Electronics 51, no. 18 (2019): 7. http://dx.doi.org/10.12968/s0047-9624(22)61426-3.

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3

Tyler, Neil. "Xilinx Unveils Adaptable Accelerator Card." New Electronics 52, no. 15 (2019): 9. http://dx.doi.org/10.12968/s0047-9624(22)61404-4.

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4

Tyler, Neil. "Xilinx Unveils Space-Grade FPGA." New Electronics 53, no. 10 (2020): 7. http://dx.doi.org/10.12968/s0047-9624(22)61249-5.

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5

Anthony Prathap, Joseph, T. S.Anandhi, K. Ramash Kumar, and B. Srikanth. "Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA." International Journal of Engineering & Technology 7, no. 2.8 (2018): 570. http://dx.doi.org/10.14419/ijet.v7i2.8.10523.

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This paper proposes the design of 64-Quadrature Amplitude Modulation using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and XILINX SPARTAN Field Programmable Gate Array (FPGA) real-time implementation for validation. QAM is used in modern digital communication applications like set-top box, satellite TV, wireless and cellular technology etc. In this paper, 64-QAM is implemented and compared with three different XILINX SPARTAN FPGA devices say 3A DSP, 3E and 6E. The power, current and thermal parameters are performed and compared. The power consumed for the

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6

Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse

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7

Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

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<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switchi

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8

R., Palanisamy, S. Boopathi C., Selvakumar K., and Vijayakumar K. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1722–27. https://doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse

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9

Тарасов, И. "АРХИТЕКТУРА И ОБЛАСТИ ПРИМЕНЕНИЯ ПЛИС XILINX VERSAL". ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 211, № 10 (2021): 136–40. http://dx.doi.org/10.22184/1992-4178.2021.211.10.136.140.

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Рассмотрены ПЛИС Xilinx Versal. Отмечено, что их особенностью является добавление на кристалл матрицы процессоров с архитектурой VLIW. Приведена информация об архитектуре, характеристиках и областях применения ПЛИС Xilinx Versal.

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10

ADHYANA, GUPTA. "HARDWARE SOFTWARE CO-SIMULATION FOR TRAFFIC LOAD COMPUTATION USING MATLAB SIMULINK MODEL BLOCKSET." International Journal of Computational Science and Information Technology (IJCSITY) 1, May (2013): 1–12. https://doi.org/10.5281/zenodo.3597180.

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<strong>ABSTRACT</strong> Due to increase in number of vehicles, Traffic is a major problem faced in urban areas throughout the world. This document presents a newly developed Matlab Simulink model to compute traffic load for real time traffic signal control. Signal processing, video and image processing and Xilinx Blockset have been extensively used for traffic load computation. The approach used is Edge detection operation, wherein, Edges are extracted to identify the number of vehicles. The developed model computes the results with greater degrees of accuracy and is capable of being used to

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11

Anusha D, Anusha D., and Swathi G. Swathi G. "Fast pipelined AES algorithm implemented on Xilinx FPGAsFast pipelined AES algorithm implemented on Xilinx FPGAs." International Journal of Scientific Research 2, no. 7 (2012): 159–62. http://dx.doi.org/10.15373/22778179/july2013/54.

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12

Aseeri, Mohammed A., and Mohamed I. Sobhy. "Design Chaotic Generator at High Frequencies." Greener Journal of Science, Engineering and Technological Research 3, no. 7 (2013): 205–9. https://doi.org/10.15580/gjsetr.2013.7.021213447.

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In this paper, we introduce a new method to implement chaotic generators based on Henon map chaotic system given by the state equations by using Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools, Leonardo spectrum or Synplicity Synplify and ModelSim XE PLUSE. The toolbox of the Xilinx System Generator used as toolbox under the MATLAB® Simulink toolbox to convert any MATLAB® Simulink model to the Xilinx System Generator model

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13

Shkil, Oleksandr, Inna Filipenko, Anatolii Miroshnyk, and Valentyn Kornienko. "Analysis of the effectiveness of using specialized computing modules and libraries when implementing digital signal processing algorithms on the platform SoC." Bulletin of the National Technical University "KhPI" A series of "Information and Modeling" 1, no. 1 (13) (2025): 112–28. https://doi.org/10.20998/2411-0558.2025.01.08.

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The implementation of the Fast Fourier Transform (FFT) algorithm on the Xilinx ZYNQ-7000 SoC system-on-chip technology platform is considered. The time and hardware costs for implementing the FFT algorithm for different options for its length on the PS part of the SoC using specialized libraries and the implementation of this algorithm on the PL part of the SoC using the IP-core from the Xilinx repository are compared. The implementation of the FFT algorithm is performed in the C programming language using the Vivado/Vitis tools. The best performance among different ways to implement the FFT a

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14

Yu, Hoyoung, Hansol Lee, Sangil Lee, Youngmin Kim, and Hyung-Min Lee. "Recent Advances in FPGA Reverse Engineering." Electronics 7, no. 10 (2018): 246. http://dx.doi.org/10.3390/electronics7100246.

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In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers su

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ILES, G., J. Jones, and A. Rose. "Experience powering Xilinx Virtex-7 FPGAs." Journal of Instrumentation 8, no. 12 (2013): C12037. http://dx.doi.org/10.1088/1748-0221/8/12/c12037.

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16

Giordano, Raffaele, Dario Barbieri, Sabrina Perrella, Roberto Catalano, and Giuliana Milluzzo. "Configuration Self-Repair in Xilinx FPGAs." IEEE Transactions on Nuclear Science 65, no. 10 (2018): 2691–98. http://dx.doi.org/10.1109/tns.2018.2868992.

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17

Тарасов, И. "Применение ПЛИС класса «система на кристалле» Xilinx Zynq и подходы к проектированию на основе языков описания аппаратуры высокого уровня". ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 185, № 4 (2019): 62–66. http://dx.doi.org/10.22184/1992-4178.2019.185.4.62.66.

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Рассмотрены возможности существующих и перспективных семейств программируемых логических интегральных схем компании Xilinx с архитектурой «система на кристалле», а также предпочтительные подходы к проектированию цифровых систем под управлением процессоров на основе САПР Xilinx Vivado HLS.

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18

Wilkinson, Brett R., and Tracy J. Noga. "Xilinx, Stock Option Pricing, and the Meaning of Arm's Length." ATA Journal of Legal Tax Research 9, no. 1 (2011): 50–63. http://dx.doi.org/10.2308/jltr-50103.

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ABSTRACT In this paper, we examine the controversy surrounding the Xilinx case and explore what the case means for the future of transfer pricing. Although the IRS acquiesced in the Xilinx result, it expressly disagreed with the reasoning and asserted that the issue is now moot due to the application of the 2009 regulations. In sharp contrast, multiple commentators have expressed the view that the Xilinx result might in fact render the 2009 regulations invalid. For this reason, it is apparent that significant uncertainty continues to surround the central issues in Xilinx, namely, the way that

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19

R., Palanisamy, and Vijayakumar K. "Switching pulse generation for DC-DC boost converter using xilinx-ISE with FPGA processor." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 81–85. https://doi.org/10.11591/ijres.v8.i2.pp81-85.

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This paper explains steps to generate switching pulse using XilinxISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for DC-DC boost converter using Xilinx-ISE and matlabsimulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse ge

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20

Tyler, Neil. "Xilinx and Daimler to Develop AI Solutions." New Electronics 52, no. 11 (2018): 8. http://dx.doi.org/10.12968/s0047-9624(23)60326-8.

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21

Baans, Omar Salem, and Asral Bahari Jambek. "Implementation of an ARM-based system using a Xilinx ZYNQ SoC." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 485. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp485-491.

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<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

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22

Aggarwal, Anurag, Astha Satija, and Tushar Nagpal. "FIR Filter Designing using Xilinx System Generator." International Journal of Computer Applications 68, no. 11 (2013): 37–41. http://dx.doi.org/10.5120/11625-7096.

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23

Huang, Xin Hua, Hui Wen Liu, and Lv Su Ye. "Visualization Spectrometer Based on Refit Xilinx FPGA." Applied Mechanics and Materials 427-429 (September 2013): 755–58. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.755.

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The spectrometer is a basic tool of optical measurement, having a wide application field. Because of its small visual range and used in a dark environment, traditional spectrometer cause eye fatigue, inconvenient in reading figure and its utilization rate is low. In order to solve these problems, I utilize Xilinx FPGA and CCD to retrofit the traditional spectrometer. Making the image which in the eyepiece shown on the displayer, realize the goal of Digital Angle measurement. The new design spectrometer has the advantage of operate simply, convenient maintenance, etc.

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24

Cheremisinov, D. I. "Protecting intellectual property in FPGA Xilinx design." Prikladnaya diskretnaya matematika, no. 24 (June 1, 2014): 110–18. http://dx.doi.org/10.17223/20710410/24/10.

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25

Hauck, S., Zhiyuan Li, and E. Schwabe. "Configuration compression for the Xilinx XC6200 FPGA." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, no. 8 (1999): 1107–13. http://dx.doi.org/10.1109/43.775631.

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26

Quinn, Heather, Paul Graham, Keith Morgan, et al. "Flight Experience of the Xilinx Virtex-4." IEEE Transactions on Nuclear Science 60, no. 4 (2013): 2682–90. http://dx.doi.org/10.1109/tns.2013.2246581.

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27

Popa, Rustem. "B12: Evolvable hardware in Xilinx XCR3064 CPLD." IFAC Proceedings Volumes 37, no. 20 (2004): 232–37. http://dx.doi.org/10.1016/s1474-6670(17)30602-x.

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28

Su, Jie. "Spectrum Test System Based on XILINX FPGA." Academic Journal of Science and Technology 5, no. 1 (2023): 196–204. http://dx.doi.org/10.54097/ajst.v5i1.5632.

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Gaussian channel is a radio frequency communication channel, which contains the characteristics of specific noise spectral density of various frequencies, resulting in arbitrary distribution of errors in the channel. Gaussian channel, often referred to as weighted Gaussian white noise (AWGN) channel. This noise assumes that the power spectral density (PSD) is constant over the entire channel bandwidth, and the amplitude conforms to the Gaussian probability distribution. The system takes the system generator as the development platform, combines matlab with the modern communication comprehensiv

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29

Alidoust Aghdam, Farid, and Siamak Saeidi Haghi. "Implementation of High Performance Microstepping Driver Using FPGA with the Aim of Realizing Accurate Control on a Linear Motion System." Chinese Journal of Engineering 2013 (December 18, 2013): 1–8. http://dx.doi.org/10.1155/2013/425093.

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This paper presents an FPGA-based microstepping driver which drives a linear motion system with a smooth and precise way. Proposed driver built on a Spartan3 FPGA (XC3S400 core) development board from Xilinx. Implementation of driver realized by an FPGA and using Verilog hardware description language in the Xilinx ISE environment. The driver’s control behavior can be adapted just by altering Verilog scripts. In addition, a linear motion system developed (with 4 mm movement per motor revolution) and coupled it to the stepper motor. The performance of the driver is tested by measuring the distan

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Raj Koti D, Raj Koti D., and Manoj Varma P. Manoj Varma P. "Fast Pipelined Aes Algorithm Implemented on Xilinx Fpgas." International Journal of Scientific Research 2, no. 10 (2012): 1–4. http://dx.doi.org/10.15373/22778179/oct2013/40.

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31

P Lavanya Kumari, N. "Design of Xilinx based Telemetry System using Verilog." International Journal of Scientific Engineering and Research 2, no. 3 (2014): 135–39. https://doi.org/10.70729/j2013185.

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32

Salah, Mahi Mohamed, and Abdelfatah Nasri. "Development of a DC motor control system by Xilinx system generator." STUDIES IN ENGINEERING AND EXACT SCIENCES 5, no. 2 (2024): e11534. https://doi.org/10.54021/seesv5n2-623.

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This study introduces a numerical approach utilizing a Xilinx System Generator to develop a DC motor control system, showcasing a significant ability to regulate and enhance motor speed. We developed the proposed system in the MATLAB/SIMULINK environment, utilizing a collection of blocks generated by the Xilinx System Generator. We developed and simulated a proportional-integral (PI) controller and pulse width modulation (PWM). Subsequent to simulation, we can transfer the HDL code from the Xilinx System Generator block to a Field Programmable Gate Array (FPGA) board using Vivado. The system c

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33

Zulfikar, Zulfikar, Shuja A. Abbasi, and Abdulrahman M. Alamoud. "FPGA Realizations of Walsh Transforms for Different Transform and Word lengths into Xilinx and Altera Chips." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4981. http://dx.doi.org/10.11591/ijece.v8i6.pp4981-4994.

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This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA rea

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34

Choi, Soyeon, and Hoyoung Yoo. "Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA." Electronics 9, no. 7 (2020): 1132. http://dx.doi.org/10.3390/electronics9071132.

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This paper presents a fast method to extract logic functions of look-up tables (LUTs) from a bitstream in Xilinx FPGAs. In general, FPGAs utilize LUTs as a primary resource to realize a logic function, and a typical N-input LUT comprises 2N 1-bit SRAM and N – 1 multiplexers. Whereas the previous research demands 2N exhaustive processing to find a mapping rule between an LUT and a bitstream, the proposed method decreases the processing to 2N by eliminating unnecessary processing. Experimental results show that the proposed method can reduce reversing time by more than 57% and 85% for Xilinx Spa

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35

Krim, Saber, Soufien Gdaim, Abdellatif Mtibaa, and Mohamed Faouzi Mimouni. "FPGA-Based Implementation Direct Torque Control of Induction Motor." International Journal of Power Electronics and Drive Systems (IJPEDS) 5, no. 3 (2015): 293. http://dx.doi.org/10.11591/ijpeds.v5.i3.pp293-304.

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<p>This paper proposes a digital implementation of the direct torque control (DTC) of an Induction Motor (IM) with an observation strategy on the Field Programmable Gate Array (FPGA). The hardware solution based on the FPGA is caracterised by fast processing speed due to the parallel processing. In this study the FPGA is used to overcome the limitation of the software solutions (Digital Signal Processor (DSP) and Microcontroller). Also, the DTC of IM has many drawbacks such as for example; The open loop pure integration has from the problems of integration especially at the low speed and

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36

Muslim, Imaduddin Amrullah, R. Rizal Isnanto, and Eko Didik Widianto. "Perancangan dan Implementasi Algoritma DES untuk Mikroprosesor Enkripsi dan Dekripsi pada FPGA." Jurnal Teknologi dan Sistem Komputer 3, no. 2 (2015): 259. http://dx.doi.org/10.14710/jtsiskom.3.2.2015.259-266.

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Seiring dengan semakin luasnya penerapan teknologi komputasi di sekitar kita, menjadikan informasi menjadi sangat mudah dan cepat untuk disebarkan. Kita dapat mengakses informasi dan data-data yang kita butuhkan dengan mudah. Namun permasalahan yang kita hadapi saat ini kerhasiaan informasi menjadi sangat riskan. Oleh karena itu Sistem keamanan merupakan hal penting yang perlu diperhatikan dalam mengembangkan suatu sistem komputer hal ini lah yang menjadikan enkripsi dan dekripsi data menjadi hal yang penting. Modul rancangan IP Core ini dirancang menggunakan aplikasi Xilinx ISE Design Suite 1

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Rivera-Ordoñez, Cesar, Jhon Jairo Santiago, and Julián Ferreira-Jaimes. "Reconocimiento de caracteres por medio de una red neuronal artificial." Respuestas 14, no. 1 (2016): 30–39. http://dx.doi.org/10.22463/0122820x.523.

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En este trabajo se presenta la implementación de un sistema de reconocimientode caracteres en una tarjeta de desarrollo FPGA de propósito general. La clasificación de los caracteres se realiza por medio de un modelo de red neuronal conocido como Feed-forward backpropagation. Se utiliza la herramienta de redes neuronales NNTool de Matlab, para crear, entrenar y simular este tipo de Red Neuronal Artificial (RNA) con cinco diferentes patrones de entrenamiento. Para realizar la implementación, estas RNAs, son traducidas del modelo computacional a un modelo realizable en hardware, el cual es descri

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Rejab Khalil, Mazin, and Rafal Taha Mahmood. "Designing of Soft Core Processor System with Direct Memory Access (DMA) Mode." University of Thi-Qar Journal for Engineering Sciences 6, no. 2 (2015): 53–64. http://dx.doi.org/10.31663/utjes.v6i2.74.

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A soft core processor system is constructed using embedded design techniques and it is configured on Field Programmable Gate Arrays (FPGAs). The system is accommodated to act with Direct Memory Access (DMA) mode using suitable Xilinx Intellectual Property (IP) core. A dual data rate synchronous dynamic random access memory (DDR_SDRAM) with 64 Mbyte capacity is introduced to the system and accessed by the DMA controller.The controller is performed to transfer programmable quantity of data from source address to destination address without intervention of the processor. Spartan-3E slice is used

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39

Slimani, M., K. Benkalaia, and L. Naviner. "Analysis of ageing effects on ARTIX7 XILINX FPGA." Microelectronics Reliability 76-77 (September 2017): 168–73. http://dx.doi.org/10.1016/j.microrel.2017.07.006.

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40

Kasper, Markus, Timo Kasper, Amir Moradi, and Christof Paar. "Praktische Angriffe auf die Bitstromverschlüsselung von Xilinx FPGAs." Datenschutz und Datensicherheit - DuD 35, no. 11 (2011): 779–85. http://dx.doi.org/10.1007/s11623-011-0185-9.

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41

Leavy, Brian. "Innovation at Xilinx: a senior operating manager's view." Strategy & Leadership 33, no. 4 (2005): 33–37. http://dx.doi.org/10.1108/10878570510608022.

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42

Cunţan, C. D., I. Baciu, and C. M. Diniș. "Xilinx implementation of a serial-parallel digital converter." IOP Conference Series: Materials Science and Engineering 477 (February 18, 2019): 012035. http://dx.doi.org/10.1088/1757-899x/477/1/012035.

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43

Frikha, Tarek, Nader Ben Amor, Jean-Philippe Diguet, and Mohamed Abid. "A novel Xilinx-based architecture for 3D-graphics." Multimedia Tools and Applications 78, no. 11 (2018): 14947–70. http://dx.doi.org/10.1007/s11042-018-6886-4.

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44

Giordano, Raffaele, Dario Barbieri, Sabrina Perrella, and Roberto Catalano. "Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs." Instruments 3, no. 4 (2019): 56. http://dx.doi.org/10.3390/instruments3040056.

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The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration. These effects may alter the functionality until the next reconfiguration of the device. In this work, we present the radiation testing of a high-speed serial link hardened by a new, custom scrubber designed for Xilinx FPGAs. We compared the performance of our scrubber to the Xilinx Single Event Mitigation (SEM) controller and we measured the impact of the scrubbers on the reliability of the link. Our re

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45

Salem, Eman, Abdelhalim Zekry, Hossam Labeb, and Radwa Tawfik. "FPGA implementation of 1000base-x Ethernet physical layer core." International Journal of Engineering & Technology 7, no. 4 (2018): 2106. http://dx.doi.org/10.14419/ijet.v7i4.13469.

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This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

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SALEH, ANDHI RACHMAN, and SUNNY ARIEF SUDIRO. "CRC 8-bit Encoder-Decoder Component in FPGA using VHDL." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, no. 1 (2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

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AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Networ

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Lounici, Mer Wan, and Xiao Ming Luan. "Implementation of Unitary Music Algorithm Using Xilinx System Generator." Advanced Materials Research 748 (August 2013): 629–33. http://dx.doi.org/10.4028/www.scientific.net/amr.748.629.

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The MUltiple SIgnal Classification MUSIC algorithm is a kind of DOA (Direction Of Arrival) estimation technique based on eigenvalue decomposition, which is also called subspace-based method [5]. In addition of its super resolution capability, MUSIC is very suitable for integration on logic circuit devices such as FPGAs (Field Programmable Gate Array).this paper proposes an implementation of unitary MUSIC algorithm using Xilinx System Generator (XSG). The design proposed uses CORDIC (COordinate Rotation DIgital Computer) -based Triangular Systolic Array for QR- decomposition to deal with EVD (e

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Hitt, D. "Xilinx strategy is to move faster to an adaptable intelligent world." ELECTRONICS: Science, Technology, Business 175, no. 4 (2018): 84–87. http://dx.doi.org/10.22184/1992-4178.2018.175.4.84.87.

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Kadam, Sarika, and S. D. Mali. "DESIGN OF RISC PROCESSOR USING VHDL." International Journal of Research -GRANTHAALAYAH 4, no. 6 (2016): 131–38. http://dx.doi.org/10.29121/granthaalayah.v4.i6.2016.2646.

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The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions are designed for this processors. Multiplier is also designed using ADD instruction. Proposed instructions are simulated using Xilinx ISE 13.1i. The processor is synthesized using Spartan-3A XC3S50A XILINX Tool.

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M S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23809.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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