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Relevant bibliographies by topics / Xnor gate

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Academic literature on the topic 'Xnor gate'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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Journal articles on the topic "Xnor gate"

1

Haponchyk, R. V., I. Yu Tatsenko, V. V. Vitko, A. A. Stashkevich, T. Goto, and A. B. Ustinov. "Investigation of a Nonlinear XNOR Logic Gate Based on an Induced Nonlinear Phase Shift of Spin Waves." Journal of the Russian Universities. Radioelectronics 26, no. 6 (2023): 54–63. http://dx.doi.org/10.32603/1993-8985-2023-26-6-54-63.

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Introduction. Recent years have seen a growing interest in studying the nonlinear properties of spin waves. Nonlinear phenomena, such as envelope solitons, nonlinear frequency shifts of intense spin waves, and etc., have attracted particular attention. However, a number of important issues remain to be underexplored, including the problem of induced nonlinear phase shift of spin waves. The relevance of this problem is related to the need to develop spin-wave logic gates that could be controlled by changing the spin wave phase.Aim. To study a nonlinear XNOR logic gate whose operation is based o

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Thakur, Dolly, and Hemant Patidar. "LITERATURE SURVEY ON AREA OPTIMIZATION OF CMOS FULL ADDER DESIGN." ICTACT Journal on Microelectronics 7, no. 4 (2022): 1241–44. https://doi.org/10.21917/ijme.2022.0213.

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In this paper, a novel architecture for a dynamic logic-based full adder is introduced and analyzed. In full adder architecture, the XOR and XNOR gates are commonly employed as basic logic units. In the report, improved XOR and XNOR logic gate topologies are employed to produce a full adder circuit. The envisioned XOR/XNOR gate architecture has a full logic cycle. The suggested adder design is modelled using a traditional 180 nm CMOS technique. The simulated outcomes using the SPICE simulation tool demonstrated that the proposed network has significant advantages in energy loss and efficiency

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Challa, Lakshmi jyothi, and Hanumantha Rao S. "Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9, no. 12 (2020): 323–28. https://doi.org/10.35940/ijitee.L7992.1091220.

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VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases th

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Mustapha, Muhazam, Jeffery Lee, Anis Shahida Niza Mokhtar, Kamarul ‘Asyikin Mustafa, and Bakhtiar Affendi Rosdi. "A Method of Realizing XOR/XNOR Gate using Symmetric Boolean Function Lattice Structure." Jurnal Kejuruteraan si4, no. 2 (2021): 85–92. http://dx.doi.org/10.17576/jkukm-2021-si4(2)-13.

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The current CMOS’s industry standard XOR and XNOR gate consist of 12 and 10 transistors, respectively. This transistor count could be lowered down to produce low power circuits as XOR/XNOR are extensively used in many functional modules. As a solution, a method for realizing low transistor count XOR/XNOR gates using a special property of symmetric Boolean function is proposed. This property suggests that the circuits for such functions can be realized with fewer transistors using a special lattice structure circuit. Modifications are made to the original lattice structure to match with the cur

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Kotb, Amer. "Performance of All-Optical XNOR Gate Based on Two-Photon Absorption in Semiconductor Optical Amplifiers." Advances in Optical Technologies 2014 (December 31, 2014): 1–6. http://dx.doi.org/10.1155/2014/754713.

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All-optical logic XNOR gate is realized by a series combination of XOR and INVERT gates. This Boolean function is realized by using Mach-Zehnder interferometers (MZIs) and exploiting the nonlinear effect of two-photon absorption (TPA) in semiconductor optical amplifiers (SOAs). The employed model takes into account the impact of amplified spontaneous emission (ASE), input pulse energy, pulsewidth, SOAs carrier lifetime, and linewidth enhancement factor (α-factor) on the gate’s output quality factor (Q-factor). The outcome of this study shows that the all-optical XNOR gate is indeed feasible wi

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Al-Sabea, Z. S., A. A. Ibrahim, and S. H. Abdulnabi. "Plasmonic Logic Gates at Optimum Optical Communications Wavelength." Advanced Electromagnetics 11, no. 4 (2022): 10–21. http://dx.doi.org/10.7716/aem.v11i4.1894.

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This paper displays a design that realizes all optical logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and consisting of one nanoring and four strips Operates on the principle of resonance. the proposed design works at the wavelength of 1550 nm using insulator-metal-insulator (IMI) plasmonic waveguide. The basic principle of the operation of these gates is input and control signals’ constructive and destructive interference. The proposed transmission threshold’s value is 0.25 between OFF state and ON state. The proposed design has small dimensions (300 nm × 300 nm) and can realize seven logic

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Kumudha, G., and B. Ramesh K. "High Speed Gate Level Synchronous Full Adder Designs." Journal of VLSI Design and its Advancement 4, no. 3 (2022): 1–11. https://doi.org/10.5281/zenodo.6344095.

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<em>Digital computer systems are built on the foundation of addition. This paper presents three innovative gate level complete adder designs based on the elements of a conventional cell library: one using XNOR and multiplexer gates (XNM), another using XNOR, AND, Inverter, multiplexer, and complex gates (XNAIMC), and a third using XOR, AND, and complex gates (XAC). Many other existing gate level full adder realizations have been used to make comparisons. In view of broad simulations with a 32-bit carry-ripple adder execution focusing on three cycle, voltage, and temperature (PVT) corners of th

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Yang, Liu, Yuqi Wang, Zhiru Wu, and Xiaoyuan Wang. "FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design." Micromachines 12, no. 11 (2021): 1344. http://dx.doi.org/10.3390/mi12111344.

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In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has distinct advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

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Meghana, Madabhushi Sai. "Low Power and Fast Full Adder by Exploring New XOR and XNOR Gates." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 1956–63. http://dx.doi.org/10.22214/ijraset.2021.35286.

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In this project, novel circuits for FULL ADDER are proposed using new XOR or XNOR gates. The conventional design of XOR or XNOR gates shows that the not gate in the schematic has drawbacks. So by investigating advanced XOR or XNOR gates we proposed the schematic design. The proposed schematics are optimized in terms of speed, delay, power and power delay product. We developed six novel hybrid full adder schematics based on exploring new XOR or XNOR gates. Each designed schematics have their specifications of energy consumption, delay, power delay product. To simulate the performance of the pro

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Upadhyay, Rahul Mani, R. K. Chauhan, and Manish Kumar. "Energy Efficient 4-2 and 5-2 Compressor for Low Power Computing." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 12, no. 1 (2023): e30381. http://dx.doi.org/10.14201/adcaij.30381.

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The rising use of multimedia devices, power management has become a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits can be used to construct the suggested compressor design. The performance of proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be space and power economical. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal

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Book chapters on the topic "Xnor gate"

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Awasthi, Shashank, Sanjeev Kumar Metya, and Alak Majumder. "MZI-Based Electro-optic Reversible XNOR/XOR Derived from Modified Fredkin Gate." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1520-8_8.

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Dutta, Siddhartha, Kousik Mukherjee, and Subhasish Roy. "Analysis of All-Optical XNOR Gate Using Quantum Dot Semiconductor Optical Amplifier (QDSOA)." In Lecture Notes in Electrical Engineering. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-9154-6_12.

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Jadon, Ekta, and Shyam Akashe. "For Enhancing the Performance in Single Bit Hybrid Full Adder Circuits Using XNOR Gate." In Communications in Computer and Information Science. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-8896-6_26.

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Nguyen, Thi Hong Loan, Duy Tien Le, Anh Tuan Nguyen, Le Minh Duong, and Trung Thanh Le. "All-Optical XNOR and XOR Logic Gates Based on Ultra-Compact Multimode Interference Couplers Using Silicon Hybrid Plasmonic Waveguides." In Lecture Notes in Electrical Engineering. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0390-8_135.

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Surya Prakash, S., Sneha M. Joseph, D. Kishore, and Y. Yamini Devi. "Stochastic Computing Solutions Challenges and Application." In Advances in Transdisciplinary Engineering. IOS Press, 2023. http://dx.doi.org/10.3233/atde221239.

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High speed and power are required for modern applications, and low power consumption and a small integration area. So, this system will be consumed less power. To manipulate these problems either way of computing should be changed by another technique or the transistor should be changed by another device. One selective computing is stochastic. While loaded computing contributes high hardware cost, high speed. Stochastic computing accuracy is less than binary computing circuits. They are having some implementation basic operations of stochastic computing. They are complementary operation, multi

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ji, Sheeba, and Mohd Nafees. "AN INTRODUCTORY OVERVIEW: FUNDAMENTALS OF LOGIC GATES." In EMERGING TRENDS IN CLOUD SECURITY AND INTELLIGENT AGENTS. GRF Books, 2023. http://dx.doi.org/10.52458/9788196869434.2023.eb.grf.ch-15.

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A fundamental building component that applies a particular logical operation to one or more binary input signals (0 or 1) to produce a binary output in the context of computer science and digital electronics. These gates serve as the building blocks of digital circuitry and are used to design intricate digital systems. They are depicted using symbolic logic notations. In the ever-evolving landscape of digital technology, logic gates stand as the fundamental components that breathe life into the binary world of ones and zeros. They are the elemental logic operators that enable the transformatio

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Sharma, Uma, Tukur Gupta, and Neeti Bansal. "Cutting-Edge Methodologies for Low Power Design in VLSI Circuits." In Exploring the Intricacies of Digital and Analog VLSI. IGI Global, 2025. https://doi.org/10.4018/979-8-3693-8084-0.ch002.

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The rapid advancements in Very Large Scale Integration (VLSI) technology have been driven by the increasing demand for high-performance and energy-efficient electronic devices. Low power design has emerged as a critical focus area in modern electronic systems to address these demands. The chapter categorizes design approaches into conventional methods, such as static and dynamic CMOS technologies, and non-conventional techniques, including FinFET, Carbon Nanotube Field Effect Transistors (CNTFET), and Floating Gate MOSFET (FGMOS). A comparative analysis of XOR/XNOR circuits highlights their de

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"All-Optical Logic XOR/XNOR Gates." In Nanophotonics. Jenny Stanford Publishing, 2013. http://dx.doi.org/10.1201/b17233-13.

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Conference papers on the topic "Xnor gate"

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Rodriguez Vázquez, Edmundo E., and Eduardo Tepichin-Rodríguez. "Digital holographic XNOR multi-gate (DHMG-XNOR)." In Optical Engineering + Applications, edited by Abdul A. S. Awwal, Khan M. Iftekharuddin, and Bahram Javidi. SPIE, 2008. http://dx.doi.org/10.1117/12.787442.

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Jeong, J. M., and M. E. Marhic. "All-optical logic gates based on cross-phase modulation in a nonlinear fiber interferometer." In Nonlinear Guided-Wave Phenomena. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/nlgwp.1991.wa3.

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All-optical logic gates have been demonstrated using nonlinear waveguide devices. In such devices, optical fibers are increasingly used, since their optical Kerr effect is very fast, and their low-loss waveguide structure allows a long interaction length and relatively low power. For example, an AND gate based on intensity-dependent polarization rotation [1], XOR and AND gates based on soliton trapping [2], a NOR gate based on soliton dragging [3], and AND, NOT, XOR, and XNOR gates [4] have been demonstrated in polarization-maintaining fibers.

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Johnson, K. M., and G. Moddel. "Optical logic gates using photoaddressed ferroelectric liquid crystals." In OSA Annual Meeting. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/oam.1987.tuf4.

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The implementation of polarization-based optical logic using low-cost, low-power, and high-speed ferroelectric liquid crystals (FLCs) has been previously described.1 In particular, the XOR and XNOR Boolean functions are easily built by cascading in series two electrically addressed FLO devices.1,2 The AND and OR operations, however, require parallel combinations of liquid crystals, polarizers, analyzers, mirrors, and in some cases photodetectors.2,3 These schemes are cumbersome because they require twice the optical components and space to build compared to cascadable logic gates. We present a

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Rakshit, J. K., J. N. Roy, and T. Chattopadhyay. "All-optical XOR/XNOR logic gate using micro-ring resonators." In 2012 International Conference on Computers and Devices for Communication (CODEC). IEEE, 2012. http://dx.doi.org/10.1109/codec.2012.6509327.

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Rashmi S.B and Veena Oli. "32 bit power efficient carry select adder using 4T XNOR gate." In 2016 2nd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT). IEEE, 2016. http://dx.doi.org/10.1109/icatcct.2016.7912009.

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Verma, Preeti, and Ajay K. Sharma. "Design and Analysis of Groundless XNOR Gate topology in 90nm Technology." In 2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT). IEEE, 2022. http://dx.doi.org/10.1109/gcat55367.2022.9971902.

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Raja, A., K. Mukherjee, and J. N. Roy. "Analysis of All-Optical XNOR Gate in SOA Based Tree-Net Architecture." In 2020 IEEE VLSI Device Circuit and System (VLSI DCS). IEEE, 2020. http://dx.doi.org/10.1109/vlsidcs47293.2020.9179744.

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Sharma, Nishtha, Andrew Marshall, and Jonathan Bird. "Verilog — A compact model of a ME-MTJ based XNOR/NOR gate." In 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, 2017. http://dx.doi.org/10.1109/nanoarch.2017.8053716.

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Maji, Kajal, Kousik Mukherjee, and Mrinal Kanti Mandal. "All Optical Logic XNOR Gate Using Dual Control Dual SOA TOAD (DCDSTOAD)." In 2022 IEEE VLSI Device Circuit and System (VLSI DCS). IEEE, 2022. http://dx.doi.org/10.1109/vlsidcs53788.2022.9811448.

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Das, Srikanta, Kankana Debnath, Suman Debnath, Nitish Sinha, and Bishanka Brata Bhowmik. "Re-Configurable Optical XNOR to XOR Gate Based on Silicon Microring Resonator." In 2023 IEEE 3rd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC). IEEE, 2023. http://dx.doi.org/10.1109/aespc59761.2023.10389915.

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