Academic literature on the topic 'Zed board fast fourier transform'
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Journal articles on the topic "Zed board fast fourier transform"
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Shruti, Vinayak Shet, and Vinayak Shet Shruti. "HW/SW Co-Design Implementation on Zedboard." Journal of VLSI Design and its Advancement 2, no. 3 (2020): 1–10. https://doi.org/10.5281/zenodo.3605415.
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<strong><em>ABSTRACT</em></strong> <em>Field Programmable Gate Arrays is an empowering tool for application-oriented methods, provided that a means for rapid prototyping and assessment, as well as algorithm acceleration. Many FPGA dealers have currently started experimenting with embedded processors in their devices, like Xilinx with ARM Cortex A cores, collected with programmable logic cells. These are identified as Programmable System on Chip (PSoC). These ARM cores (embedded in the Processing System or PS) communicate with the programmable logic cells (PL) using ARM standard AXI buses. The hardware setup used in this project is Zedboard along with AD- FMCOMMS2-EBZ is a high speed analog module which has pre- installed IIO OSCILLOSCOPE and GNU RADIO software. The IIO OSCILLSCOPE Linux Application maintains various slots for real time processing and examining the signals attained from the antennas of the analog module. This demand captures the wanted incoming RF signal in the IIO OSCILLOSCOPE where the whole computation is run on to the PS; although the FPGA cloth keeps on idle during this process. During profiling it was found that the most computational expensive block is Fast Fourier transform (FFT) block that took a longer time to display the output. So to lessen the computation time we transfer the FFT block on to the PL side via AXI buses to communicate to the PS side of the board. Due to the parallel nature of FPGA the capability to calculate large mathematical calculation can be made smoother and in lesser time period.</em>
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Ponomareva, O. V., A. V. Ponomarev, and N. V. Smirnova. "Algorithms for Direct and Inverse Parametric Fast Fourier Transform." Informacionnye Tehnologii 28, no. 1 (2022): 9–19. http://dx.doi.org/10.17587/it.28.9-19.
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Русский Main page New issue Archive of articles Editorial board For the authors Publishing house ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES". No. 1. Vol. 28. 2022 DOI: 10.17587/it.28.9-19 O. V. Ponomareva, Dr. Sc., Tech., Professor, A. V. Ponomarev, PhD, Econ., Associate Professor, Kalashnikov Izhevsk State Technical University, Izhevsk, 426069, Russian Federation, N. V. Smirnova, PhD, Tech., Associate Professor, Sevastopol State University, Sevastopol, 299053, Russian Federation Algorithms for Direct and Inverse Parametric Fast Fourier Transform Classical Fourier processing of finite information discrete signals (FID signals) is the most important method of digital analysis, modeling, optimization, improvement of control and decision making. The theoretical basis of classical Fourier processing of FID signals is the discrete Fourier transform (DFT). The practical basis of classical Fourier processing of FID signals is the Fast Fourier Transform (FFT). The practice of using classical Fourier processing of FID signals, having confirmed its effectiveness, revealed a number of negative effects inherent in this type of digital signal processing (DSP). The aliasing effect, scalloping effect, picket fence effect, significantly affect the effectiveness of analysis, modeling, optimization, improvement of management and decision making. To increase the efficiency of Fourier processing of FID signals, the authors of the paper have developed a generalization of DFT in the form of a parametric DFT (DFT-P). Since the direct application of parametric Fourier processing of FID signals (as well as the use of classical Fourier processing of FID signals) requires complex multiplications, fast procedures are required for the practical implementation of this type of FID signals. Purpose of the research is to develop algorithms for the fast parametric discrete Fourier transform (FFT-P). The work developed fast procedures for the implementation of DFT-P by time decimation. Parametric FFT-P with substitution (in place) and without substitution (no place) are proposed. The estimation of the efficiency of the FFT-P algorithms is given. The practical significance of the work is in the fact that developing algorithms for the parametric fast Fourier transform can reduce the computational costs of performing parametric discrete transformations by three or more orders of magnitude.
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Thohari, Afandi Nur Aziz, and Agfianto Eko Putra. "Rancang Bangun Spectrum Analyzer Menggunakan Fast Fouier Transform Pada Single Board Computer." IJEIS (Indonesian Journal of Electronics and Instrumentation Systems) 7, no. 1 (2017): 71. http://dx.doi.org/10.22146/ijeis.16417.
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Spectrum analyzer is an instrument device to measure the magnitude of the frequency and the power of signal. It has many benefits, such as used for testing telecommunication devices, determining the allocation of unused frequencies and also for practicum in schools or universities. However, because of these many benefits, the price of this signal measuring equipment soared in the market.As an alternative, a device that can serve as spectrum analyzer yet has an affordable price is invented in the form of the prototype of spectrum analyzer built using a single board computer by applying a fast Fourier transform algorithm. Feedback from the prototype is in the form of radio signal captured using RTL-SDR.The test results showed that the range of frequencies that can be displayed by the prototype is 24 MHz to 1.769 MHz. Then the test results of fast Fourier transform computing on N points showed that the prototype can work smoothly using the N from 512 to 32.768 points. The use of N more than 32.768 points will cause CPU and disk memory overloaded and lead to a slow performance. Finally, comparison of the levels of spectrum was performed using spectrum analyzer Anritsu MS2720T. As a result, it is known that prototype can be used to show the location of the frequency spectrum of the radio signal appropriately.
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Yang, Hua, Jun Wu, and Lei Meng Cheng. "Research and Design about a System of Harmonic Detection Based on ARM and HHT." Applied Mechanics and Materials 333-335 (July 2013): 487–91. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.487.
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As we all know FFT(Fast Fourier Transform) can be used analyze and calculate linear and stationary signals, while signals in reality are always nonlinear and transient, so we use HHT(Hilbert-Huang Transform) to detect them. In the past,scholars detect harmonics by applying ARM accompany with FFT. In this article, we use the development board S3C6410-as hardware platform. our processor is ARM, while the main algorithm is HHT.
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L. M. Hassan, S., N. Sulaiman, S. S. Shariffudin, and T. N. T. Yaakub. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (2018): 230–35. http://dx.doi.org/10.11591/eei.v7i2.1167.
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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
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S., L. M. Hassan, Sulaiman N., S. Shariffudin S., and N. T. Yaakub T. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (2018): 230–35. https://doi.org/10.11591/eei.v7i2.1167.
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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-tonoise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
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Pardo, Ehud, and D. K. Cullers. "Design of the fast fourier transform board in the SETI follow-up detection device." Acta Astronautica 42, no. 10-12 (1998): 619–33. http://dx.doi.org/10.1016/s0094-5765(98)00017-4.
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Guaragnella, Cataldo, Agostino Giorgio, and Maria Rizzi. "BFT—Low-Latency Bit-Slice Design of Discrete Fourier Transform." Journal of Low Power Electronics and Applications 13, no. 3 (2023): 45. http://dx.doi.org/10.3390/jlpea13030045.
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Structures for the evaluation of fast Fourier transforms are important components in several signal-processing applications and communication systems. Their capabilities play a key role in the performance enhancement of the whole system in which they are embedded. In this paper, a novel implementation of the discrete Fourier transform is proposed, based on a bit-slice approach and on the exploitation of the input sequence finite word length. Input samples of the sequence to be transformed are split into binary sequences and each one is Fourier transformed using only complex sums. An FPGA-based solution characterized by low latency and low power consumption is designed. Simulations have been carried out, first in the Matlab environment, then emulated in Quartus IDE with Intel. The hardware implementation of the conceived system and the test for the functional accuracy verification have been performed, adopting the DE2-115 development board from Terasic, which is equipped with the Cyclone IV EP4CE115F29C7 FPGA by Intel.
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Vuyets, T. R., and Vladislav A. Ovchinnikov. "Development of a Parallel Fast Fourier Transform-Based Algorithm for Digital Hologram Reconstruction." Advanced Materials Research 1040 (September 2014): 949–53. http://dx.doi.org/10.4028/www.scientific.net/amr.1040.949.
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Digital holography is a comparatively new observation method for micron-sized particles. It is based on numerical reconstruction of recorded interference fringe. Calculation processes for reconstruction are both time- and memory-intensive. The aim of this study was to develop a faster, more efficient algorithm for digital hologram reconstruction. To this purpose Central Processing Unit (CPU) and Graphics Processing Unit (GPU) programming were implemented. For the problem solving the algorithms’ run-time for both configurations was measured. The results showed that the algorithm using a GPU board is faster and more suitable for reconstruction processes. Thus, it makes possible the accomplishment of real-time analysis.
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Jamal, A. Sulisetyono, and W. D. Aryawan. "Direct Measurement of Motion on Fast Ferries." IOP Conference Series: Earth and Environmental Science 1081, no. 1 (2022): 012036. http://dx.doi.org/10.1088/1755-1315/1081/1/012036.
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Abstract This paper describes a new identification method for the fast ferry motions by using the direct measurements on the ship’s board. The inertial sensor type of the Analog Devices (ADIS) 16364 is selected as a as suitable instrument to measure accelerations and velocity of the ship motions namely heave, pitch, and roll in time domain. Furthermore, the ship motion responses are transferred as the energy spectral density in frequency domain which are identified using the Fast Fourier Transform (FFT) method. For the case study, the measurement equipment was placed on the navigation room of MV. Dumai Line 12 recording in 15 minutes within ship voyage from Bengkalis to Batam in September 2021. Finally, the natural frequencies of heave, pitch, and roll motions are identified about 0.568 rad/s, 0.117 rad/s, and 0.227 rad/s, respectively.
Dissertations / Theses on the topic "Zed board fast fourier transform"
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Nouman, Ziad. "Užití programovatelných hradlových polí v systémech průmyslové automatizace." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-234615.
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Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a jejich struktury. Přechodné jevy veličin, jako jsou IG, VGE, VCE během procesu přepínání (zapnutí, vypnutí), mohou poukazovat na degradaci IGBT. Pro měření a monitorování těchto veličin byla navržena nová architektura budiče IGBT. Rychlé měření a monitorování během přepínacího děje vyžaduje vysokou vzorkovací frekvenci. Proto jsou navrhovány paralelní vysokorychlostní AD převodníky (> 50 MSPS). Práce je zaměřena převážně na návrh zařízení s FPGA včetně hardware a software. Byla navržena nová deska plošných spojů s FPGA, která plní požadované funkce, jako je řízení IGBT pomocí vícenásobných paralelních koncových stupňů, monitorování a diagnostiku, a propojení s řídicí jednotkou měniče.
Conference papers on the topic "Zed board fast fourier transform"
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Wang, Junzhen, Yanfeng Shen, Xuezhi Peng, Zhengyang Han, and Shaopeng Jiang. "An Ultra-Compliant and Flexible Structural Sensing Neural System for Damage Detection in Wind Turbine Blades." In ASME 2021 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2021. http://dx.doi.org/10.1115/imece2021-70986.
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Abstract This paper presents a new ultra-compliant and flexible structural sensing neural system for damage detection in wind turbine blades. The entire sensing cluster is integrated inside a flexible printed circuit (FPC), which complies the structural geometric features as a neural skin planted on the structural surfaces. It is worth of noting that the proposed sensing system can be mounted on arbitrary locations of a wind turbine blade, mimicking the neurons of the human biological system to detect and monitor the damage in the blade. Besides, all the sensing elements are interfaced with a laptop-controlled data acquisition board to receive the structural dynamic responses. In addition, a miniature electromagnetic actuator is utilized to excite the blade. Additional mass is employed to simulate the damage situation. Several signal processing techniques are implemented to analyze the oscillatory responses, such as wavelet analysis, fast Fourier transform (FFT), and short time Fourier transform (STFT). Furthermore, the damage indices (DIs) which correlate the structural spectral power density of both pristine and damaged cases can accurately identify the location of damage. Such a sensing neural system possesses the tremendous potential in future Structural Health Monitoring (SHM) and Nondestructive Evaluation (NDE) applications. This paper finishes with discussion, concluding remarks, and suggestions for future work.
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Aspera, France B., Christopher Flores, and Ma Cristina Salvador. "Frequency Domain Imaging: Acoustic Microscopy Technique for Die Stacking Application." In ISTFA 2004. ASM International, 2004. http://dx.doi.org/10.31399/asm.cp.istfa2004p0385.
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Abstract Die stacking package technology continues to become the trend of manufacturing integrated circuits (IC) today. This primary design offers smaller and thinner packages that would optimize board space and assembly cost. Consequently, this packaging technology has posed challenges in conducting failure analysis. Nondestructive techniques like acoustic microscopy are bound for advancement to make them feasible for use in this packaging technology. This paper will present frequency domain imaging in the field of acoustic microscopy as applied in the detection of delamination defect on a stacked die package. Fast Fourier Transform (FFT) was used as an algorithm to reconstruct and reveal the delamination defect which was not clearly detected in time domain imaging of the package. Frequency domain imaging was found to offer a better image contrast of delamination. This gives the failure analyst another approach to characterize the location and extent of delamination defect, a set of information that is substantial in the root cause analysis of adhesion related failures in stacked die packages.
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Naaijen, Peter, and Elise Blondel-Couprie. "Reconstruction and Prediction of Short-Crested Seas Based on the Application of a 3D-FFT on Synthetic Waves: Part 1 — Reconstruction." In ASME 2012 31st International Conference on Ocean, Offshore and Arctic Engineering. American Society of Mechanical Engineers, 2012. http://dx.doi.org/10.1115/omae2012-83093.
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This article explores the feasibility of using a 3-dimensional Fast Fourier Transform (3D FFT) to obtain a frequency domain description of a spatio temporal measured short crested wave field. As 3D FFT is also the basic technique behind wave measurements by navigational X-band radars, the frequency components obtained by these radars could be used as initialization of a wave propagation model, enabling deterministic prediction of wave elevation on board of ships / offshore structures. Different methods are presented to use the dispersion relation to filter wave components obtained by the 3D FFT. The effect on the accuracy of data windowing and temporal measurement domain size are explored by simulations with linear synthetic wave data: It is investigated how well a synthetic wave field reconstructs after inverse transforming the filtered frequency components obtained by 3D FFT. A second paper [1] will consider the prediction outside the measurement domain by using the filtered 3D FFT components.
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Vijaykumar, Srikanth, Abhijith Sabu, DEBAYAN PRADHAN, and Yash Shrivardhankar. "Improving Reliability of 2 Wheelers Using Predictive Diagnostics." In Small Powertrains and Energy Systems Technology Conference. SAE International, 2023. http://dx.doi.org/10.4271/2023-01-1836.
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<div class="section abstract"><div class="htmlview paragraph">The On-Board Diagnostics (OBD) system can detect problems with the vehicle’s engine, transmission, and emissions control systems to generate error codes that can pinpoint the source of the problem. However, there are several wear and tear parts (air filter, oil filter, batteries, engine oil, belt/chain, clutch, gear tooth) that are not diagnosed but replaced often or periodically in motorcycles/ power sports applications. Traditionally there is a lack of availability of in-field and on-board assistive tools to diagnose vehicle health for 2wheelers. An alert system that informs the riders about health and remaining useful life of their motorcycle can help schedule part replacements, ensuring they are always trip-ready and have a stress-free ownership and service experience. This information can also aid in the correct assessment during warranty claims. With the increase of onboard sensors on vehicles, there has been a notable increase in the availability of condition-monitoring data such as vibration, temperature, pressure, voltage, and other electrical and mechanical parameters. The connectivity device on the motorcycle can transmit this onboard real time data to the cloud for analysis to derive the information of useful life of these components. This paper presents an edge-plus-cloud architecture with part of the algorithm in the Engine Control Unit (ECU) and final processing done on the cloud. Various sensor signals and other vehicle operating parameters are collected and processed using a combination of Machine learning, Fast Fourier Transform, Regression models and other data analytical algorithms. Based on the analysis, information transmitted back from cloud/ Edge device to Vehicle Instrument cluster/ Mobile App/ Web UI to inform rider before the failure has occurred, along with real time data of the remaining useful life of these components.</div></div>