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Shruti, Vinayak Shet, and Vinayak Shet Shruti. "HW/SW Co-Design Implementation on Zedboard." Journal of VLSI Design and its Advancement 2, no. 3 (2020): 1–10. https://doi.org/10.5281/zenodo.3605415.
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<strong><em>ABSTRACT</em></strong> <em>Field Programmable Gate Arrays is an empowering tool for application-oriented methods, provided that a means for rapid prototyping and assessment, as well as algorithm acceleration. Many FPGA dealers have currently started experimenting with embedded processors in their devices, like Xilinx with ARM Cortex A cores, collected with programmable logic cells. These are identified as Programmable System on Chip (PSoC). These ARM cores (embedded in the Processing System or PS) communicate with the programmable logic cells (PL) using ARM standard AXI buses. The hardware setup used in this project is Zedboard along with AD- FMCOMMS2-EBZ is a high speed analog module which has pre- installed IIO OSCILLOSCOPE and GNU RADIO software. The IIO OSCILLSCOPE Linux Application maintains various slots for real time processing and examining the signals attained from the antennas of the analog module. This demand captures the wanted incoming RF signal in the IIO OSCILLOSCOPE where the whole computation is run on to the PS; although the FPGA cloth keeps on idle during this process. During profiling it was found that the most computational expensive block is Fast Fourier transform (FFT) block that took a longer time to display the output. So to lessen the computation time we transfer the FFT block on to the PL side via AXI buses to communicate to the PS side of the board. Due to the parallel nature of FPGA the capability to calculate large mathematical calculation can be made smoother and in lesser time period.</em>
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Ponomareva, O. V., A. V. Ponomarev, and N. V. Smirnova. "Algorithms for Direct and Inverse Parametric Fast Fourier Transform." Informacionnye Tehnologii 28, no. 1 (2022): 9–19. http://dx.doi.org/10.17587/it.28.9-19.
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Русский Main page New issue Archive of articles Editorial board For the authors Publishing house ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES". No. 1. Vol. 28. 2022 DOI: 10.17587/it.28.9-19 O. V. Ponomareva, Dr. Sc., Tech., Professor, A. V. Ponomarev, PhD, Econ., Associate Professor, Kalashnikov Izhevsk State Technical University, Izhevsk, 426069, Russian Federation, N. V. Smirnova, PhD, Tech., Associate Professor, Sevastopol State University, Sevastopol, 299053, Russian Federation Algorithms for Direct and Inverse Parametric Fast Fourier Transform Classical Fourier processing of finite information discrete signals (FID signals) is the most important method of digital analysis, modeling, optimization, improvement of control and decision making. The theoretical basis of classical Fourier processing of FID signals is the discrete Fourier transform (DFT). The practical basis of classical Fourier processing of FID signals is the Fast Fourier Transform (FFT). The practice of using classical Fourier processing of FID signals, having confirmed its effectiveness, revealed a number of negative effects inherent in this type of digital signal processing (DSP). The aliasing effect, scalloping effect, picket fence effect, significantly affect the effectiveness of analysis, modeling, optimization, improvement of management and decision making. To increase the efficiency of Fourier processing of FID signals, the authors of the paper have developed a generalization of DFT in the form of a parametric DFT (DFT-P). Since the direct application of parametric Fourier processing of FID signals (as well as the use of classical Fourier processing of FID signals) requires complex multiplications, fast procedures are required for the practical implementation of this type of FID signals. Purpose of the research is to develop algorithms for the fast parametric discrete Fourier transform (FFT-P). The work developed fast procedures for the implementation of DFT-P by time decimation. Parametric FFT-P with substitution (in place) and without substitution (no place) are proposed. The estimation of the efficiency of the FFT-P algorithms is given. The practical significance of the work is in the fact that developing algorithms for the parametric fast Fourier transform can reduce the computational costs of performing parametric discrete transformations by three or more orders of magnitude.
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Thohari, Afandi Nur Aziz, and Agfianto Eko Putra. "Rancang Bangun Spectrum Analyzer Menggunakan Fast Fouier Transform Pada Single Board Computer." IJEIS (Indonesian Journal of Electronics and Instrumentation Systems) 7, no. 1 (2017): 71. http://dx.doi.org/10.22146/ijeis.16417.
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Spectrum analyzer is an instrument device to measure the magnitude of the frequency and the power of signal. It has many benefits, such as used for testing telecommunication devices, determining the allocation of unused frequencies and also for practicum in schools or universities. However, because of these many benefits, the price of this signal measuring equipment soared in the market.As an alternative, a device that can serve as spectrum analyzer yet has an affordable price is invented in the form of the prototype of spectrum analyzer built using a single board computer by applying a fast Fourier transform algorithm. Feedback from the prototype is in the form of radio signal captured using RTL-SDR.The test results showed that the range of frequencies that can be displayed by the prototype is 24 MHz to 1.769 MHz. Then the test results of fast Fourier transform computing on N points showed that the prototype can work smoothly using the N from 512 to 32.768 points. The use of N more than 32.768 points will cause CPU and disk memory overloaded and lead to a slow performance. Finally, comparison of the levels of spectrum was performed using spectrum analyzer Anritsu MS2720T. As a result, it is known that prototype can be used to show the location of the frequency spectrum of the radio signal appropriately.
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Yang, Hua, Jun Wu, and Lei Meng Cheng. "Research and Design about a System of Harmonic Detection Based on ARM and HHT." Applied Mechanics and Materials 333-335 (July 2013): 487–91. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.487.
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As we all know FFT(Fast Fourier Transform) can be used analyze and calculate linear and stationary signals, while signals in reality are always nonlinear and transient, so we use HHT(Hilbert-Huang Transform) to detect them. In the past,scholars detect harmonics by applying ARM accompany with FFT. In this article, we use the development board S3C6410-as hardware platform. our processor is ARM, while the main algorithm is HHT.
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L. M. Hassan, S., N. Sulaiman, S. S. Shariffudin, and T. N. T. Yaakub. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (2018): 230–35. http://dx.doi.org/10.11591/eei.v7i2.1167.
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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
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S., L. M. Hassan, Sulaiman N., S. Shariffudin S., and N. T. Yaakub T. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (2018): 230–35. https://doi.org/10.11591/eei.v7i2.1167.
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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-tonoise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.
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Pardo, Ehud, and D. K. Cullers. "Design of the fast fourier transform board in the SETI follow-up detection device." Acta Astronautica 42, no. 10-12 (1998): 619–33. http://dx.doi.org/10.1016/s0094-5765(98)00017-4.
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Guaragnella, Cataldo, Agostino Giorgio, and Maria Rizzi. "BFT—Low-Latency Bit-Slice Design of Discrete Fourier Transform." Journal of Low Power Electronics and Applications 13, no. 3 (2023): 45. http://dx.doi.org/10.3390/jlpea13030045.
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Structures for the evaluation of fast Fourier transforms are important components in several signal-processing applications and communication systems. Their capabilities play a key role in the performance enhancement of the whole system in which they are embedded. In this paper, a novel implementation of the discrete Fourier transform is proposed, based on a bit-slice approach and on the exploitation of the input sequence finite word length. Input samples of the sequence to be transformed are split into binary sequences and each one is Fourier transformed using only complex sums. An FPGA-based solution characterized by low latency and low power consumption is designed. Simulations have been carried out, first in the Matlab environment, then emulated in Quartus IDE with Intel. The hardware implementation of the conceived system and the test for the functional accuracy verification have been performed, adopting the DE2-115 development board from Terasic, which is equipped with the Cyclone IV EP4CE115F29C7 FPGA by Intel.
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Vuyets, T. R., and Vladislav A. Ovchinnikov. "Development of a Parallel Fast Fourier Transform-Based Algorithm for Digital Hologram Reconstruction." Advanced Materials Research 1040 (September 2014): 949–53. http://dx.doi.org/10.4028/www.scientific.net/amr.1040.949.
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Digital holography is a comparatively new observation method for micron-sized particles. It is based on numerical reconstruction of recorded interference fringe. Calculation processes for reconstruction are both time- and memory-intensive. The aim of this study was to develop a faster, more efficient algorithm for digital hologram reconstruction. To this purpose Central Processing Unit (CPU) and Graphics Processing Unit (GPU) programming were implemented. For the problem solving the algorithms’ run-time for both configurations was measured. The results showed that the algorithm using a GPU board is faster and more suitable for reconstruction processes. Thus, it makes possible the accomplishment of real-time analysis.
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Jamal, A. Sulisetyono, and W. D. Aryawan. "Direct Measurement of Motion on Fast Ferries." IOP Conference Series: Earth and Environmental Science 1081, no. 1 (2022): 012036. http://dx.doi.org/10.1088/1755-1315/1081/1/012036.
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Abstract This paper describes a new identification method for the fast ferry motions by using the direct measurements on the ship’s board. The inertial sensor type of the Analog Devices (ADIS) 16364 is selected as a as suitable instrument to measure accelerations and velocity of the ship motions namely heave, pitch, and roll in time domain. Furthermore, the ship motion responses are transferred as the energy spectral density in frequency domain which are identified using the Fast Fourier Transform (FFT) method. For the case study, the measurement equipment was placed on the navigation room of MV. Dumai Line 12 recording in 15 minutes within ship voyage from Bengkalis to Batam in September 2021. Finally, the natural frequencies of heave, pitch, and roll motions are identified about 0.568 rad/s, 0.117 rad/s, and 0.227 rad/s, respectively.
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Fu, Haijin, Zheng Wang, Xionglei Lin, et al. "A Two-Dimensional Precision Level for Real-Time Measurement Based on Zoom Fast Fourier Transform." Micromachines 14, no. 11 (2023): 2028. http://dx.doi.org/10.3390/mi14112028.
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This paper proposes a two-dimensional precision level for real-time measurement using a zoom fast Fourier transform (zoom FFT)-based decoupling algorithm that was developed and integrated in an FPGA. This algorithm solves the contradiction between obtaining high resolution and obtaining high measurement speed, and achieves both high angle-resolution measurement and real-time measurement. The proposed level adopts a silicone-oil surface as the angle-sensitive interface and combines the principle of homodyne interference. By analyzing the frequency of the interference fringes, the angle variation can be determined. The zoom-FFT-based decoupling algorithm improves the system’s frequency resolution of the interference fringes, thereby significantly enhancing the angle resolution. Furthermore, this algorithm improves the efficiency of angle decoupling, while the angle decoupling process can also be transplanted to the board to realize real-time measurement of the level. Finally, a prototype based on the level principle was tested to validate the effectiveness of the proposed method. The principle analysis and test results showed that the angle resolution of the prototype improved from 9 arcsec to about 0.1 arcsec using this angle-solution method. At the same time, the measurement repeatability of the prototype was approximately ±0.2 arcsec. In comparison with a commercial autocollimator, the angle measurement accuracy reached ±0.6 arcsec.
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Tabet, Seddik, Adel Ghoggal, Hubert Razik, Ishaq Amrani, and Salah Eddine Zouzou. "Experimental and simulation investigation for rotor bar fault diagnosis in closed-loop induction motors drives." Bulletin of Electrical Engineering and Informatics 12, no. 4 (2023): 2058–68. http://dx.doi.org/10.11591/beei.v12i4.4833.
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This research presents a comparative analysis of two broken rotor bar (BRB) fault identification techniques for closed-loop induction motors (IMs). Both motor current signal analysis and Hilbert transform (HT) rely on spectrum analysis by means of fast fourier transform (FFT). Both approaches have shown their ability to identify BRBs under varying loads. In contrast, the HT is deemed more efficient than the motor current signature analysis (MCSA) approach when the motor is working without load. To maintain a high-performance speed control and to compensate for BRBs effect on the mechanical speed, the approach of control used is direct torque control (DTC). Utilizing a real-time implementation in MATLAB/Simulink with the real-time interface (RTI) based on the dSPACE 1104 board, the efficacy of the two techniques was evaluated.
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Tabet, Seddik, Adel Ghoggal, Hubert Razik, Ishaq Amrani, and Salah Eddine Zouzou. "Experimental and simulation investigation for rotor bar fault diagnosis in closed-loop induction motors drives." Bulletin of Electrical Engineering and Informatics 12, no. 4 (2023): 2058–68. http://dx.doi.org/10.11591/eei.v12i4.4833.
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This research presents a comparative analysis of two broken rotor bar (BRB) fault identification techniques for closed-loop induction motors (IMs). Both motor current signal analysis and Hilbert transform (HT) rely on spectrum analysis by means of fast fourier transform (FFT). Both approaches have shown their ability to identify BRBs under varying loads. In contrast, the HT is deemed more efficient than the motor current signature analysis (MCSA) approach when the motor is working without load. To maintain a high-performance speed control and to compensate for BRBs effect on the mechanical speed, the approach of control used is direct torque control (DTC). Utilizing a real-time implementation in MATLAB/Simulink with the real-time interface (RTI) based on the dSPACE 1104 board, the efficacy of the two techniques was evaluated.
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Cortez, Alfredo, Zulay Franco, and Jose Borjas. "Noise generator by free FPGA technology." Universidad Ciencia y Tecnología 27, no. 121 (2023): 64–73. http://dx.doi.org/10.47460/uct.v27i121.755.
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The IceStorm project by Clifford Wolf, which involved reverse engineering of an FPGA from Lattice, has sparked interest in developing open-source software and hardware within free FPGA communities. As a contribution to these communities, this paper presents the development of a block generator of random sequences with Gaussian distribution in the Icestudio environment. This block was used in the design and implementation of a Gaussian White Noise generator on the open-source FPGA of the Alhambra II board. Experimental tests demonstrated the similarity of the obtained distribution with the results from the simulation in Matlab and the Fast Fourier Transform (FFT) of the generated noise signal, verifying its limited bandwidth spectrum.
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Chen, Ssu-Han, Chen-Wei Wang, Andres Philip Mayol, Chia-Ming Jan, and Tzu-Yi Yang. "Predictive Maintenance for Cutter System of Roller Laminator." Mathematics 13, no. 8 (2025): 1264. https://doi.org/10.3390/math13081264.
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In the era of Industry 4.0, equipment maintenance is shifting toward data-driven strategies. Traditional methods rely on usage time or cycle counts to estimate component lifespan. This often causes early replacement of parts, leading to increased production costs. This study focuses on the cutter system of a roller laminator used in printed circuit board (PCB) manufacturing. An accelerometer is used to collect vibration signals under normal and abnormal states. Fast Fourier transform (FFT) is used to convert time-domain data into the frequency domain, then key statistical features from critical frequency bands are extracted as independent variables. The study applies logistic regression (LR), random forest (RF), and support vector machine (SVM) for predictive modeling of the cutting tool’s condition. The results show that the prediction accuracies of these models are 87.55%, 93.77%, and 94.94%, respectively, with SVM performing the best.
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Nishimura, Atsushi, Takeru Matsumoto, Teppei Yonetsu, et al. "Observational demonstration of a low-cost fast Fourier transform spectrometer with a delay-line-based ramp-compare ADC implemented on FPGA." Publications of the Astronomical Society of Japan 73, no. 3 (2021): 692–700. http://dx.doi.org/10.1093/pasj/psab030.
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Abstract In this study, a novel type of Fourier transform radio spectrometer (termed as all-digital radio spectrometer; ADRS) has been developed in which all functionalities comprising a radio spectrometer including a sampler and Fourier computing unit were implemented as a soft-core on a field-programmable gate array (FPGA). A delay-line-based ramp-compare analog-to-digital converter (ADC), which was completely digital, was used, and two primary elements of the ADC, an analog-to-time converter (ATC) and a time-to-digital converter (TDC), were implemented on the FPGA. The sampling rate of the ADRS f and the quantization bit rate n are limited by the relation τ = 1/(2nf), where τ is the latency of the delay element of the delay-line. Given that the typical latency of the delay element implemented on FPGAs is ∼10 ps, the adoption of a low-quantization bit rate, which satisfies the requirements for radio astronomy, facilitates the realization of a high sampling rate up to ∼100 GSa s−1. In addition, as the proposed ADRS does not require a discrete ADC and can be implemented on mass-produced evaluation boards, its fabrication cost is much lower than that of conventional spectrometers. The ADRS prototype was fabricated with values of f = 600 MSa s−1 and n = 6.6 using a PYNQ-Z1 evaluation board, with a τ of 16.7 ps. The performance of the prototype, including its linearity and stability, was measured, and a test observation was conducted using the Osaka Prefecture University 1.85−m mm–submm telescope; this confirmed the potential application of the prototype in authentic radio observations. With a cost performance 10 times better (∼800 USD GHz−1) than conventional radio spectrometers, the prototype facilitates cost-effective coverage of intermediate frequency bandwidths of ∼100 GHz in modern receiver systems.
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Zushi, Takahiro, Hirotsugu Kojima, and Hiroshi Yamakawa. "One-chip analog circuits for a new type of plasma wave receiver on board space missions." Geoscientific Instrumentation, Methods and Data Systems 6, no. 1 (2017): 159–67. http://dx.doi.org/10.5194/gi-6-159-2017.
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Abstract. Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm × 1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz, respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.
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Li, Xiaoguang, Rui Zhang, Diya Zhang, Xin Fan, Meiqi Guo, and Jinyi Qin. "Prediction of Thermal Conductivity of a Rock Wool Board by Computer X-Ray Tomography Technique Scanning and Random Generation-Growth Model." Advances in Materials Science and Engineering 2022 (September 9, 2022): 1–9. http://dx.doi.org/10.1155/2022/5654325.
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Thermal conductivity of rock wool boards was investigated in this study. Although distribution of fibers in a realistic rock wool board is unclear, it can be simulated by computer X-ray tomography technique (CT) followed by rearrangement through the random generation-growth (RGG) model. An ideal CT-RGG structure model of rock wool boards (CT-random generation-growth model) was established by simplifying material properties based on the mesostructure parameters of the RGG model. Thermal conductivity of rock wool boards with different apparent densities and fiber diameters was studied, and the CT-RGG model was analyzed by explicit jump (EJ) diffusion equations solved by the fast Fourier transform method. We found that thermal conductivity of a single rock wool fiber can be successfully determined. Simulation and measurement results show that thermal conductivity increases consistently with the increase of apparent density and fiber diameter, particularly when the apparent density of rock wool board is greater than 140 kg m−3. Compared with the existing theoretical models, the proposed method does not depend on the empirical parameters; therefore, it is useful in designing and optimizing the thermal conductivity of rock wool boards.
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Qasim, Aseel. "Efficient Multi-Carrier Communication Systems: A Performance Evaluation of Parallel and Sequential Data Processing Models." Journal of Internet Services and Information Security 15, no. 1 (2025): 67–78. https://doi.org/10.58346/jisis.2025.i1.005.
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Orthogonal frequency division multiplexing (OFDM) is a popular method for multi-carrier transmission today. Nonetheless, one disadvantage of OFDM is its large peak-to-average power ratio (PAPR) which decreases the efficiency of power amplifiers. Orthogonal Wavelet Division Multiplexing (OWDM) offers an alternative to Orthogonal Frequency Division Multiplexing (OFDM). While OFDM utilizes the Inverse Fast Fourier Transform (IFFT), OWDM employs the Inverse Discrete Wavelet Transform (IDWT). Previous studies have shown that the Bit Error Rate (BER) for both OWDM and OFDM is nearly identical; however, OWDM features a lower Peak Average Power Ratio (PAPR) compared to OFDM. This research evaluates different wavelets' performance in implementing OWDM and designs two OWDM system models using hardware description language for FPGA implementation. The first design accomplishes data processing parallelly, while the second design processes data sequentially. The first design processes faster than the second one but takes up more resources. Specifically, the former algorithm uses 393 pins with 39% utilization of FPGA resources while the latter algorithm utilizes 73 pins with only 6% use of FPGA resources. Designers are allowed to opt between these proposed models depending on system requirements and available resources. FPGAs provide numerous advantages, including parallel processing power and substantial computational capabilities. The modelling and simulation were performed on the VCU118-XCVU9P-L2FLGA2104E FPGA board.
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De Rosa, Anna, Bernd Luber, Gabor Müller, and Josef Fuchs. "Methodology to Detect Rail Corrugation from Vehicle On-Board Measurements by Isolating Effects from Other Sources of Excitation." Applied Sciences 14, no. 19 (2024): 8920. http://dx.doi.org/10.3390/app14198920.
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Detecting track geometry and rail surface defects using on-board vehicle monitoring systems is a key issue for rail infrastructure managers to increase availability and reliability while reducing the costs associated with monitoring and maintenance. Rail corrugation is one of the most common rail surface defects which grows in almost all metro, conventional and high-speed lines. This paper focuses on the development of a methodology to detect rail corrugation using axle box acceleration measurements acquired on an in-service high-speed vehicle. The main purpose of the proposed methodology is to distinguish the effect of rail corrugation on the accelerations from the other excitations that can be observed in the same wavelength range. For this purpose, the accelerations are analysed by calculating the fast Fourier transform and the spectrogram. Based on the characteristics of each excitation, the effects of modes of vibration, resonances, bridges, switches, and wheel defects are identified. From the remaining effects, which have congruent characteristics, a hypothesis of rail corrugation is formulated. The hypothesis is consolidated with multibody dynamics simulations and by comparing the corrugation indicators provided by the railway infrastructure company.
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Baungarten-Leon, Emilio Isaac, Gustavo Daniel Martín-del-Campo-Becerra, Susana Ortega-Cisneros, Maron Schlemon, Jorge Rivera, and Andreas Reigber. "Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface." Electronics 12, no. 12 (2023): 2558. http://dx.doi.org/10.3390/electronics12122558.
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This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access.
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Pradnya Zode. "Design of area and power-competent FFT architectures with radix-4 butterfly structures." Advances in Nonlinear Variational Inequalities 28, no. 7s (2025): 234–49. https://doi.org/10.52783/anvi.v28.4500.
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In the field of signal processing, systematic examination of the frequency components of a real-time signal is often a top priority. In digital signal processing, the Fast Fourier Transform (FFT) computes the Fourier Transform quickly and accurately, which is significant for finding out and studying frequency components. It develops the performance of radio frequency signals in electronic circuits. For the FFT calculations, the very noteworthy structure is called a butterfly as it is an operation over a complex number. This calculation involves addition and multiplication operations of input real-time signals with applicable coefficients. Therefore, the accurate and optimized design of these butterfly units can result in FFT architectures with decreased area and power consumption. In this paper, two different 16-point FFT structures with radix-4 butterfly units for both DIT as well as DIF are designed. The main goal of this design is to reduce the number of butterflies i.e. addition and multiplication arithmetic operators, so that the designed FFT structures is area and power competent. The area and power-competent FFT architectures are designed using high-level transformation techniques like folding and retiming. Folding is a transformation technique that reduces the silicon area of VLSI hardware implementation by time multiplexing all arithmetic units of a DSP system to a single unit. Retiming is a transformation technique that increases any DSP system's functioning speed by increasing operating frequency. The FFT structures in this paper are designed using Verilog hardware language and implemented on the ML605 Virtex-6 FPGA board. The paper compares the number of butterflies, FPGA resources, and power consumption of two structures for real-time signal DIT and DIF FFT algorithms.
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Ma, Changfu, Wei Xu, and Yue Kuen Kwok. "Willow tree algorithms for pricing VIX derivatives under stochastic volatility models." International Journal of Financial Engineering 07, no. 01 (2020): 2050003. http://dx.doi.org/10.1142/s2424786320500036.
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VIX futures and options are the most popular contracts traded in the Chicago Board Options Exchange. The bid-ask spreads of traded VIX derivatives remain to be wide, possibly due to the lack of reliable pricing models. In this paper, we consider pricing VIX derivatives under the consistent model approach, which considers joint modeling of the dynamics of the S&P index and its instantaneous variance. Under the affine jump-diffusion formulation with stochastic volatility, analytic integral formulas can be derived to price VIX futures and options. However, these integral formulas invariably involve Fourier inversion integrals with cumbersome hyper-geometric functions, thus posing various challenges in numerical evaluation. We propose a unified numerical approach based on the willow tree algorithms to price VIX derivatives under various common types of joint process of the S&P index and its instantaneous variance. Given the analytic form of the characteristic function of the instantaneous variance of the S&P index process in the Fourier domain, we apply the fast Fourier transform algorithm to obtain the transition density function numerically in the real domain. We then construct the willow tree that approximates the dynamics of the instantaneous variance process up to the fourth order moment. Our comprehensive numerical tests performed on the willow tree algorithms demonstrate high level of numerical accuracy, runtime efficiency and reliability for pricing VIX futures and both European and American options under the affine model and 3/2-model. We also examine the implied volatility smirks and the term structures of the implied skewness of VIX options.
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Jaskólski, Krzysztof, Wojciech Czaplinski, and Arkadiusz Tomczak. "Spectral Analysis of Compass Errors Based on Fast Fourier Transform and Reduction Absolute Errors Using a Pass-Band Finite Impulse Response Filter." Polish Maritime Research 31, no. 2 (2024): 109–20. http://dx.doi.org/10.2478/pomr-2024-0027.
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Abstract Compass errors can be regarded as a deviation of the vessel from the expected heading. Gyrocompass errors are randomly oscillating in nature, and it is difficult to describe the behaviour of a gyrocompass sufficiently accurately using mathematical relationships. Fibre-optic gyroscopes have no mechanical components, so the variability in their indications has a different nature; the computational processes and inertial sensors used cause certain types of errors. Thus far, compass studies have focused on presenting absolute errors in the time domain. However, compasses exhibit specific characteristics in the frequency domain that affect the amplitude of their deviation. This leads to the issue of identifying the oscillatory spectrum of errors in the operation of such compasses, and how this spectrum is impacted by the dynamic movement of the vessel. We attempt to assess this phenomenon by means of measurements taken on board the training and research vessel M/S NAWIGATOR XXI. The application of a fast Fourier transform allows for calculation of the absolute compass errors in the frequency domain, meaning that the frequency of occurrence of errors can be observed as noise against the background of the useful signal. Our results confirm the value of applying a finite impulse response filter, which is used to filter out noise in the form of absolute compass errors from the useful signal background. The convolution function proposed here considerably extends the possibilities for analysing the signal spectrum in the frequency domain when testing for the accuracy of compass device indications, and enables the elimination of random errors with a low frequency of occurrence..
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Mon, Yi-Jen. "Simulation and Implementation of Signal Processing for LFM Radar Using DSK 6713." Electronics 12, no. 17 (2023): 3682. http://dx.doi.org/10.3390/electronics12173682.
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This research aims to propose a comprehensive simulation and implementation methodology for LFM (Linear Frequency Modulated) Radar Signal Processing and its application, using digital signal processing techniques on the DSP Starter Kit (DSK) 6713 board. The motivation behind this study is to develop control software based on MATLAB R14 and SIMULINK to model various system software tasks, including detection, A/D conversion, Fast Fourier Transform (FFT), modulation, accumulation, decision-making, and target detection. The simulations are categorized into two groups: ideal beat frequency and parameterized beat frequency. We introduce several important terminologies for consideration, including pulse compression, SNR, matched filter, Doppler effect, and more. The use of real-time data exchange (RTDX) will facilitate the generation of input data and enable real-time calculations for outputs, leading to the creation of machine code for the DSP chip. This process aims to ensure data verification calculations and enhance the credibility and performance of the proposed methodology. By conducting thorough simulations, verification, and practical testing, the study demonstrates the satisfactory credibility and performance of the developed method. Using this research, we aim to contribute to the advancement of LFM Radar Signal Processing and enable its efficient implementation using digital signal processing techniques on the DSP Starter Kit (DSK) 6713 board.
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Wang, Chao, Peiyuan Guo, Donghao Feng, Yangjie Cao, Wenning Zhang, and Pengsong Duan. "An Array-Radar-Based Frequency-Modulated Continuous-Wave Synthetic Aperture Radar Imaging System and Fast Detection Method for Targets." Electronics 14, no. 8 (2025): 1585. https://doi.org/10.3390/electronics14081585.
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This paper proposes a frequency-modulated continuous-wave synthetic aperture radar (FMCW-SAR) imaging system for fast target detection. The system’s antenna array improves azimuthal resolution while maintaining low complexity using a 44-element equivalent virtual array and improves the data acquisition efficiency by employing the trigger and MCU control board. A series of improved algorithms are adopted to increase the speed of radar imaging and achieve fast detection. To solve the problem of large data volumes in traditional array antenna switching control methods, an array switching control algorithm is proposed based on the enhanced ordered statistical constant false alarm rate (EOS-CFAR). The data volume is reduced by dividing the array into several subarrays in advance. The echo signals acquired by the array switching control method are not continuous in the azimuthal direction, and data anomalies are handled by interpolating and compensating the received radar data to form compensated periodic data. The coherent background is subtracted from the padded signal using recursive averaging, resulting in high-resolution imaging while improving the data-processing speed. The TensorFlow-based Omega-K algorithm is employed for synthetic aperture radar (SAR) imaging, which customizes the optimization of TensorFlow for array radar signals. For the radar signal phase optimization, an improved Adam Optimizer optimizes the phase of the radar signal to maintain phase smoothing, thereby improving the clarity of the radar image. The Omega-K algorithm is optimized by TensorFlow and accelerated on the GPU to improve the efficiency of the large-scale fast Fourier transform (FFT) and Stolt interpolation operations, which improves the speed of radar imaging and enables fast detection.
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Researcher. "DESIGN AND IMPLEMENTATION OF LOW POWER PIPELINED FFT ARCHITECTURE FOR DSP APPLICATION." International Journal of Advanced Research in Engineering and Technology (IJARET) 15, no. 4 (2024): 86–94. https://doi.org/10.5281/zenodo.13166453.
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The swift advancements in signal analysis applications have heightened the need for efficient, high-performance architectures to execute complex algorithms like the Quick Fourier Transform (FFT). This study introduces a VLSI implementation of a pipelined FFT architecture customized for DSP applications, addressing challenges in real-time processing, power consumption, and resource utilization. By exploiting the parallelism of the FFT algorithm and using pipelining techniques, our design achieves high throughput and low latency with minimal area overhead and power consumption. Implemented through VLSI techniques, this architecture can be integrated into dedicated DSP processors or system-on-chip (SoC) designs. It is optimized for area efficiency, making it suitable for resource-constrained applications while maintaining high performance. Extensive simulations and comparisons with existing FFT architectures demonstrate its superior throughput, latency, and power efficiency. Additionally, clock gating strategies are employed to further reduce power consumption. The design, synthesized using Xilinx tools and implemented on an Artix-7 FPGA board, was verified for theoretical accuracy using Verilog HDL.
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Hernandez-Gonzalez, Nieves G., Juan Montiel-Caminos, Javier Sosa, and Juan A. Montiel-Nelson. "An Edge Computing Application of Fundamental Frequency Extraction for Ocean Currents and Waves." Sensors 24, no. 5 (2024): 1358. http://dx.doi.org/10.3390/s24051358.
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This paper describes the design and optimization of a smart algorithm based on artificial intelligence to increase the accuracy of an ocean water current meter. The main purpose of water current meters is to obtain the fundamental frequency of the ocean waves and currents. The limiting factor in those underwater applications is power consumption and that is the reason to use only ultra-low power microcontrollers. On the other hand, nowadays extraction algorithms assume that the processed signal is defined in a fixed bandwidth. In our approach, belonging to the edge computing research area, we use a deep neural network to determine the narrow bandwidth for filtering the fundamental frequency of the ocean waves and currents on board instruments. The proposed solution is implemented on an 8 MHz ARM Cortex-M0+ microcontroller without a floating point unit requiring only 9.54 ms in the worst case based on a deep neural network solution. Compared to a greedy algorithm in terms of computational effort, our worst-case approach is 1.81 times faster than a fast Fourier transform with a length of 32 samples. The proposed solution is 2.33 times better when an artificial neural network approach is adopted.
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Villarroel, Adrian, Grover Zurita, and Romeo Velarde. "Development of a Low-Cost Vibration Measurement System for Industrial Applications." Machines 7, no. 1 (2019): 12. http://dx.doi.org/10.3390/machines7010012.
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Vibration-Based Condition Monitoring (VBCM) provides essential data to perform Condition-Based Maintenance for efficient, optimal, reliable, and safe industrial machinery operation. However, equipment required to perform VBCM is often relatively expensive. In this paper, a low-cost vibration measurement system based on a microcontroller platform is presented. The FRDM K64F development board was selected as the most suitable for fulfilling the system requirements. The industrial environment is highly contaminated by noise (electromagnetic, combustion, airborne, sound borne, and mechanical noise). Developing a proper antialiasing filter to reduce industrial noise is a real challenge. In order to validate the developed system, evaluations of frequency response and phase noise were carried out. Additionally, vibration measurements were recorded in the industry under different running conditions and machine configurations. Data were collected simultaneously using a standard reference system and the low-cost vibration measurement system. Results were processed using Fast Fourier Transform and Welch’s method. Finally, a low-cost vibration measurement system was successfully created. The validation process demonstrates the robustness, reliability, and accuracy of this research approach. Results confirm a correlation between signal frequency spectrum obtained using both measurement systems. We also introduce new guidelines for practical data storage, communications, and validation process for vibration measurements.
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Козлов, Д. В., and А. Б. Степанов. "TIME-FREQUENCY SIGNAL ANALYSIS ALGORITHM USING CONTINUOUS WAVELET TRANSFORM AND WELCH’S PERIODOGRAM METHOD WITH ITS IMPLEMENTATION ON GRAPHICAL PROCESSING UNIT." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 3 (July 2, 2021): 85–93. http://dx.doi.org/10.36622/vstu.2021.17.3.012.
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Работа посвящена описанию предложенного авторами алгоритма выполнения частотно-временного анализа сигналов с применением непрерывного вейвлет-преобразования совместно с использованием метода периодограмм Уэлча. При этом приводятся два метода вычисления непрерывного вейвлет-преобразования на основе взаимно-корреляционной функции и на основе быстрого преобразования Фурье. Представлены результаты реализации данного алгоритма на различных графических процессорах (на одноплатных компьютерах с графическим ускорителем и дискретных видеокартах). Выполняются оценка скорости вычисления непрерывного вейвлет-преобразования от частоты дискретизации входного сигнала, оценка скорости вычисления непрерывного вейвлет-преобразования и метода периодограмм Уэлча от числа физических каналов, оценка скорости вычисления метода периодограмм Уэлча от количества частотных ячеек. Было произведено сравнение скорости выполнения двух методов вычисления непрерывного вейвлет-преобразования. Как показали проведённые исследования, среди рассмотренных графических процессоров наилучшие результаты продемонстрировала дискретная видеокарта Nvidia GTX1660 SUPER, которая позволила выполнить предложенный алгоритм за 32,5 мс. Показано, что данный алгоритм может применяться при анализе электроэнцефалограммы с целью определения ее частотного состава и локализации во времени ее основных видов особенностей (соответствующих патологии и артефактам) In the work we describe the algorithm for performing time-frequency analysis of the signals using continuous wavelet transform together with the use of the Welch’s periodogram method. At the same time, we present two methods for calculating the continuous wavelet transform based on the cross-correlation function and on the basis of the fast Fourier transform. We give the results of the implementation of this algorithm on various graphics processors (on single-board computers with a graphics accelerator and discrete video cards). We performed the estimation of the computation speed of the continuous wavelet transform from the sampling frequency of the input signal, the evaluation of the computation speed of the continuous wavelet transform and the Welch periodogram method from the number of physical channels, the evaluation of the computation speed of the Welch periodogram method from the number of frequency cells. We compared the execution speed of the two methods for calculating the continuous wavelet transform. As the studies have shown, among the considered graphics processors, the best results were demonstrated by the discrete Nvidia GTX1660 SUPER graphics card, which made it possible to execute the proposed algorithm in 32.5 ms. We show that this algorithm can be used in the analysis of an electroencephalogram in order to determine its frequency composition and localization in time of its main types of features (corresponding to pathology and artifacts)
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Zandi-Darehgharibi, Farideh, Hedayat Haddadi, and Arash Asfaram. "Fast and Selective Adsorption of Au (III) from the Waste Printed Circuit Boards Using a Low-Cost Adsorbent: Optimization by Central Composite Design Based on Response Surface Methodology." Journal of Chemistry 2023 (September 4, 2023): 1–19. http://dx.doi.org/10.1155/2023/7465722.
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A low-cost new green adsorbent (GA) was synthesized by tannin-rich pomegranate peel powder and formaldehyde for the fast and selective recovery of Au (III). It was characterized by Fourier transform infrared spectroscopy (FT-IR), Brunauer–Emmett–Teller (BET), elemental analysis (CHN), field emission scanning electron microscopy (FE-SEM), and energy-dispersive X-ray spectroscopy (EDS) (FE-SEM-EDS-mapping). The optimal values of influential factors were defined using a central composite design based on the response surface methodology (CCD-RSM). Adsorption properties were investigated by the kinetic, isotherm, thermodynamic, and interference of coexisting metal ions at optimum conditions. The experimental adsorption percentage with three repetitions under the optimized conditions such as pH = 2, adsorbent mass = 23 mg, Au (III) concentration = 32 m g L − 1 , and contact time = 30 min was 97% and the highest adsorption capacity of the GA was 315.450 m g g − 1 . The adsorption isotherm and kinetic were clarified by the Freundlich (R2 = 0.952) and pseudo-second-order (R2 = 0.998) models. The thermodynamic study (∆S° > 0, ∆H° > 0, and ∆G° < 0) revealed that Au (III) adsorption via GA was a facile, endothermic, and spontaneous process. The adsorption mechanism could be an electrostatic interaction and reductive adsorption. A small amount of GA (23 mg) adsorbed gold selectively and rapidly (30 min) from coexisting metals present in the waste printed circuit board (PCB) such as Ag, Al, Si, Zn, Pb, Ba, Ni, Ca, Mo, Co, Cr, Mn, Cu, Mg, Fe, and W. These results confirm the use of low-cost and high-efficiency GA to fast and selectively recover gold from waste PCBs.
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Su, Yu, and Defu Jiang. "Digital Instantaneous Frequency Measurement of a Real Sinusoid Based on Three Sub-Nyquist Sampling Channels." Mathematical Problems in Engineering 2020 (March 24, 2020): 1–11. http://dx.doi.org/10.1155/2020/5089761.
Full textAbstract:
Multichannel sub-Nyquist sampling is an efficient technique to break through the limitation of the Nyquist sampling theorem for the wideband digital instantaneous frequency measurement (DIFM) receiver. The significant challenge is calculating the folding frequency and solving the ambiguity quickly and accurately. Usually, the researchers adopt a fast Fourier transform (FFT) to calculate the folding frequency and a Chinese remainder theorem (CRT) to solve the ambiguity caused by undersampling. However, these algorithms have the drawback of long response time. In this paper, we use a frequency deduction algorithm based on the total least-squares estimation to measure the folding frequency accurately within a few clocks. We propose a frequency-band division algorithm by dividing the measurable frequency range into a few sub-bands to solve the frequency ambiguity. This deblurring algorithm is more efficient and faster than CRT. We analyse the performance of our algorithms by numerical simulations and functional hardware simulations and compare them with FFT and CRT. We also conduct experiments on a hardware platform to confirm the effectiveness of our algorithms. The simulation results show that our algorithms have better performance than FFT and CRT in accuracy and response time. Board-level measurement results verify that the proposed DIFM technique can capture the frequency from 0 to 5,000 MHz with a maximum of 0.8 MHz root-mean-squared error in less than 200 ns.
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Milz, M., T. v. Clarmann, P. Bernath, et al. "Validation of water vapour profiles (version 13) retrieved by the IMK/IAA scientific retrieval processor based on full resolution spectra measured by MIPAS on board Envisat." Atmospheric Measurement Techniques Discussions 2, no. 1 (2009): 489–559. http://dx.doi.org/10.5194/amtd-2-489-2009.
Full textAbstract:
Abstract. Vertical profiles of stratospheric water vapour measured by the Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) between September 2002 and March 2004 and retrieved with the IMK/IAA scientific retrieval processor were compared to a number of independent measurements in order to estimate the bias and to validate the existing precision estimates of the MIPAS data. The independent instruments were: the Halogen Occultation Experiment (HALOE), the Atmospheric Chemistry Experiment Fourier Transform Spectrometer (ACE-FTS), the Improved Limb Atmospheric Spectrometer-II (ILAS-II), the Polar Ozone and Aerosol Measurement (POAM III) instrument, the Middle Atmospheric Water Vapour Radiometer (MIAWARA), the Michelson Interferometer for Passive Atmospheric Sounding, balloon-borne version (MIPAS-B), the Airborne Microwave Stratospheric Observing System (AMSOS), the Fluorescent Stratospheric Hygrometer for Balloon (FLASH-B), the NOAA frostpoint hygrometer, and the Fast In Situ Hygrometer (FISH). In the stratosphere there is no clear indication of a bias in MIPAS data, because the independent measurements in some cases are drier and in some cases are moister than the MIPAS measurements. Compared to the infrared measurements of MIPAS, measurements in the ultraviolet and visible have a tendency to be high, whereas microwave measurements have a tendency to be low. The results of χ2-based precision validation are somewhat controversial among the comparison estimates. However, for comparison instruments whose error budget also includes errors due to uncertainties in spectrally interfering species and where good coincidences were found, the χ2 values found are in the expected range or even below. This suggests that there is no evidence of systematically underestimated MIPAS random errors.
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Roman, Adrian-Silviu, Béla Genge, Adrian-Vasile Duka, and Piroska Haller. "Privacy-Preserving Tampering Detection in Automotive Systems." Electronics 10, no. 24 (2021): 3161. http://dx.doi.org/10.3390/electronics10243161.
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Modern auto-vehicles are built upon a vast collection of sensors that provide large amounts of data processed by dozens of Electronic Control Units (ECUs). These, in turn, monitor and control advanced technological systems providing a large palette of features to the vehicle’s end-users (e.g., automated parking, autonomous vehicles). As modern cars become more and more interconnected with external systems (e.g., cloud-based services), enforcing privacy on data originating from vehicle sensors is becoming a challenging research topic. In contrast, deliberate manipulations of vehicle components, known as tampering, require careful (and remote) monitoring of the vehicle via data transmissions and processing. In this context, this paper documents an efficient methodology for data privacy protection, which can be integrated into modern vehicles. The approach leverages the Fast Fourier Transform (FFT) as a core data transformation algorithm, accompanied by filters and additional transformations. The methodology is seconded by a Random Forest-based regression technique enriched with further statistical analysis for tampering detection in the case of anonymized data. Experimental results, conducted on a data set collected from the On-Board Diagnostics (OBD II) port of a 2015 EUR6 Skoda Rapid 1.2 L TSI passenger vehicle, demonstrate that the restored time-domain data preserves the characteristics required by additional processing algorithms (e.g., tampering detection), showing at the same time an adjustable level of privacy. Moreover, tampering detection is shown to be 100% effective in certain scenarios, even in the context of anonymized data.
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Zainal Abidin, Ana Sakura, Mohamad Syafiq Iylia Jamadi, Sinin Hamdan, et al. "Physicochemical Characterisation of White Pepper: A Comparative Study Between Traditional Sun Drying and Convective Rotary Drum Drying Methods." Pertanika Journal of Tropical Agricultural Science 47, no. 3 (2024): 1021–36. http://dx.doi.org/10.47836/pjtas.47.3.26.
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Drying is a crucial process in preserving the physicochemical qualities of white pepper. This study investigates the impact of two drying processes, namely traditional sun drying (TSD) and rotary drum drying (RDD), on the quality of white pepper. TSD requires three consecutive sunny days for drying, whereas RDD achieves the target moisture content of 12% within a rapid drying time of 120 min. The research employs thermo-gravimetric analysis (TGA), Fourier transform infrared (FTIR) spectroscopy analysis, and scanning electron microscopy (SEM) to analyse the dimensions, thermo-physical profiles, chemical constituents, and microstructure of the pepper samples. RDD, with a drying temperature of 55°C and centrifugation force of 129.7 × g, ensures fast and uniform drying while preserving the physicochemical qualities of white pepper. In terms of physical characteristics, RDD results in larger dried pepper dimensions, measuring 4.56 mm on average, compared to TSD, which measures 4.35 mm. SEM observations reveal varying pore sizes and cracks in both drying methods. Additionally, quality validation conducted by the Malaysian Pepper Board demonstrates that RDD exhibits superior quality compared to TSD. The RDD samples show moisture content, piperine, volatile, and ash percentages of 11.83, 8.18, 2.53, and 0.82, respectively, while the TSD samples show 10.37, 7.16, 2.43, and 0.74. All samples complied with Standard Malaysian White Pepper No. 1 and International Pepper Community Grade 1. Future studies should focus on enhancing different drying methods to achieve efficient white pepper drying while preserving its quality.
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Teymourzadeh, Rozita. "On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for FFT Architecture." American Journal of Engineering and Applied Sciences. ISSN 1941-7020 3, no. 4 (2010): 757–64. https://doi.org/10.5281/zenodo.1239897.
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The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents an on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach is taken; in order to reduce computation complexity in the butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly. In comparison with the conventional butterfly architecture, the design that can only run at a maximum clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.
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Allian, Farhad, and Rekha Jain. "The need for new techniques to identify the high-frequency MHD waves of an oscillating coronal loop." Astronomy & Astrophysics 650 (June 2021): A91. http://dx.doi.org/10.1051/0004-6361/202039763.
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Context. Magnetic arcades in the solar atmosphere, or coronal loops, are common structures known to host magnetohydrodynamic (MHD) waves and oscillations. Of particular interest are the observed properties of transverse loop oscillations, such as their frequency and mode of oscillation, which have received significant attention in recent years because of their seismological capability. Previous studies have relied on standard data analysis techniques, such as a fast Fourier transform (FFT) and wavelet transform (WT), to correctly extract periodicities and identify the MHD modes. However, the ways in which these methods can lead to artefacts requires careful investigation. Aims. We aim to assess whether these two common spectral analysis techniques in coronal seismology can successfully identify high-frequency waves from an oscillating coronal loop. Methods. We examine extreme ultraviolet images of a coronal loop observed by the Atmospheric Imaging Assembly in the 171 Å waveband on board the Solar Dynamics Observatory. We perform a spectral analysis of the loop waveform and compare our observation with a basic simulation. Results. The spectral FFT and WT power of the observed loop waveform is found to reveal a significant signal with frequency ∼2.67 mHz superposed onto the dominant mode of oscillation of the loop (∼1.33 mHz), that is, the second harmonic of the loop. The simulated data show that the second harmonic is completely artificial even though both of these methods identify this mode as a real signal. This artificial harmonic, and several higher modes, are shown to arise owing to the periodic but non-uniform brightness of the loop. We further illustrate that the reconstruction of the ∼2.67 mHz component, particularly in the presence of noise, yields a false perception of oscillatory behaviour that does not otherwise exist. We suggest that additional techniques, such as a forward model of a 3D coronal arcade, are necessary to verify such high-frequency waves. Conclusions. Our findings have significant implications for coronal seismology, as we highlight the dangers of attempting to identify high-frequency MHD wave modes using these standard data analysis techniques.
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Stein, John. "Reduced Visual Magnocellular Event-Related Potentials in Developmental Dyslexia." Brain Sciences 11, no. 1 (2021): 48. http://dx.doi.org/10.3390/brainsci11010048.
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(1) Background—the magnocellular hypothesis proposes that impaired development of the visual timing systems in the brain that are mediated by magnocellular (M-) neurons is a major cause of dyslexia. Their function can now be assessed quite easily by analysing averaged visually evoked event-related potentials (VERPs) in the electroencephalogram (EEG). Such analysis might provide a useful, objective biomarker for diagnosing developmental dyslexia. (2) Methods—in adult dyslexics and normally reading controls, we recorded steady state VERPs, and their frequency content was computed using the fast Fourier transform. The visual stimulus was a black and white checker board whose checks reversed contrast every 100 ms. M- cells respond to this stimulus mainly at 10 Hz, whereas parvocells (P-) do so at 5 Hz. Left and right visual hemifields were stimulated separately in some subjects to see if there were latency differences between the M- inputs to the right vs. left hemispheres, and these were compared with the subjects’ handedness. (3) Results—Controls demonstrated a larger 10 Hz than 5 Hz fundamental peak in the spectra, whereas the dyslexics showed the reverse pattern. The ratio of subjects’ 10/5 Hz amplitudes predicted their reading ability. The latency of the 10 Hz peak was shorter during left than during right hemifield stimulation, and shorter in controls than in dyslexics. The latter correlated weakly with their handedness. (4) Conclusion—Steady state visual ERPs may conveniently be used to identify developmental dyslexia. However, due to the limited numbers of subjects in each sub-study, these results need confirmation.
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Mohan, Navya, and James Kurian. "Design and implementation of shape-based feature extraction engine for vision systems using Zynq SoC." International journal of electrical and computer engineering systems 13, no. 2 (2022): 109–17. http://dx.doi.org/10.32985/ijeces.13.2.3.
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With the great impact of vision and Artificial Intelligence (AI) technology in the fields of quality control, robotic assembly and robot navigation, the hardware implementation of object detection and classification algorithms on embedded platforms has got ever-increasing attention these days. The real-time performance with optimum resource utilization of the implementation and its reliability as well as the robustness of the underlying algorithm is the overarching challenges in this field. In this work, an approach employing a fast and accurate vision-based shape-detection algorithm has been proposed and its implementation in heterogeneous System on Chip (SoC) is discussed. The proposed system determines centroid distance and its Fourier Transform for the object feature vector extraction and is realized in the Zybo Z7 development board. The ARM processor is responsible for communication with the external systems as well as for writing data to the Block RAM (BRAM), the control signals for efficient execution of the memory operations are designed and implemented using Finite State Machine (FSM) in the Programmable Logic (PL) fabric. Shape feature vector determination has been accelerated using custom modules developed in Verilog, taking full advantage of the possible parallelization and pipeline stages. Meanwhile, industry-standard Advanced Extendable Interface (AXI) buses are adopted for encapsulating standardized IP cores and building high-speed data exchange bridges between units within Zynq-7000. The developed system processes images of size 32 × 64 in real-time and can generate feature descriptors at a clock rate of 62MHz. Moreover, the method yields a shape feature vector that is computationally light, scalable and rotation invariant. The hardware design is validated using MATLAB for comparative studies
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Milz, M., T. v. Clarmann, P. Bernath, et al. "Validation of water vapour profiles (version 13) retrieved by the IMK/IAA scientific retrieval processor based on full resolution spectra measured by MIPAS on board Envisat." Atmospheric Measurement Techniques 2, no. 2 (2009): 379–99. http://dx.doi.org/10.5194/amt-2-379-2009.
Full textAbstract:
Abstract. Vertical profiles of stratospheric water vapour measured by the Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) with the full resolution mode between September 2002 and March 2004 and retrieved with the IMK/IAA scientific retrieval processor were compared to a number of independent measurements in order to estimate the bias and to validate the existing precision estimates of the MIPAS data. The estimated precision for MIPAS is 5 to 10% in the stratosphere, depending on altitude, latitude, and season. The independent instruments were: the Halogen Occultation Experiment (HALOE), the Atmospheric Chemistry Experiment Fourier Transform Spectrometer (ACE-FTS), the Improved Limb Atmospheric Spectrometer-II (ILAS-II), the Polar Ozone and Aerosol Measurement (POAM III) instrument, the Middle Atmospheric Water Vapour Radiometer (MIAWARA), the Michelson Interferometer for Passive Atmospheric Sounding, balloon-borne version (MIPAS-B), the Airborne Microwave Stratospheric Observing System (AMSOS), the Fluorescent Stratospheric Hygrometer for Balloon (FLASH-B), the NOAA frostpoint hygrometer, and the Fast In Situ Hygrometer (FISH). For the in-situ measurements and the ground based, air- and balloon borne remote sensing instruments, the measurements are restricted to central and northern Europe. The comparisons to satellite-borne instruments are predominantly at mid- to high latitudes on both hemispheres. In the stratosphere there is no clear indication of a bias in MIPAS data, because the independent measurements in some cases are drier and in some cases are moister than the MIPAS measurements. Compared to the infrared measurements of MIPAS, measurements in the ultraviolet and visible have a tendency to be high, whereas microwave measurements have a tendency to be low. The results of χ2-based precision validation are somewhat controversial among the comparison estimates. However, for comparison instruments whose error budget also includes errors due to uncertainties in spectrally interfering species and where good coincidences were found, the χ2 values found are in the expected range or even below. This suggests that there is no evidence of systematically underestimated MIPAS random errors.
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Knapp, Marvin, Ralph Kleinschek, Frank Hase, et al. "Shipborne measurements of XCO<sub>2</sub>, XCH<sub>4</sub>, and XCO above the Pacific Ocean and comparison to CAMS atmospheric analyses and S5P/TROPOMI." Earth System Science Data 13, no. 1 (2021): 199–211. http://dx.doi.org/10.5194/essd-13-199-2021.
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Abstract. Measurements of atmospheric column-averaged dry-air mole fractions of carbon dioxide (XCO2), methane (XCH4), and carbon monoxide (XCO) have been collected across the Pacific Ocean during the Measuring Ocean REferences 2 (MORE-2) campaign in June 2019. We deployed a shipborne variant of the EM27/SUN Fourier transform spectrometer (FTS) on board the German R/V Sonne which, during MORE-2, crossed the Pacific Ocean from Vancouver, Canada, to Singapore. Equipped with a specially manufactured fast solar tracker, the FTS operated in direct-sun viewing geometry during the ship cruise reliably delivering solar absorption spectra in the shortwave infrared spectral range (4000 to 11000 cm−1). After filtering and bias correcting the dataset, we report on XCO2, XCH4, and XCO measurements for 22 d along a trajectory that largely aligns with 30∘ N of latitude between 140∘ W and 120∘ E of longitude. The dataset has been scaled to the Total Carbon Column Observing Network (TCCON) station in Karlsruhe, Germany, before and after the MORE-2 campaign through side-by-side measurements. The 1σ repeatability of hourly means of XCO2, XCH4, and XCO is found to be 0.24 ppm, 1.1 ppb, and 0.75 ppb, respectively. The Copernicus Atmosphere Monitoring Service (CAMS) models gridded concentration fields of the atmospheric composition using assimilated satellite observations, which show excellent agreement of 0.52±0.31 ppm for XCO2, 0.9±4.1 ppb for XCH4, and 3.2±3.4 ppb for XCO (mean difference ± SD, standard deviation, of differences for entire record) with our observations. Likewise, we find excellent agreement to within 2.2±6.6 ppb with the XCO observations of the TROPOspheric MOnitoring Instrument (TROPOMI) on the Sentinel-5 Precursor satellite (S5P). The shipborne measurements are accessible at https://doi.org/10.1594/PANGAEA.917240 (Knapp et al., 2020).
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Alif Haiqal Khairul Shah, Khairul Azlan A Rahman, Goh Thing Thing, Sin Jin Tan, Christian Ritz, and Norfaiza Fuad. "Investigation of Electroencephalographic (EEG) Brainwave Signal on Mental Stress through Psychomotor Activities." Journal of Advanced Research in Applied Sciences and Engineering Technology 62, no. 2 (2025): 245–58. https://doi.org/10.37934/araset.62.2.245258.
Full textAbstract:
Mental well-being plays a crucial aspect in human life alongside physical health. A positive mental health allows individuals to engage in healthy relationship, navigate challenges in a positive manner and enjoys a sense of fulfilment upon achieving goals. Conversely, when mental health is not well taken care of, it can impair one’s ability to function well in daily life, which subsequently leads to depression and anxiety disorder. Hence, early detection and intervention is necessary for individuals experiencing mental health challenges. The aim of this work is to study the recorded Electroencephalogram (EEG) signals of human subjects for stress detection while engaging in psychomotor activity. EEG signals captured from electrodes were sent to OpenBCI on a laptop via a ganglion board for analysis. The data was then exported to Matlab for further analysis using Fast Fourier Transform (FFT) and was monitored in real time using Python. Volunteers between the ages of 18 and 50 were carefully chosen, and the experimental conditions were closely monitored to reduce any external factors that could affect stress levels and EEG readings. The findings reveal notable changes in brainwave frequencies observed during periods of stress: a decrease of 18.95% in alpha waves, a 9.89% increase in beta waves, and a 5% rise in delta waves. Comparison was also carried out by placing the electrodes at different location on the subject’s head Significantly, there was a 7.5% increase in alpha readings at the top electrode positions, with beta (4.76%) and theta (1.93%) readings also showing growth at the side positions on the head. An accuracy of 65% was obtained using the developed monitoring system. This research effectively illuminates the relationship between mental stress, physical activity, and EEG brainwave patterns. It highlights the important role that brainwave frequencies play in influencing stress and cognitive responses during physical activity. In addition, the advancement of real-time monitoring systems offers dynamic tools for observing stress, improving opportunities for personalized therapies and strategies for well-being.
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Xie, Yu, Yizhuang Xie, Bingyi Li, and He Chen. "Advancements in Spaceborne Synthetic Aperture Radar Imaging with System-on-Chip Architecture and System Fault-Tolerant Technology." Remote Sensing 15, no. 19 (2023): 4739. http://dx.doi.org/10.3390/rs15194739.
Full textAbstract:
With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR imaging chip based on a SoC architecture with system fault-tolerant technology. The fault-tolerant SAR SoC architecture has a CPU, interface subsystem, memory subsystem, data transit subsystem, and data processing subsystem. The data processing subsystem, which includes fast Fourier transform (FFT) modules, coordinated rotation digital computer (CORDIC) modules (for phase factor calculation), and complex multiplication modules, is the most critical component and can achieve various modes of SAR imaging. Through analyzing the computational requirements of various modes of SAR, we found that FFT accounted for over 50% of the total computational workload in SAR imaging processing, while the CORDIC modules for phase factor generation accounted for around 30%. Therefore, ensuring the fault tolerance of these two modules is crucial. To address this issue, we propose a word-length optimization redundancy (WLOR) method to make the fixed-point pipelined FFT processors in FFT modules fault tolerant. Additionally, we propose a fault-tolerant pipeline CORDIC architecture utilizing error correction code (ECC) and sum of squares (SOS) check. For other parts of the SoC architecture, we propose a generic partial triple modular redundancy (TMR) hardening method based on the HITS algorithm to improve fault tolerance. Finally, we developed a fully automated FPGA-based fault injection platform to test the design’s effectiveness by injecting errors at arbitrary locations. The simulation results demonstrate that the proposed methods significantly improved the chip’s fault tolerance, making the SAR imaging chip safer and more reliable. We also implemented a prototype measurement system with a chip-included board and demonstrated the proposed design’s performance on the Chinese Gaofen-3 strip-map continuous imaging system. The chip requires 9.2 s, 50.6 s, and 7.4 s for a strip-map with 16,384 × 16,384 granularity, multi-channel strip-map with 65,536 × 8192 granularity, and multi-channel scan mode with 32,768 × 4096 granularity, respectively, and the system hardware consumes 6.9 W of power to process the SAR raw data.
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Teymourzaedh, Rozita. "VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers." American Journal of Engineering and Applied Sciences.vISSN 1941-7020 3, no. 4 (2010): 663–69. https://doi.org/10.5281/zenodo.1239903.
Full textAbstract:
The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.
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Walid, Walid, Muhammad Awais, Ashfaq Ahmed, Guido Masera, and Maurizio Martina. "Real-time implementation of fast discriminative scale space tracking algorithm." Journal of Real-Time Image Processing, May 22, 2021. http://dx.doi.org/10.1007/s11554-021-01119-6.
Full textAbstract:
AbstractReal-time object tracking is an important step of many modern image processing applications. The efficient hardware design of real-time object tracker must achieve the desired accuracy while satisfying the frame rate requirements for a variety of image sizes. The existing methods of visual tracking employ sophisticated algorithms and challenge the capabilities of most embedded architectures. Discriminative scale space tracking is one algorithm that is capable of demonstrating good performance with affordable complexity. It has a high degree of parallelism which can be exploited for efficient implementation of reconfigurable hardware architectures. This paper proposes a real-time implementation of the discriminative scale-space tracker on FPGA for the major blocks. A careful design exploration of core mathematical operations of the tracking algorithm is performed to improve their hardware utilization and timing performance. Among the core functional units optimized in this work, the discrete Fourier transform achieves a computational time improvement of 92% relative to existing works, QR factorization achieves a 2.3$$\times$$ × reduction in resource utilization, and singular value decomposition yields a 3.8$$\times$$ × improvement in processing time. The proposed data path architecture is designed using Vivado HLS tool set and implemented for Zync Zed Board (xc7z020clg484-1). For an input image size of 320 $$\times$$ × 240, the proposed architecture achieves a mean 25.38 fps.
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Walid, Walid, Muhammad Awais, Ashfaq Ahmed, Guido Masera, and Maurizio Martina. "Real-time implementation of fast discriminative scale space tracking algorithm." May 22, 2021. https://doi.org/10.1007/s11554-021-01119-6.
Full textAbstract:
AbstractReal-time object tracking is an important step of many modern image processing applications. The efficient hardware design of real-time object tracker must achieve the desired accuracy while satisfying the frame rate requirements for a variety of image sizes. The existing methods of visual tracking employ sophisticated algorithms and challenge the capabilities of most embedded architectures. Discriminative scale space tracking is one algorithm that is capable of demonstrating good performance with affordable complexity. It has a high degree of parallelism which can be exploited for efficient implementation of reconfigurable hardware architectures. This paper proposes a real-time implementation of the discriminative scale-space tracker on FPGA for the major blocks. A careful design exploration of core mathematical operations of the tracking algorithm is performed to improve their hardware utilization and timing performance. Among the core functional units optimized in this work, the discrete Fourier transform achieves a computational time improvement of 92% relative to existing works, QR factorization achieves a 2.3$$\times$$ × reduction in resource utilization, and singular value decomposition yields a 3.8$$\times$$ × improvement in processing time. The proposed data path architecture is designed using Vivado HLS tool set and implemented for Zync Zed Board (xc7z020clg484-1). For an input image size of 320 $$\times$$ × 240, the proposed architecture achieves a mean 25.38 fps.
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Moung, Young Lee, and Gyu Song Chul. "Comparison of Back-Projection with Non-Uniform Fast Fourier Transform for Real-Time Photoacoustic Tomography." March 5, 2016. https://doi.org/10.5281/zenodo.1123977.
Full textAbstract:
Photoacoustic imaging is the imaging technology that combines the optical imaging and ultrasound. This provides the high contrast and resolution due to optical imaging and ultrasound imaging, respectively. We developed the real-time photoacoustic tomography (PAT) system using linear-ultrasound transducer and digital acquisition (DAQ) board. There are two types of algorithm for reconstructing the photoacoustic signal. One is back-projection algorithm, the other is FFT algorithm. Especially, we used the non-uniform FFT algorithm. To evaluate the performance of our system and algorithms, we monitored two wires that stands at interval of 2.89 mm and 0.87 mm. Then, we compared the images reconstructed by algorithms. Finally, we monitored the two hairs crossed and compared between these algorithms.
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Moung, Young Lee, and Gyu Song Chul. "Comparison of Back-Projection with Non-Uniform Fast Fourier Transform for Real-Time Photoacoustic Tomography." International Journal of Medical, Medicine and Health Sciences 9.0, no. 4 (2016). https://doi.org/10.5281/zenodo.1339237.
Full textAbstract:
Photoacoustic imaging is the imaging technology that combines the optical imaging and ultrasound. This provides the high contrast and resolution due to optical imaging and ultrasound imaging, respectively. We developed the real-time photoacoustic tomography (PAT) system using linear-ultrasound transducer and digital acquisition (DAQ) board. There are two types of algorithm for reconstructing the photoacoustic signal. One is back-projection algorithm, the other is FFT algorithm. Especially, we used the non-uniform FFT algorithm. To evaluate the performance of our system and algorithms, we monitored two wires that stands at interval of 2.89 mm and 0.87 mm. Then, we compared the images reconstructed by algorithms. Finally, we monitored the two hairs crossed and compared between these algorithms.
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López-Randulfe, Javier, Tobias Duswald, Zhenshan Bing, and Alois Knoll. "Spiking Neural Network for Fourier Transform and Object Detection for Automotive Radar." Frontiers in Neurorobotics 15 (June 7, 2021). http://dx.doi.org/10.3389/fnbot.2021.688344.
Full textAbstract:
The development of advanced autonomous driving applications is hindered by the complex temporal structure of sensory data, as well as by the limited computational and energy resources of their on-board systems. Currently, neuromorphic engineering is a rapidly growing field that aims to design information processing systems similar to the human brain by leveraging novel algorithms based on spiking neural networks (SNNs). These systems are well-suited to recognize temporal patterns in data while maintaining a low energy consumption and offering highly parallel architectures for fast computation. However, the lack of effective algorithms for SNNs impedes their wide usage in mobile robot applications. This paper addresses the problem of radar signal processing by introducing a novel SNN that substitutes the discrete Fourier transform and constant false-alarm rate algorithm for raw radar data, where the weights and architecture of the SNN are derived from the original algorithms. We demonstrate that our proposed SNN can achieve competitive results compared to that of the original algorithms in simulated driving scenarios while retaining its spike-based nature.
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Seddik, Tabet, Ghoggal Adel, Razik Hubert, Amrani Ishaq, and Eddine Zouzou Salah. "Experimental and simulation investigation for rotor bar fault diagnosis in closed-loop induction motors drives." August 1, 2023. https://doi.org/10.11591/eei.v12i4.4833.
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This research presents a comparative analysis of two broken rotor bar (BRB) fault identification techniques for closed-loop induction motors (IMs). Both motor current signal analysis and Hilbert transform (HT) rely on spectrum analysis by means of fast fourier transform (FFT). Both approaches have shown their ability to identify BRBs under varying loads. In contrast, the HT is deemed more efficient than the motor current signature analysis (MCSA) approach when the motor is working without load. To maintain a high-performance speed control and to compensate for BRBs effect on the mechanical speed, the approach of control used is direct torque control (DTC). Utilizing a real-time implementation in MATLAB/Simulink with the real-time interface (RTI) based on the dSPACE 1104 board, the efficacy of the two techniques was evaluated.