Готові списки джерел за темами / Circuit reliability simulation

Добірка наукової літератури з теми "Circuit reliability simulation"

Автор: Grafiati
Опубліковано: 23 вересня 2022
Оновлено: 28 січня 2023

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  1. Статті в журналах
  2. Дисертації
  3. Книги
  4. Частини книг
  5. Тези доповідей конференцій

Статті в журналах з теми "Circuit reliability simulation":

1

Lei, Chi Un, K. L. Man, Eng Gee Lim, Nan Zhang, and Kai Yu Wan. "Development of a Reliability Course for Emerging Circuits and Systems." Advanced Materials Research 622-623 (December 2012): 1922–24. http://dx.doi.org/10.4028/www.scientific.net/amr.622-623.1922.

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This paper presents a curriculum design of a course about reliability of circuits and systems. Contents in the learning modules include failure mechanisms of electronics, reliability for electronic components and circuit systems and simulation for circuit reliability. Through learning modules, students can learn concepts about reliability in circuits and systems, as well as develop awareness to design a reliable circuit system.
2

Kim, Je-Hyuk, Youngjin Seo, Jun Tae Jang, Shinyoung Park, Dongyeon Kang, Jaewon Park, Moonsup Han, Changwook Kim, Dong-Wook Park, and Dae Hwan Kim. "Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate." Applied Sciences 11, no. 11 (May 25, 2021): 4838. http://dx.doi.org/10.3390/app11114838.

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Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (VT) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al2O3 gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits.
3

Cao, Yu, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, and Michael Fritze. "Cross-Layer Modeling and Simulation of Circuit Reliability." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 1 (January 2014): 8–23. http://dx.doi.org/10.1109/tcad.2013.2289874.

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4

Alexeyev, Alexander A., and Michael M. Green. "Secure Communications Based on Variable Topology of Chaotic Circuits." International Journal of Bifurcation and Chaos 07, no. 12 (December 1997): 2861–69. http://dx.doi.org/10.1142/s0218127497001941.

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A new technique for synchronization of chaotic circuits is proposed. This technique, based on varying a circuit's overall topology rather than varying a set of continuous parameters, offers a possible resolution to the tradeoff between security and synchronizability inherent in existing chaotic systems. The encryption key is represented by a mapping from a set of nodes to a set of switches in the circuit. This method significantly improves reliability and can be easily interfaced to digital control circuits.
5

Zhang, Yu, and Ji Dong Li. "Simulation Research of a Soft Power Bi-Directional DC-DC Converter." Advanced Materials Research 945-949 (June 2014): 2327–30. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.2327.

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A type of BUCK/BOOST bi-directional DC-DC topology for high power occasions was presented based on the main circuit topology shortcomings of conventional BUCK/BOOST bidirectional DC-DC converter by increasing the inductance, capacitance, diode auxiliary circuits, the work process of the main circuit BUCK BOOST in the simulation state was analyzed. Select multiple sets of parameters on simulation, observe the waveform ON and OFF of main power device to determine the appropriate auxiliary circuit parameter set. The results show that: The topology suppresses large current peak of the main power device and improve the reliability.
6

Li, Minghan, Chenglong Fu, Jingyi Huang, and Jiaxin Liu. "Reliability Evaluation Model of Distribution Network Based on Circuit Structure." Journal of Physics: Conference Series 2310, no. 1 (October 1, 2022): 012070. http://dx.doi.org/10.1088/1742-6596/2310/1/012070.

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Abstract In order to meet the electricity requirements and improve the quality of distribution networks, it is essential to improve the reliability level of the power system. This paper established several mathematical models based on circuit analysis and computer simulation to realize the evaluation of distribution network reliability. Firstly, the Sequential Monte Carlo method was utilized to simulate the indicators of series and parallel circuits, and the Entropy Weight Method was adopted to weight the indicators. Then, simulation results were comprehensively evaluated using the Technique for Order Preference by Similarity to Ideal Solution (TOPSIS), and the evaluation model of distribution network reliability was obtained. The established mathematical model provided some guidance to construct an industrial distribution network and improve the reliability level of the power system.
7

NASEH, SASAN, and M. JAMAL DEEN. "RF CMOS RELIABILITY." International Journal of High Speed Electronics and Systems 11, no. 04 (December 2001): 1249–95. http://dx.doi.org/10.1142/s0129156401001088.

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In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.
8

Суханова, Наталия, and Nataliya Sukhanova. "ELECTRONIC CIRCUIT FAILURE MODELING USING NEURAL NETWORKS." Bulletin of Bryansk state technical university 2018, no. 8 (October 25, 2018): 76–83. http://dx.doi.org/10.30987/article_5bb5e6f323cf39.47317213.

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The object of researches is electronic circuits. For elements of the circuit there are defined characteristics of input and output signals in a working condition and at a state of non-operability. The subject of researches is a reliability of electronic circuits (EC). The purpose of the work consists in the automation of reliability tests at the expense of the failure simulation of electronic circuit elements with the aid of artificial neural networks (ANN). There is developed a method for carrying out EC reliability tests with the use of automation means. During tests one simulates different failures of circuit elements. For element failure simulation there are used ANN trained fragments. The ANN fragments are trained with the use of the selection of input and output signals of the element in a working condition and at a state non-operability. For the signal formation of a working condition a signal generator is used. For the signal formation of a state of nonoperability the signals from outputs of a noise generator are added. To reduce time and costs for training there is offered for use the ANN of a special switch type which allows copying, replicating, modifying ANN, training and forming ANN from its fragments.
9

Chen, Jinjie. "A Simulation Research on the Grid-Connected Control Technology of Single-Phase Inverters Based on MATLAB." Journal of Electronic Research and Application 6, no. 4 (July 27, 2022): 7–12. http://dx.doi.org/10.26689/jera.v6i4.4154.

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This paper primarily discusses the main circuit of single-phase inverter circuits. It begins by introducing the research context and the significance of the subject, then discusses the topology of grid-connected single-phase inverter circuits, continues by discussing the control strategy for grid-connected single-phase inverter circuits, realizes a sinusoidal pulse width modulation (SPWM) signal generation circuit and an inverse control algorithm program, and finally ensures good output waveform and fast dynamic response. In view of the hysteresis feature of the grid voltage’s synchronous signal sampling circuit, the acquisition function in digital signal processing (DSP) control chips is applied, and the reasons for the hysteresis phenomenon are thoroughly investigated. The reliability of the SPWM control algorithm is revealed through the results.
10

Zandevakili, Hamed, Ali Mahani, and Mohsen Saneei. "An accurate and fast reliability analysis method for combinational circuits." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, no. 3 (May 5, 2015): 979–95. http://dx.doi.org/10.1108/compel-06-2014-0137.

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Purpose – One of the main issues which microelectronics industry encounter is reliability as feature sizes scale down to nano-design level. The purpose of this paper is to provide a probabilistic transfer matrix based to find the accurate and efficient method of finding circuit’s reliability. Design/methodology/approach – The proposed method provides a probabilistic description of faulty behavior and is well-suited to reliability and error susceptibility calculations. The proposed method offers accurate circuit reliability calculations in the presence of reconvergent fanout. Furthermore, a binary probability matrix is used to not only resolve signals correlation problem but also improve the accuracy of the obtained reliability in the presence of reconverging signals. Findings – The results provide the accuracy and computation time of reliability evaluation for ISCAS85 benchmark schemes. Also, simulations have been conducted on some digital circuits involving LGSynth’91 circuits. Simulation results show that proposed solution is a fast method with less complexity and gives an accurate reliability value in comparison with other methods. Originality/value – The proposed method is the only scheme giving the low calculation time with high accuracy compared to other schemes. The library-based method also is able to evaluate the reliability of every scheme independent from its circuit topology. The comparison exhibits that a designer can save its evaluation time in terms of performance and complexity.
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Статті в журналах Дисертації

Дисертації з теми "Circuit reliability simulation":

1

Li, Xiaojun. "Deep submicron CMOS VLSI circuit reliability modeling, simulation and design." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3124.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.
Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
2

Trattles, John T. "Finite element simulation of VLSI interconnections with application to reliability design optimisation and electromigration modelling." Thesis, University of Newcastle Upon Tyne, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.334059.

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3

Brusamarello, Lucas. "Modeling and simulation of device variability and reliability at the electrical level." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2011. http://hdl.handle.net/10183/65634.

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O efeito das variações intrínsecas afetando parâmetros elétricos de circuitos fabricados com tecnologia CMOS de escala nanométrica apresenta novos desafios para o yield de circuitos integrados. Este trabalho apresenta modelos para representar variações físicas que afetam transistores projetados em escala sub-micrônica e metodologias computacionalmente eficientes para simular estes dispositivos utilizando ferramentas de Electronic Design Automation (EDA). O trabalho apresenta uma investigação sobre o estado-da-arte de modelos para variabilidade em nível de simulação de transistor. Modelos de variações no processo de fabricação (RDF, LER, etc) e confiabilidade (NBTI, RTS, etc) são investigados e um novo modelo estatístico para a simulação de Random Telegraph Signal (RTS) e Bias Temperature Instability (BTI) para circuitos digitais é proposta. A partir desses modelos de dispositivo, o trabalho propõe modelos eficientes para analisar a propagação desses fenômenos para o nível de circuito através de simulação. As simulações focam no impacto de variabilidade em três diferentes aspectos do projeto de circuitos integrados digitais: caracterização de biblioteca de células, análise de violações de tempo de hold e células SRAM. Monte Carlo é a técnica mais conhecida e mais simples para simular o impacto da variabilidade para o nível elétrico do circuito. Este trabalho emprega Monte Carlo para a análise do skew em redes de distribuição do sinal de relógio e em caracterização de células SRAM considerando RTS. Contudo, simulações Monte Carlo exigem tempo de execução elevado. A fim de acelerar a análise do impacto de variabilidade em biblioteca de células este trabalho apresenta duas alternativas aMonte Carlo: 1) propagação de erros usando aproximação linear de primeira ordem e 2)Metodologia de Superfície de Resposta (RSM). As técnicas são validados usando circuitos de nível comercial, como a rede de clock de um chip comercial utilizando a tecnologia de 90nm e uma biblioteca de células usando um nó tecnológico de 32nm.
In nanometer scale complementary metal-oxide-semiconductor (CMOS) parameter variations pose a challenge for the design of high yield integrated circuits. This work presents models that were developed to represent physical variations affecting Deep- Submicron (DSM) transistors and computationally efficient methodologies for simulating these devices using Electronic Design Automation (EDA) tools. An investigation on the state-of-the-art of computer models and methodologies for simulating transistor variability is performed. Modeling of process variability and aging are investigated and a new statistical model for simulation of Random Telegraph Signal (RTS) in digital circuits is proposed. The work then focuses on methodologies for simulating these models at circuit level. The simulations focus on the impact of variability to three relevant aspects of digital integrated circuits design: library characterization, analysis of hold time violations and Static Random Access Memory (SRAM) cells. Monte Carlo is regarded as the "golden reference" technique to simulate the impact of process variability at the circuit level. This work employs Monte Carlo for the analysis of hold time and SRAM characterization. However Monte Carlo can be extremely time consuming. In order to speed-up variability analysis this work presents linear sensitivity analysis and Response Surface Methodology (RSM) for substitutingMonte Carlo simulations for library characterization. The techniques are validated using production level circuits, such as the clock network of a commercial chip using 90nm technology node and a cell library using a state-of-theart 32nm technology node.
4

CUI, ZHI. "MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2163.

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Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation
Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
5

Wilson, Antony R. "Modelling and simulation of paradigms for printed circuit board assembly to support the UK's competency in high reliability electronics." Thesis, Loughborough University, 2012. https://dspace.lboro.ac.uk/2134/10236.

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The fundamental requirement of the research reported within this thesis is the provision of physical models to enable model based simulation of mainstream printed circuit assembly (PCA) process discrete events for use within to-be-developed (or under development) software tools which codify cause & effects knowledge for use in product and process design optimisation. To support a national competitive advantage in high reliability electronics UK based producers of aircraft electronic subsystems require advanced simulation tools which offer model based guidance. In turn, maximization of manufacturability and minimization of uncontrolled rework must therefore enhance inservice sustainability for 'power-by-the-hour' commercial aircraft operation business models.
6

Tran, Thi-Phuong-Yen. "CMOS 180 nm Compact Modeling Including Ageing Laws for Harsh Environment." Thesis, Bordeaux, 2022. http://www.theses.fr/2022BORD0185.

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Au cours des dernières décennies, la demande de fonctionnalités complexes et d'intégration haute densité pour les Circuits Intégrés (CI) a mené à une réduction de la taille des dispositifs métal-oxyde-silicium (MOS). Dans ce scénario, les problèmes de fiabilité sont les préoccupations considérables par suite de la miniaturisation de l'appareil, telles que Hot Carrier Injection (HCI) et Bias Temperature Instability (BTI) qui ont un impact sérieux sur les performances de l'appareil. Dans certains domaines d'application où le coût des pannes est extrêmement élevé, comme l'espace, les champs pétrolifères ou les soins de santé, l'appareil doit pouvoir fonctionner de manière stable et fiable, en particulier dans une plage de températures étendue. Bien que les mécanismes de défaillance des dispositifs aient été intensivement étudiés dans le passé, les investigations de ces mécanismes à hautes températures sont rarement étudiées.L'objectif de cette thèse est de développer les lois de vieillissement de la technologie CMOS 0.18µm afin d'optimiser la conception des circuits pour une durée de vie ciblée sous des températures extrêmes. Nous avons mené une campagne intensive de tests de vieillissement pour nMOS et pMOS avec plusieurs longueurs de grille. Les mécanismes HCI et BTI intrinsèques ont été caractérisés et modélisés sous des tensions de polarisation de fonctionnement typique pour éviter le risque de sur-accélération d'autres mécanismes d'usure qui ne sont pas censés être expérimentés dans l'application pratique. Notre expérimentation est un test à longue durée avec un temps de stress allant jusqu'à 2,000 heures. Cette thèse présente des résultats de mesure jusqu'à 230°C qui n'ont jamais été étudiés auparavant dans la littérature pour cette technologie.Les lois de vieillissement sont finalement intégrées dans un environnement de conception assistée par ordinateur (EDA) pour prédire l'évolution des paramètres électriques dégradés du transistor/circuit et l'estimation de la durée de vie en conséquence des effets du vieillissement. De plus, le test de fiabilité au niveau du circuit a été réalisé pour valider et vérifier les modèles de vieillissement proposés. Cette approche offre la possibilité d'évaluer et de simuler la dérive de spécification du CI due à l'effet du vieillissement dans la phase de conception précoce
In the past decades, the demand for complicated functionality and high-density integration for Integrated Circuits (ICs) has resulted in metal-oxide-silicon (MOS) devices' scaling down. In this scenario, the reliability problems are the considerable concerns due to the device miniaturization, such as Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) that seriously impact the device performance. In some application fields where the cost of failure is extremely high such as space, oilfield, or healthcare, the device must be able to stably and reliably work, especially at an extensive temperature range. Although device failure mechanisms have been intensively investigated in the past, the investigations of these mechanisms at high temperatures are seldom studied.This thesis aims to develop the aging laws for 0.18µm CMOS technology to optimize circuit design for a targeted lifetime under extreme temperatures. We conducted an intensive aging test campaign for both nMOS and pMOS featuring several gate lengths. The intrinsic HCI and BTI mechanisms were characterized and modeled under typical operating voltage biases to avoid the risk of overaccelerating other wear-out mechanisms that are not supposed to be experienced in practical application. Our experiment is a long-term test with a stress time of up to 2,000 hours. This thesis presents measurement results up to 230°C that have never been studied before in the literature for this technology.The aging laws are finally integrated into an electronic design automation (EDA) environment to predict the evolution of the degraded transistor/circuit electrical parameters and the lifetime estimation due to the aging effects. In addition, the reliability test at the circuit level has been performed to validate and verify the proposed aging models. This approach offers the possibility to assess and simulate the IC specification drift due to the aging effect in the early design phase and optimize the circuit design over lifetime
7

Loayza, Ramirez Jorge Miguel. "Study and characterization of electrical overstress aggressors on integrated circuits and robustness optimization of electrostatic discharge protection devices." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI044.

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Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citées
This Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement
8

Xuan, Xiangdong. "Analysis and design of reliable mixed-signal CMOS circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08032004-185515/unrestricted/xuan%5Fxiangdong%5F200412%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.
9

Qin, Jin. "A new physics-of-failure based VLSI circuits reliability simulation and prediction methodology." College Park, Md. : University of Maryland, 2007. http://hdl.handle.net/1903/7410.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Reliability Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
10

Lahbib, Insaf. "Contribution à l'analyse des effets de vieillissement de composants actifs et de circuits intégrés sous contraintes DC et RF en vue d'une approche prédictive." Thesis, Normandie, 2017. http://www.theses.fr/2017NORMC256.

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Les travaux de cette thèse portent sur la simulation de la dégradation des paramètres électriques des transistors MOS et bipolaires sous stress statiques et dynamiques. Cette étude a été menée à l’aide d’un outil de simulation de fiabilité développé en interne. Selon la technologie MOS ou bipolaire, les mécanismes étudiés ont été successivement : Hot Carrier Injection, Bias Temperature instability, Mixed Mode et Reverse base emitter bias. L’investigation a été aussi étendue au niveau circuit. Nous nous sommes ainsi intéressés à l’effet de la dégradation des transistors sur la fréquence d’un oscillateur en anneau et les performances RF d’un amplificateur faible bruit. Les circuits ont été soumis à des contraintes DC , AC et RF. La prédictibilité, établie de ces dégradations, a été validée par des essais de vieillissement expérimentaux sur des démonstrateurs encapsulés et montés sur PCB. Les résultats de ces études ont permis de valider la précision du simulateur et la méthode de calcul quasi-statique utilisée pour calculer les dégradations sous stress dynamiques. Ces travaux de recherche ont pour but d’inscrire cette approche prédictive dans un flot de conception de circuits afin d’assurer leur fiabilité
The work of this thesis focuses on the simulation of the electrical parameters degradation of MOS and bipolar transistors under static and dynamic stresses. This study was conducted using an in-house reliability simulation tool. According to the MOS or bipolar technology, the studied mechanisms were successively: Hot Carrier Injection, Bias Temperature instability, Mixed Mode and Reverse base emitter bias. The investigation was then extended to circuit-level. The effect of transistors degradation on a ring oscillator frequency and the RF performances of a low noise amplifier were investigated. The circuits were subjected to DC, AC and RF constraints. Predictability of these degradations has been validated by experimental aging tests on encapsulated and PCB-mounted demonstrators. The results of these studies proved the accuracy of the simulator and validated the quasi-static calculation method used to predict the degradation under dynamic stress. The goal of this research is to embed this predictive approach into a circuit design flow to ensure its reliability
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Книги з теми "Circuit reliability simulation":

1

Liu, S. Modeling and simulation for microelectronic packaging assembly: Manufacture, reliability, and testing. Hoboken, N.J: Wiley, 2011.

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2

Billinton, Roy. Reliability assessment of electric power systems using Monte Carlo methods. New York: Plenum Press, 1994.

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3

Lawday, Geoff. A signal integrity engineer's companion: Real-time test and measurement and design simulation. Upper Saddle River, NJ: Prentice Hall, 2008.

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4

Lawday, Geoff. A signal integrity engineer's companion: Real-time test and measurement and design simulation. Upper Saddle River, NJ: Prentice Hall, 2008.

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5

Y, Tsui Paul G., ed. Hot-carrier circuit reliability simulation. Reading, Mass: Addison-Wesley, 1992.

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6

J, Melcher Kevin, and United States. National Aeronautics and Space Administration., eds. A sensor failure simulator for control system reliability studies. [Washington, DC]: National Aeronautics and Space Administration, 1986.

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7

Voldman, Steven H. Esd: Computer Aided Design and Simulation. Wiley & Sons, Limited, John, 2023.

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Частини книг з теми "Circuit reliability simulation":

1

Leblebici, Yusuf, and Sung-Mo Kang. "Transistor-Level Simulation for Circuit Reliability." In Hot-Carrier Reliability of MOS VLSI Circuits, 111–42. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3250-7_5.

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2

Leblebici, Yusuf, and Sung-Mo Kang. "Fast Timing Simulation for Circuit Reliability." In Hot-Carrier Reliability of MOS VLSI Circuits, 143–63. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3250-7_6.

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3

Golanbari, Mohammad Saber, Mojtaba Ebrahimi, Saman Kiamehr, and Mehdi B. Tahoori. "Selective Flip-Flop Optimization for Circuit Reliability." In Dependable Embedded Systems, 337–64. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_14.

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AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.
4

Gadelrab, Serag M., and James A. Barby. "Creative Methods of Leveraging VHDL-AMS-like Analog-HDL Environments. Case Study: Simulation of Circuit Reliability." In Analog VHDL, 69–84. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5753-1_7.

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5

Vasileska, Dragica, and Nabil Ashraf. "Atomistic Simulations on Reliability." In Circuit Design for Reliability, 47–67. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-4078-9_4.

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6

Sutaria, Ketul B., Jyothi B. Velamala, Venkatesa Ravi, Gilson Wirth, Takashi Sato, and Yu Cao. "Multilevel Reliability Simulation for IC Design." In Bias Temperature Instability for Devices and Circuits, 719–49. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-7909-3_28.

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7

Wang, Zuowei, Hong Zhang, Dongchao Liu, Shiping E., Kanjun Zhang, Haitao Li, Hengxuan Li, and Zhigang Chen. "New Principle of Fault Data Synchronization for Intelligent Protection Based on Wavelet Analysis." In Proceeding of 2021 International Conference on Wireless Communications, Networking and Applications, 850–61. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2456-9_87.

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AbstractIn order to eliminate the influence of the delay error of the sampled value in the data link on the longitudinal differential protection device, this paper proposes a protection data self-healing synchronization algorithm based on wavelet transform to calculate the moment of sudden change. First, calculate the mutation amount of the sampled data at each end in real time. When the mutation amount threshold is exceeded, it is determined that the multi-terminal system has a short-circuit fault. Then, according to the sudden change characteristics of the collected current waveform, the wavelet modulus maximum value is used to extract the fault sudden change time of each end data, based on the fault time at one terminal, the automatic compensation for the time differences between this terminal and others are realized, thus a new sampling sequence is formed. The resynchronized sampling sequences are used to calculate the differential current and braking current after fault to ensure the correct action of the protective device. Through theoretical analysis and simulations, the correctness and effectiveness of the proposed algorithm is verified; in addition, it is shown that this algorithm can improve the reliability of actions by the intelligent protection device, thus realizing protections such as multi-terminal differential, wide-area differential, etc.
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Ferreira, Pietro M., Hao Cai, and Lirida Naviner. "Reliability Aware AMS/RF Performance Optimization." In Advances in Computer and Electrical Engineering, 28–54. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6627-6.ch002.

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Reliability has become an important issue in the continuously CMOS technology scaling down. The exploration of the technology limits using classic performance optimization techniques and leads to the best trade-off for the area, power consumption, and speed. Nevertheless, such key characteristics have been degraded in a context of continuous use and stressful environment. Thus, circuit reliability emerges as a design criterion for AMS/RF performance optimization. Aiming a design for reliability, this chapter presents an overview of CMOS unreliable phenomena. Reliability-aware methodologies for circuit design, simulation, and optimization are reviewed. The authors focus in particular on large and complex systems, providing circuit design insights to achieve a reliability specification from system-level to transistor-level. They highlight the more sensitive building blocks in CT S? modulator and demonstrate how performance is affected by unreliable phenomena. A system-level direct-conversion RF front-end design is described in top-down approach. Electrical simulations are presented with 65 nm CMOS technology.
9

Kamboj, Vikram Kumar, Kamalpreet Sandhu, and Shamik Chatterjee. "Modelling Analysis and Simulation for Reliability Prediction for Thermal Power System." In AI Techniques for Reliability Prediction for Electronic Components, 136–63. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1464-1.ch008.

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The size of the power system is growing exponentially due to heavy demand of power in all the sectors (e.g., agricultural, industrial, and commercial). Due to this, the chance of failure of individual units leading to practical or complete collapse of power supply is common to be encountered. The reliability of power system is therefore the most important feature to be maintained above some acceptable threshold value. Furthermore, the maintenance of individual units can also be planned and implemented once the level of reliability for given instant of time is known. The proposed research therefore aims at determining the threshold reliability of generation system. The generation system consists of boiler, water, blade angle in turbine, shaft coupling, excitation system, generator winding, circuit breaker, and relay. This chapter presents the mathematical model of reliability of individual components and equivalent reliability of the entire generation system. It suggests the approach to determine the critical reliability of both individual and equivalent reliability of the generation system.
10

Baccari, Silvio, Giulio Cammeo, Christian Dufour, Luigi Iannelli, Vincenzo Mungiguerra, Mario Porzio, Gabriella Reale, and Francesco Vasca. "Real-Time Hardware-in-the-Loop in Railway." In Railway Safety, Reliability, and Security, 221–48. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-1643-1.ch010.

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The increasing complexity of modern ground vehicles is making crucial the role of control for improving energetic efficiency, comfort and performance. At the same time, the control software must be frequently updated in order to let the vehicle respond safely and efficiently within more sophisticated environments and to optimize the operations when new vehicle components are integrated. In this framework real-time hardware-in-the-loop simulations represent a fundamental tool for supporting the verification and validation processes of the control software and hardware. In this chapter a railway case study will be presented. The mathematical models of the most relevant electromechanical components of the vehicle powertrain are presented: the pantograph connected to an ideal overhead line with continuous voltage; the electrical components of a pre-charge circuit, the line filter and the braking chopper; the three-phase voltage source inverter and the induction motor; and, finally, the mechanical transmission system, including its interactions with the rail. Then the issues related to the real-time simulation of the locomotive components models are discussed, concentrating on challenges related to the stiff nature of the dynamic equations and on their numerical integration by combining field programmable gate array (FPGA) and central processing unit (CPU) boards. The usefulness of the real-time hardware-in-the-loop simulations for the analysis of railway control software will be demonstrated by considering the powertrains of two real metropolitan trains under complex scenarios, i.e., stator winding disconnection of the induction motor, pantograph missing contact, wheel-rail slipping phenomenon.

Тези доповідей конференцій з теми "Circuit reliability simulation":

1

Jeng, Min-Chie, Cheng Hsiao, Ke-Wei Su, and Chung-Kai Lin. "Circuit reliability simulation using TMI2." In 2013 IEEE Custom Integrated Circuits Conference - CICC 2013. IEEE, 2013. http://dx.doi.org/10.1109/cicc.2013.6658491.

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2

Tan, Cher Ming. "Electromigration simulation at circuit levels." In 2014 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2014. http://dx.doi.org/10.1109/irps.2014.6860656.

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3

Kole, M. "Circuit reliability simulation based on Verilog-A." In 2007 IEEE International Behavioral Modeling and Simulation Workshop. IEEE, 2007. http://dx.doi.org/10.1109/bmas.2007.4437525.

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4

Sasse, Guido. "Device degradation models for circuit reliability simulation." In 2013 IEEE International Integrated Reliability Workshop (IIRW). IEEE, 2013. http://dx.doi.org/10.1109/iirw.2013.6804152.

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5

Aitken, Rob. "Special Session 4: Reliability and Circuit Simulation." In 14th IEEE International On-Line Testing Symposium. IEEE, 2008. http://dx.doi.org/10.1109/iolts.2008.69.

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6

Aur, S. "Kinetics of Hot Carrier Effects for Circuit Simulation." In 27th International Reliability Physics Symposium. IEEE, 1989. http://dx.doi.org/10.1109/irps.1989.363367.

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7

Hu, Ning, and Jinyong Huang. "Application of circuit fault simulation in reliability disign." In 2014 International Conference on Reliability, Maintainability and Safety (ICRMS). IEEE, 2014. http://dx.doi.org/10.1109/icrms.2014.7107346.

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8

Quader, Khandker N., Ping K. Ko, Chenming Hu, Peng Fang, and John T. Yue. "Simulation of CMOS Circuit Degradation due To Hot-Carrier Effects." In 30th International Reliability Physics Symposium. IEEE, 1992. http://dx.doi.org/10.1109/irps.1992.363266.

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9

Di Sarro, James, and Elyse Rosenbaum. "A scalable SCR compact model for ESD circuit simulation." In 2008 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2008. http://dx.doi.org/10.1109/relphy.2008.4558895.

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10

Lifang Lou and Juin J. Liou. "Acomprehensive compact SCR model for CDM ESD circuit simulation." In 2008 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2008. http://dx.doi.org/10.1109/relphy.2008.4558963.

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