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Добірка наукової літератури з теми "Flip-flop (electronics)"

Автор: Grafiati

Опубліковано: 23 червня 2022

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Статті в журналах з теми "Flip-flop (electronics)"

Mathis, Wolfgang. "100 years multivibrator-history, circuits and mathematical analysis." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 39, no. 3 (2020): 725–37. http://dx.doi.org/10.1108/compel-10-2019-0411.

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Purpose This work is intended to historically commemorate the one hundredth anniversary of the invention of a new type of electronic circuit, referred to in 1919 by Abraham and Bloch as a multivibrator and by Eccles and Jordan as a trigger relay (later known as a flip-flop). Design/methodology/approach The author also considers the circuit-technical side of this new type of circuit, considering the technological change as well as the mathematical concepts developed in the context of the analysis of the circuit. Findings The multivibrator resulted in a “circuit shape” which became one of the most applied nonlinear circuits in electronics. It is shown that at the beginning the multivibrator as well as the flip-flop circuits were used because their interesting properties in the frequency domain. Originality/value Therefore, it is a very interesting subject to consider the history of the multivibrator as electronic circuits in different technologies including tube, transistors and integrated circuits as well as the mathematical theory based on the concept from electrical circuit theory.

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Lin, Dave Y. W., and Charles H. P. Wen. "A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (2021): 1–12. http://dx.doi.org/10.1145/3462171.

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As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

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Ragavendran, U., and M. Ramachandran. "Low Power and Low Complexity Flip-Flop Design using MIFGMOS." International Journal of Engineering & Technology 7, no. 3.1 (2018): 183. http://dx.doi.org/10.14419/ijet.v7i3.1.17233.

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Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.

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Guo, Wei Jia, Shu Bao Wang, Gui Jing Mei, and Xiu Mei Zhang. "Swift Self-Starting Design of Sequential Logic Circuit Based on Karnaugh Map." Applied Mechanics and Materials 220-223 (November 2012): 1008–11. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.1008.

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To make the circuit self-start swiftly in the environment with much disturbance, according to the principle of being propitious to simplify state equation and output equation, assigned a next state for each bound term on Karnaugh map, and the next state must be a state of the valid cycle, at last tested the method by simulation. In the simulation, imitated the disturbance by the set pin or reset pin of flip-flop. The simulation based on electronics workbench 5.0C shows the effectiveness and feasibility of the method.

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Rompis, Lianly. "A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER." Jurnal Ilmiah Realtech 14, no. 1 (2018): 64–68. http://dx.doi.org/10.52159/realtech.v14i1.118.

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Mostly some specific computer circuits and digital circuit applications need a random counter circuit module for handling specific tasks or operations. To design this kind of circuit, it is more common to use the standard format design of synchronous counter, although this will be more complicated to derive its truth table and karnaugh-maps in order to solve the right output equations for flip-flop inputs. This paper will introduce another way of designing a digital random counter, using shift register and encoder, which is easier to applied and the sequence of this counter can be managed randomly. The methodology being used for this research is mainly tounderstand the basic concept and combine the functions of shift register and encoder, to derive a new and simple form of designing a random counter. Using an Electronics Workbench software, the outputs are shown in logic simulation.

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Rahman, Aminur, Ian Jordan, and Denis Blackmore. "Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops." Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 474, no. 2209 (2018): 20170111. http://dx.doi.org/10.1098/rspa.2017.0111.

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It has been observed through experiments and SPICE simulations that logical circuits based upon Chua’s circuit exhibit complex dynamical behaviour. This behaviour can be used to design analogues of more complex logic families and some properties can be exploited for electronics applications. Some of these circuits have been modelled as systems of ordinary differential equations. However, as the number of components in newer circuits increases so does the complexity. This renders continuous dynamical systems models impractical and necessitates new modelling techniques. In recent years, some discrete dynamical models have been developed using various simplifying assumptions. To create a robust modelling framework for chaotic logical circuits, we developed both deterministic and stochastic discrete dynamical models, which exploit the natural recurrence behaviour, for two chaotic NOR gates and a chaotic set/reset flip-flop. This work presents a complete applied mathematical investigation of logical circuits. Experiments on our own designs of the above circuits are modelled and the models are rigorously analysed and simulated showing surprisingly close qualitative agreement with the experiments. Furthermore, the models are designed to accommodate dynamics of similarly designed circuits. This will allow researchers to develop ever more complex chaotic logical circuits with a simple modelling framework.

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Prema, S., N. Karthikeyan, and S. Karthik. "Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications." Journal of Medical Imaging and Health Informatics 11, no. 12 (2021): 3215–22. http://dx.doi.org/10.1166/jmihi.2021.3919.

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To adapt to varied working situations, the latest biomedical imaging applications require low energy consumption, high performance, and extensive energy-performance scalability. State-of-the-art electronics with higher sensitivity, higher counting rate, and finer time resolution are required to create higher precision, higher temporal resolution, and maximum contrast biomedical images. In recent days, the system’s power consumption is important critically in modern VLSI circuits particularly for the low power application. In order to decrease the power, a power optimization technique must be used at various design levels. The low power use of logic cells is a proficient technique for decreasing the circuit level power. Dual Feedback edge triggered Flip Flop (DFETFF) is considered for biomedical imaging applications in the proposed system. Initially, the high dynamic range voltage is given as input signal. The comparator output is then retried at the comparator end. The integration capacitor is employed for storing remaining voltage signal. The comparator voltage is then given to the capacitor reset block. In the proposed work, a capacitor-reset block that employs clock signal takes up a dual-feedbackedge-triggered Flip-flop as an alternative of a conventional type for reducing the final output signals errors. Dual feedback loops assure that feedback loops do not tri-state at the time of SET restoration, a scheme that could lead to SEUs in latches if a single delay component and a single feedback loop are used. In digital system, Clock gating is a competent method of lessening the overall consumption of power along with deactivating the clock signal selectively and is useful for controlling the usage of clock signal asynchronously in reference to input-signal current. The integration-control (Vint) signal is employed in controlling the integration time. On the termination of integration, the signal level phase is kept, also similar one is send to arrangement all through read period. As a result, the simulation was carried out after the design layout and the estimations of performance were made and are compared with traditional approaches to prove the proposed mechanism effectiveness for future biomedical applications.

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Hassan, Ahmad, Jean-Paul Noël, Yvon Savaria, and Mohamad Sawan. "Circuit Techniques in GaN Technology for High-Temperature Environments." Electronics 11, no. 1 (2021): 42. http://dx.doi.org/10.3390/electronics11010042.

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As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilling. More than 15 integrated circuits were implemented and tested. We performed the HT characterization of passive elements integrated in GaN500 including resistors, capacitors, and inductors up to 600 °C. Moreover, we developed for the first time several digital circuits based on GaN500 technology, including logic gates (NOT, NAND, NOR), ring oscillators, D Flip-Flop, Delay circuits, and voltage reference circuits. The tested circuits are fabricated on a 4 mm × 4 mm chip to validate their functionality over a wide range of temperatures. The logic gates show functionality at HT over 400 °C, while the voltage reference circuits remain stable up to 550 °C.

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Wang, An Jing, and Yu Zhuo Fu. "Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact." Applied Mechanics and Materials 716-717 (December 2014): 1239–43. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1239.

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Recently, Multi-bit flip-flop usage has shown its advantage in dynamic power saving in nowadays commercial electronic design. This paper present a more comprehensive comparison of chip-level synthesis result by using single-bit flip-flop and multi-bit flip-flop standard cell and except for analyzing the power and area benefit from replacement under the maximum speed, this paper give a compromise solution to solve that using multi-bit flip-flop cannot run as the fastest as single-bit with even large area. The trade-off between a multi-bit flip-flop cell driving strength and its area when designing multi-bit standard cell that will greatly influence synthesis result as speed arise are also mentioned. Finally, this research about MBFF further usage improvements may be helpful for designers to know how to take full advantage of multi-bit flip-flops to bring about the wanted benefit.

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Komshina, A., S. Telibaev, and B. S. Mikhlin. "ASSEMBLING THE RS FLIP-FLOP ON CHIPS CONTAINING ELEMENTS OF "OR-NOT", "AND-NOT"." Informatics in school, no. 7 (November 17, 2018): 17–25. http://dx.doi.org/10.32517/2221-1993-2018-17-7-17-25.

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The article provides general information about flip-flops, their types, about an asynchronous RS flip-flop. A detailed description of the practical work on assembling the RS flip-flop in two variants is given, based on a chip containing four "2OR-NOT" elements, and based on a chip containing four "2AND-NOT" elements. The details from the electronic set "Micronik" ("Amperka") and the details provided by the site "Let's create together" are used in assembling.

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Більше джерел

Дисертації з теми "Flip-flop (electronics)"

Yongyi, Yuan. "Investigation and implementation of data transmission look-ahead D flip-flops." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2529.

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This thesis investigates four D flip-flops with data transmission look-ahead circuits. Based on logical effort and power-delay products to resize all the transistor widths along the critical path in µm CMOS technology. The main goal is to verify and proof this kind of circuits can be used when the input data have low switching probabilities. From comparing the average energy consumption between the normal D flip-flops and D flip-flops with look-ahead circuits, D flip-flops with look-ahead circuits consume less power when the data switching activities are low.

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Johansson, Kenny. "Low Complexity and Low Power Bit-Serial Multipliers." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1751.

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Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital devices low power consumption is always desirable. How to attain this in bit-serial multipliers is a complex problem. The aim of this thesis was to find a strategy on how to implement bit-serial multipliers with as low cost as possible. An important step was achieved by deriving formulas that can be used to calculate the carry switch probability in the adders/subtractors. It has also been established that it is possible to design a power model that can be applied to all possible structures of bit- serial multipliers.

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Hansson, Martin. "Low-Power Multi-GHz Circuit Techniques for On-chip Clocking." Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.

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Jovanovic, Natalija. "Bascules et registres non-volatiles à base de ReRAM en technologies CMOS avancées." Electronic Thesis or Diss., Paris, ENST, 2016. http://www.theses.fr/2016ENST0023.

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Les mémoires et l'éléments séquentiels non-volatiles peuvent améliorer l'efficacité énergétique des appareils à piles en éliminant la consommation statique tout en maintenant l'état du système.Parmi les nouvelles technologies NVM intégrées, ReRAMs se distinguent par un temps de programmation rapide, une structure simple, compatible avec la technologie CMOS et très bien scalable. Les flip-flops non-volatiles (NVFF) basées sur ReRAM ont été implémentées dans des nœuds CMOS de 90nm ou plus et souffrent de problèmes de fiabilité dans les nœuds plus petits, en raison de hautes tensions de programmation et de formation. Cette thèse fait l'analyse de la conception robuste et fiable non volatile dans le nœud CMOS 28nm et ci-dessous. Elle présente deux nouvelles solutions de conception pour la programmation de dispositifs ReRAM. Les circuits de programmation sont appliqués en architecture NVFF qui utilise deux dispositifs ReRAM (2R). Une architecture alternative (1R) est également proposée afin d'obtenir une densité plus élevée et une consommation plus faible. Les solutions NVFF sont optimisées pour les conditions de programmation ReRAM qui améliorent l'endurance et minimisent la puissance necessaire pour la programmation. L'analyse statistique de la structure du FF et de son optimisation a été réalisée, afin d'évaluer les meilleures architectures de fonctionnement de restauration. Les NVFF sont implémentés en FDSOI CMOS 28nm et comparés à un FF d'une bibliothèque standard. Enfin, pour minimiser la surcharge de la zone NVFF sans affecter la robustesse des opérations non volatiles, un Fichier de registres non-volatils multi-ports (NVRF) basé sur la solution 1R NVFF est proposé Non-volatile memories and flip-flops can improve the energy efficiency in battery-operated devices by eliminating the sleep-mode consumption, while maintaining the system state. Among emerging embedded NVM technologies, ReRAMs differentiate itself with a fast programming time, a simple CMOS-compatible structure and a good scalability. Previously proposed ReRAM-based non-volatile flip-flops (NVFF) have been implemented in 90nm or older CMOS nodes and suffer from CMOS reliability issues in scaled nodes due to high programming and forming voltages. This thesis makes the analysis of robust and reliable non-volatile design in 28nm CMOS node and below. It presents two novel thin-gate oxide CMOS design solutions for the programming of ReRAM devices. The programming circuits are applied in dual-voltage NVFF architecture which employs two ReRAM devices (2R). Alternative 1R NVFF architecture is also proposed in order to achieve higher density and lower consumption. With regard to the existing ReRAM technologies, given NVFF solutions are optimized for ReRAM programming conditions which improve endurance and minimize programming power. Statistical analysis of the FF core and its optimization was performed, to evaluate the best restore operation architectures which meet digital CMOS circuit design yield requirements. The NVFFs are implemented in 28nm CMOS FDSOI and benchmarked against a master slave flip-flop from a standard library and a data-retention flip-flop. Finally, to minimize the NVFF area overhead without impacting the robustness of \nv{} operations, multi-port non-volatile register file (NVRF) based on the 1R NVFF solution is proposed

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Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.

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Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.

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Jagirdar, Aditya. "Novel flip-flop designs tolerant to soft-errors and crosstalk effects." 2007. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.16402.

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Jadidi, Tayebeh. "In-silico Modeling of Lipid-Water Complexes and Lipid Bilayers." Doctoral thesis, 2013. https://repositorium.ub.uni-osnabrueck.de/handle/urn:nbn:de:gbv:700-2013102111709.

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In the first part of the thesis, the molecular structure and electronic properties of phospholipids at the single molecule level and also for a monolayer structure are investigated via ab initio calculations under different degrees of hydration. The focus of the study is on phosphatidylcholines, in particular dipalmitoylphosphatidylcholine (DPPC), which are the most abundant phospholipids in biological membranes. Upon hydration, the phospholipid shape into a sickle-like structure. The hydration dramatically alters the surface potential, dipole and quadrupole moments of the lipids, and probably guides the interactions of the lipids with other molecules and the communication between cells. The vibrational spectrum of DPPC and DPPC-water complexes are completely assigned and it is shown that water hydrating the lipid head groups enables efficient energy transfer across membrane leaflets on sub-picosecond time scales. Moreover, the vibrational modes and lifetimes of pure and hydrated DPPC lipids, at human body temperature, are estimated by performing ab initio molecular dynamics simulations. The vibrational modes of the water molecules close to the head group of DPPC are active in the frequency range between 0.5 - 55 THz, with a peak at 2.80 THz in the energy spectrum. The computed lifetimes for the high-frequency modes agree well with recent data measured at room temperature, where high-order phonon scattering is not negligible. The structure and auto-ionization of water at the water-phospholipid interface are investigated by ab initio molecular dynamics and ab initio Monte Carlo simulations using local density approximation and generalized gradient approximation for the exchange-correlation energy functional. Depending on the lipid head group, strongly enhanced ionization is observed, leading to dissociation of several water molecules into H+ and OH- per lipid. The results can shed light on the phenomena of the high proton conductivity along membranes that has been reported experimentally. In the second part of the thesis, Monte Carlo simulations of the lipid bilayer, on the basis of a coarse grained model, are performed to gain insight into the mechanical properties of planar lipid bilayers. By using a rescaling method, the Poisson's ratio is calculated for different phases. Additional information on the bending rigidity, determined from height fluctuations on the basis of the Helfrich Hamiltonian, allows for calculation of the Young's modulus for each phase. In addition, the free energy barrier for lipid flip-flop process in the fluid and gel phases are estimated. The main rate-limiting step to complete a flip-flop process is related to a free energy barrier that has to be crossed in order to reach the center of the bilayer. The free energy cost for performing a lipid flip-flop in the gel phase is found to be five times greater than in the fluid phase, demonstrating the rarity of such events in the gel phase. Moreover, an energy barrier is estimated for formation of transient water pores that often precedes lipid translocation events and accounts for the rate-limiting step of these pore-associated lipid translocation processes.

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Книги з теми "Flip-flop (electronics)"

Steel, Duncan G. Introduction to Quantum Nanotechnology. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780192895073.001.0001.

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Quantum physics is rapidly emerging as a transformative approach to expand the frontiers of technology in areas including communications, information processing, metrology, and sensing. Indeed, the end of Moore’s Law looms in the near future and quantum effects in modern electronics such as quantum tunneling are a limiting factor. In contrast, in new technology based on quantum behavior, the quantum properties represent a new dimension of opportunity. This shift is already creating a growing need for engineers and physical scientists who have specialized knowledge in this area, in order to contribute to the growing effort. There are numerous outstanding textbooks available for a general approach to the field of quantum physics. There is much to be gained by taking the traditional learning approach, but it can take two or three years before students encounter many of the exciting ideas and tools for this area. This book takes an application-motivated approach to enable students to build a quantum toolbox. The first six chapters describe the quantum states of various systems of interest, while the remaining chapters focus mainly on dynamics. Important concepts like the quantum flip-flop, based using Rabi oscillations, and engineering the quantum vacuum are presented. Powerful tools including the atomic operator approach and density matrix operator are introduced with examples of applications. This book is aimed at upper level undergraduates and some first year graduate students. The book is arranged to fulfil the needs for a one-semester or two-semester sequence. For a one-semester sequence, the preface describes several paths that emphasize different aspects of quantum behavior.

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Частини книг з теми "Flip-flop (electronics)"

Kumari, Reshmi, Sneha Pandey, Swarnima, and Surya Deo Choudhary. "Metastability Mitigation and Error Masking of High-Speed Flip-Flop." In Micro-Electronics and Telecommunication Engineering. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8721-1_52.

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Srivastava, Pragya, Ramsha Suhail, Richa Yadav, and Richa Srivastava. "Whistle-stop Low-power MCML technique to design Toggle Flip-Flop at nanoscale regime." In Recent Trends in Communication and Electronics. CRC Press, 2021. http://dx.doi.org/10.1201/9781003193838-86.

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Kotta, Satish, and Rajanbabu Mallavarapu. "Novel Design of Pulse Trigger Flip-Flop with High Speed and Power Efficiency." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_25.

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"Latch and Flip-Flop." In Digital Electronics 2. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119329756.ch1.

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Crowe, John, and Barrie Hayes-Gill. "Flip-flops and flip-flop based circuits." In Introduction to Digital Electronics. Elsevier, 1998. http://dx.doi.org/10.1016/b978-034064570-3/50008-3.

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"HOW TO MAKE A D TYPE FLIP FLOP FROM BASIC GATES." In Computer Electronics. Elsevier, 1985. http://dx.doi.org/10.1016/b978-0-434-98405-3.50023-x.

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"Radiation hard circuit design: flip-flop and SRAM." In VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects. Institution of Engineering and Technology, 2019. http://dx.doi.org/10.1049/pbcs073g_ch12.

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"The impact of Negative Bias Temperature Instability (NBTI) effect on D flip-flop." In Electronics and Electrical Engineering. CRC Press, 2015. http://dx.doi.org/10.1201/b18443-50.

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Тези доповідей конференцій з теми "Flip-flop (electronics)"

Kim, Min-su, Bai-Sun Kong, Chil-Gee Lee, Tae-Hyung Kim, Sung Bae Park, and Young-Hyun Jun. "Nonoverlapping Cuspid-Pulsed Flip-Flop." In 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07). IEEE, 2007. http://dx.doi.org/10.1109/icecs.2007.4510954.

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Nagesh, B., and B. S. Nikhil Chandra. "Designof Efficient Scan Flip-Flop." In 2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT). IEEE, 2021. http://dx.doi.org/10.1109/rteict52294.2021.9573924.

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Joachim, C., G. Treboux, and H. Tang. "A model conformational flip-flop molecular switch." In Molecular electronics—Science and Technology. AIP, 1992. http://dx.doi.org/10.1063/1.42677.

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Stipcevic, Mario. "Random flip-flop and its applications." In 2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO). IEEE, 2014. http://dx.doi.org/10.1109/mipro.2014.6859784.

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Wang, Danni, Sumitha George, Ahmedullah Aziz, Suman Datta, Vijaykrishnan Narayanan, and Sumeet K. Gupta. "Ferroelectric Transistor based Non-Volatile Flip-Flop." In ISLPED '16: International Symposium on Low Power Electronics and Design. ACM, 2016. http://dx.doi.org/10.1145/2934583.2934603.

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Sharma, Manisha, K. G. Sharma, Tripti Sharma, B. P. Singh, and Neha Arora. "SET D-flip flop design for portable applications." In 2010 India International Conference on Power Electronics (IICPE). IEEE, 2011. http://dx.doi.org/10.1109/iicpe.2011.5728081.

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Brindha, B., V. S. Kanchana Bhaaskaran, C. Vinoth, V. Kavinilavu, and Samiappa Sakthikumaran. "Optimization of sense amplifier energy recovery flip-flop." In 2011 3rd International Conference on Electronics Computer Technology (ICECT). IEEE, 2011. http://dx.doi.org/10.1109/icectech.2011.5941614.

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Sadrossadat, Sayed Alireza, Minoo Mirsaeedi, Kumaraswamy Ponnambalam, and Mohab Anis. "Framework for statistical design of a flip-flop." In 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009). IEEE, 2009. http://dx.doi.org/10.1109/icecs.2009.5410810.

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Moradi, Farshad, Dag Wisland, Jens Kargaard Madsen, and Hamid Mahmoodi. "Flip-flop design using novel pulse generation technique." In 2012 19th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2012). IEEE, 2012. http://dx.doi.org/10.1109/icecs.2012.6463633.

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Sushma, R., and N. S. Murty. "Feedback Oriented XORed Flip-Flop Based Arbiter PUF." In 2018 Third International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT). IEEE, 2018. http://dx.doi.org/10.1109/iceeccot43722.2018.9001605.

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