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Добірка наукової літератури з теми "Flip-flop (electronics)"

Автор: Grafiati

Опубліковано: 23 червня 2022

Оновлено: 31 липня 2025

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Статті в журналах з теми "Flip-flop (electronics)"

K., Srilatha, Pujitha B., and V. Sirisha M. "Implementation of D Flip Flop using CMOS Technology." International Journal of Trend in Scientific Research and Development 4, no. 3 (2020): 624–26. https://doi.org/10.5281/zenodo.3892465.

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In this paper, D flip flop has been designed and layout simulated using 32nm technology. This schematic of d flip flop has been designed using and its equivalent layout is created using Micro wind tools. The performance has been Analysed and compared in terms of area and power and delay. These proposed circuits are investigated in terms of area and power consumption and delay. K. Srilatha | B. Pujitha | M. V. Sirisha "Implementation of D Flip-Flop using CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volum

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Gomathi, R., S. Gopalakrishnan, S. Ravi Chand, S. Selvakumaran, J. Jeffin Gracewell, and Kalivaraprasad B. "Design and Speed Analysis of Low Power Single and Double Edge Triggered Flip Flop with Pulse Signal Feed-Through Scheme." International Journal of Electrical and Electronics Research 10, no. 4 (2022): 1107–14. http://dx.doi.org/10.37391/ijeer.100456.

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Flip flop is a fundamental electrical design component. Most electrical designs incorporate memory and their corresponding designs. The consumer electronics or end users need mobility and extended battery backup to enhance design performance. The focus on any parameter in the system is to maximize the performance of the design. Here the task is to reduce the energy use of flip flop. Due to the increased frequency clock delivered to the networks within the design, the edge or level triggered by a flip flop will contribute to power consumption. Due to the short circuit power consumption between

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Surbhi, Vishwakarma, and Vinod Kapse Dr. "Design of Dual Pulsating Latch Flip Flop DPLFF using Novel Pulse Generator." International Journal of Trend in Scientific Research and Development 2, no. 2 (2018): 1713–18. https://doi.org/10.31142/ijtsrd12743.

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In this paper various flip flop structures have been studied. In all designs to reduce power consumption, the Pulse Generator circuitry should be in build along with the flip flop itself. If a pulse generator is included along with DPSCRFF structure, power consumption can be reduced. In this work a new design of flip flop, Double Pulse Latch Flip flop DPLFF is proposed. DPLFF eliminates unnecessary glitches, which consume more power. DPLFF consume less power for same delay as compared with other existing techniques, which is performing one of the fastest known flip flops. In serial operation a

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Mathis, Wolfgang. "100 years multivibrator-history, circuits and mathematical analysis." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 39, no. 3 (2020): 725–37. http://dx.doi.org/10.1108/compel-10-2019-0411.

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Purpose This work is intended to historically commemorate the one hundredth anniversary of the invention of a new type of electronic circuit, referred to in 1919 by Abraham and Bloch as a multivibrator and by Eccles and Jordan as a trigger relay (later known as a flip-flop). Design/methodology/approach The author also considers the circuit-technical side of this new type of circuit, considering the technological change as well as the mathematical concepts developed in the context of the analysis of the circuit. Findings The multivibrator resulted in a “circuit shape” which became one of the mo

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Lin, Dave Y. W., and Charles H. P. Wen. "A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (2021): 1–12. http://dx.doi.org/10.1145/3462171.

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As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF wi

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Ragavendran, U., and M. Ramachandran. "Low Power and Low Complexity Flip-Flop Design using MIFGMOS." International Journal of Engineering & Technology 7, no. 3.1 (2018): 183. http://dx.doi.org/10.14419/ijet.v7i3.1.17233.

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Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.

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Guo, Wei Jia, Shu Bao Wang, Gui Jing Mei, and Xiu Mei Zhang. "Swift Self-Starting Design of Sequential Logic Circuit Based on Karnaugh Map." Applied Mechanics and Materials 220-223 (November 2012): 1008–11. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.1008.

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To make the circuit self-start swiftly in the environment with much disturbance, according to the principle of being propitious to simplify state equation and output equation, assigned a next state for each bound term on Karnaugh map, and the next state must be a state of the valid cycle, at last tested the method by simulation. In the simulation, imitated the disturbance by the set pin or reset pin of flip-flop. The simulation based on electronics workbench 5.0C shows the effectiveness and feasibility of the method.

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Swathi, Prabhu, H. R. Unnathi, B. R. Chethan, R. Tejaswini, and A. O. Vaishnavi. "Review on multi bit flip-flop enhanced shift register: A low power solution for UART." i-manager’s Journal on Electrical Engineering 17, no. 2 (2023): 35. http://dx.doi.org/10.26634/jee.17.2.20432.

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This paper details the Verilog HDL- based design of UART modules. Developing UART with a shift register utilizing multibit flip-flops proves to be pragmatic strategy for contemporary VLSI circuits. This work supports not only asynchronous and serial communication but also aligns with essential objectives of minimizing power consumption and reducing overall circuit area. Such integration enhances data transmission efficiency while meeting crucial design considerations in modern electronics

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Rompis, Lianly. "A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER." Jurnal Ilmiah Realtech 14, no. 1 (2018): 64–68. http://dx.doi.org/10.52159/realtech.v14i1.118.

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Mostly some specific computer circuits and digital circuit applications need a random counter circuit module for handling specific tasks or operations. To design this kind of circuit, it is more common to use the standard format design of synchronous counter, although this will be more complicated to derive its truth table and karnaugh-maps in order to solve the right output equations for flip-flop inputs. This paper will introduce another way of designing a digital random counter, using shift register and encoder, which is easier to applied and the sequence of this counter can be managed rand

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Rahman, Aminur, Ian Jordan, and Denis Blackmore. "Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops." Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 474, no. 2209 (2018): 20170111. http://dx.doi.org/10.1098/rspa.2017.0111.

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It has been observed through experiments and SPICE simulations that logical circuits based upon Chua’s circuit exhibit complex dynamical behaviour. This behaviour can be used to design analogues of more complex logic families and some properties can be exploited for electronics applications. Some of these circuits have been modelled as systems of ordinary differential equations. However, as the number of components in newer circuits increases so does the complexity. This renders continuous dynamical systems models impractical and necessitates new modelling techniques. In recent years, some dis

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Більше джерел

Дисертації з теми "Flip-flop (electronics)"

Yongyi, Yuan. "Investigation and implementation of data transmission look-ahead D flip-flops." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2529.

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<p>This thesis investigates four D flip-flops with data transmission look-ahead circuits. Based on logical effort and power-delay products to resize all the transistor widths along the critical path in µm CMOS technology. The main goal is to verify and proof this kind of circuits can be used when the input data have low switching probabilities. From comparing the average energy consumption between the normal D flip-flops and D flip-flops with look-ahead circuits, D flip-flops with look-ahead circuits consume less power when the data switching activities are low.</p>

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Johansson, Kenny. "Low Complexity and Low Power Bit-Serial Multipliers." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1751.

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<p>Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital

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Hansson, Martin. "Low-Power Multi-GHz Circuit Techniques for On-chip Clocking." Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.

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Jovanovic, Natalija. "Bascules et registres non-volatiles à base de ReRAM en technologies CMOS avancées." Electronic Thesis or Diss., Paris, ENST, 2016. http://www.theses.fr/2016ENST0023.

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Les mémoires et l'éléments séquentiels non-volatiles peuvent améliorer l'efficacité énergétique des appareils à piles en éliminant la consommation statique tout en maintenant l'état du système.Parmi les nouvelles technologies NVM intégrées, ReRAMs se distinguent par un temps de programmation rapide, une structure simple, compatible avec la technologie CMOS et très bien scalable. Les flip-flops non-volatiles (NVFF) basées sur ReRAM ont été implémentées dans des nœuds CMOS de 90nm ou plus et souffrent de problèmes de fiabilité dans les nœuds plus petits, en raison de hautes tensions de programma

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Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.

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Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TK

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Jagirdar, Aditya. "Novel flip-flop designs tolerant to soft-errors and crosstalk effects." 2007. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.16402.

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Jadidi, Tayebeh. "In-silico Modeling of Lipid-Water Complexes and Lipid Bilayers." Doctoral thesis, 2013. https://repositorium.ub.uni-osnabrueck.de/handle/urn:nbn:de:gbv:700-2013102111709.

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In the first part of the thesis, the molecular structure and electronic properties of phospholipids at the single molecule level and also for a monolayer structure are investigated via ab initio calculations under different degrees of hydration. The focus of the study is on phosphatidylcholines, in particular dipalmitoylphosphatidylcholine (DPPC), which are the most abundant phospholipids in biological membranes. Upon hydration, the phospholipid shape into a sickle-like structure. The hydration dramatically alters the surface potential, dipole and quadrupole moments of the lipids, and probably

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Книги з теми "Flip-flop (electronics)"

Steel, Duncan G. Introduction to Quantum Nanotechnology. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780192895073.001.0001.

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Quantum physics is rapidly emerging as a transformative approach to expand the frontiers of technology in areas including communications, information processing, metrology, and sensing. Indeed, the end of Moore’s Law looms in the near future and quantum effects in modern electronics such as quantum tunneling are a limiting factor. In contrast, in new technology based on quantum behavior, the quantum properties represent a new dimension of opportunity. This shift is already creating a growing need for engineers and physical scientists who have specialized knowledge in this area, in order to con

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Частини книг з теми "Flip-flop (electronics)"

Kushwaha, Vinay, and Rathnamala Rao. "High-Speed Multiplexed Feedback D Flip-Flop." In Proceedings of Second International Conference on Computational Electronics for Wireless Communications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6661-3_35.

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Kumari, Reshmi, Sneha Pandey, Swarnima, and Surya Deo Choudhary. "Metastability Mitigation and Error Masking of High-Speed Flip-Flop." In Micro-Electronics and Telecommunication Engineering. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8721-1_52.

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Prakash, Amiya, and Priyanka Jain. "Optimization of leakage power consumption in D Flip-Flop using hybrid technique." In Advances in AI for Biomedical Instrumentation, Electronics and Computing. CRC Press, 2024. http://dx.doi.org/10.1201/9781032644752-4.

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Srivastava, Pragya, Ramsha Suhail, Richa Yadav, and Richa Srivastava. "Whistle-stop Low-power MCML technique to design Toggle Flip-Flop at nanoscale regime." In Recent Trends in Communication and Electronics. CRC Press, 2021. http://dx.doi.org/10.1201/9781003193838-86.

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Kotta, Satish, and Rajanbabu Mallavarapu. "Novel Design of Pulse Trigger Flip-Flop with High Speed and Power Efficiency." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_25.

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"Latch and Flip-Flop." In Digital Electronics 2. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119329756.ch1.

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Crowe, John, and Barrie Hayes-Gill. "Flip-flops and flip-flop based circuits." In Introduction to Digital Electronics. Elsevier, 1998. http://dx.doi.org/10.1016/b978-034064570-3/50008-3.

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"HOW TO MAKE A D TYPE FLIP FLOP FROM BASIC GATES." In Computer Electronics. Elsevier, 1985. http://dx.doi.org/10.1016/b978-0-434-98405-3.50023-x.

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"Radiation hard circuit design: flip-flop and SRAM." In VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects. Institution of Engineering and Technology, 2019. http://dx.doi.org/10.1049/pbcs073g_ch12.

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"The impact of Negative Bias Temperature Instability (NBTI) effect on D flip-flop." In Electronics and Electrical Engineering. CRC Press, 2015. http://dx.doi.org/10.1201/b18443-50.

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Тези доповідей конференцій з теми "Flip-flop (electronics)"

Madhuram, M., Bikkili Alekya Himabindu, M. Maheswari, and M. V. Subramanyam. "Design of CMOS D Flip-Flop with Different Supply Voltages." In 2025 8th International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2025. https://doi.org/10.1109/icoei65986.2025.11013666.

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H K, Akshayini, Amodini K, Jane Sharon R, and Shruthi M L J. "Modified Flip Flop with Two Phase Clocking for Low Power Consumption." In 2024 Third International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT). IEEE, 2024. http://dx.doi.org/10.1109/iceeict61591.2024.10718526.

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Yu, Ya-Cheng, and Shih-Hsu Huang. "Securing Finite State Machines through Obfuscation Modes and Diverse Flip-Flop Configurations." In 2024 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan). IEEE, 2024. http://dx.doi.org/10.1109/icce-taiwan62264.2024.10674645.

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Joy, Ancy, Anju Damodaran, and Jinsa Kuruvilla. "Optimization of Forced Sleep 4x4 Sram Array Using Delay Flip Flop." In 2025 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE). IEEE, 2025. https://doi.org/10.1109/iitcee64140.2025.10915248.

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Nadaf, Nazir, and Sonali Agrawal. "TSPC STC-DET Flip-Flop With Autogated Clock Gating For Low-Power." In 2024 8th International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2024. https://doi.org/10.1109/iceca63461.2024.10800954.

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Rawat, Akash, and Manoj Kumar. "Low Power CMOS Based Dual Edge Triggered Flip Flop Using LECTOR C-Element." In 2024 International Conference on Computer, Electronics, Electrical Engineering & their Applications (IC2E3). IEEE, 2024. https://doi.org/10.1109/ic2e362166.2024.10827394.

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Kumar, Vobulapuram Ramesh, Gedda Shyam, and B. Divya Madhuri. "Design of Positive Edge Triggered D Flip-Flop Using Quantum Dot Cellular Automata." In 2024 International Conference on Computer, Electronics, Electrical Engineering & their Applications (IC2E3). IEEE, 2024. https://doi.org/10.1109/ic2e362166.2024.10826622.

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Dhanasekar, S., K. A. Balasuriya, N. Blesson, M. Boopathi, S. Muthuraman, and D. Sathish Kumar. "Design of Low Power TG Based FinFET D-Flip Flop for Memory Cell Architecture." In 2025 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS). IEEE, 2025. https://doi.org/10.1109/sceecs64059.2025.10940975.

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Juveria, Syeda Hurmath, Shashank Rebelli, and J. Ajayan. "Investigation of Gate-Length Scaling Effects on the Thermal Reliability of 25T-TSPC Flip-Flop." In 2024 International Conference on Smart Electronics and Communication Systems (ISENSE). IEEE, 2024. https://doi.org/10.1109/isense63713.2024.10872273.

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Lee, Dongkwon, Sunghoon Kim, Minyoung Kang, et al. "A 1.22fJ/cycle 17T Pseudo-Static True Single-Phase Clock Flip-Flop in 14nm FinFET CMOS." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC). IEEE, 2024. http://dx.doi.org/10.1109/esserc62670.2024.10719564.

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