Готові списки джерел за темами / Germanium on insulator

Добірка наукової літератури з теми "Germanium on insulator"

Автор: Grafiati
Опубліковано: 8 травня 2022

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Зміст

  1. Статті в журналах
  2. Дисертації
  3. Книги
  4. Частини книг
  5. Тези доповідей конференцій

Статті в журналах з теми "Germanium on insulator":

1

Hoshi, Yusuke, Kentarou Sawano, Kohei Hamaya, Masanobu Miyao, and Yasuhiro Shiraki. "Formation of Tensilely Strained Germanium-on-Insulator." Applied Physics Express 5, no. 1 (December 19, 2011): 015701. http://dx.doi.org/10.1143/apex.5.015701.

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2

Tracy, Clarence J., Peter Fejes, N. David Theodore, Papu Maniar, Eric Johnson, Albert J. Lamm, Anthony M. Paler, Igor J. Malik, and Philip Ong. "Germanium-on-insulator substrates by wafer bonding." Journal of Electronic Materials 33, no. 8 (August 2004): 886–92. http://dx.doi.org/10.1007/s11664-004-0216-5.

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3

Morshed, Tahsin, Yuki Kai, Ryo Matsumura, Jong-Hyeok Park, Hironori Chikita, Taizoh Sadoh, and Abdul Manaf Hashim. "Formation of germanium (111) on graphene on insulator by rapid melting growth for novel germanium-on-insulator structure." Materials Letters 168 (April 2016): 223–27. http://dx.doi.org/10.1016/j.matlet.2016.01.056.

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4

Maeda, Tatsuro, Masayasu Nishizawa, Yukinori Morita, and Shinichi Takagi. "Role of germanium nitride interfacial layers in HfO2/germanium nitride/germanium metal-insulator-semiconductor structures." Applied Physics Letters 90, no. 7 (February 12, 2007): 072911. http://dx.doi.org/10.1063/1.2679941.

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5

Liu, Bin, Xiao Gong, Chunlei Zhan, Genquan Han, Hock-Chun Chin, Moh-Lung Ling, Jie Li, et al. "Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate." IEEE Transactions on Electron Devices 60, no. 6 (June 2013): 1852–60. http://dx.doi.org/10.1109/ted.2013.2258924.

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6

Chao, Y. L., S. Prussin, J. C. S. Woo, and R. Scholz. "Preamorphization implantation-assisted boron activation in bulk germanium and germanium-on-insulator." Applied Physics Letters 87, no. 14 (October 3, 2005): 142102. http://dx.doi.org/10.1063/1.2076440.

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7

Bao, Shuyu, Kwang Hong Lee, Cong Wang, Bing Wang, Riko I. Made, Soon Fatt Yoon, Jurgen Michel, Eugene Fitzgerald, and Chuan Seng Tan. "Germanium-on-insulator virtual substrate for InGaP epitaxy." Materials Science in Semiconductor Processing 58 (February 2017): 15–21. http://dx.doi.org/10.1016/j.mssp.2016.11.001.

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8

Bao, Shuyu, Kwang Hong Lee, Cong Wang, Bing Wang, Riko I. Made, Soon Fatt Yoon, Jurgen Michel, Eugene Fitzgerald, and Chuan Seng Tan. "Germanium-on-insulator virtual substrate for InGaP epitaxy." Materials Science in Semiconductor Processing 70 (November 2017): 17–23. http://dx.doi.org/10.1016/j.mssp.2017.07.012.

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9

Seo, J. W., Ch Dieker, A. Tapponnier, Ch Marchiori, M. Sousa, J. P. Locquet, J. Fompeyrine, et al. "Epitaxial germanium-on-insulator grown on (001) Si." Microelectronic Engineering 84, no. 9-10 (September 2007): 2328–31. http://dx.doi.org/10.1016/j.mee.2007.04.019.

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10

Ferreira da Silva, A. "Metal-insulator transitions in doped silicon and germanium." Physical Review B 37, no. 9 (March 15, 1988): 4799–800. http://dx.doi.org/10.1103/physrevb.37.4799.

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Статті в журналах Дисертації

Дисертації з теми "Germanium on insulator":

1

Hennessy, John 1980. "Germanium on insulator fabrication technology." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28556.

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Анотація:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 53-55).
As CMOS devices continue to scale to smaller dimensions, it has become clear that new materials and structures are needed to also continue to improve performance. Germanium on insulator is proposed as it combines both a high mobility material (relative to silicon) and a structure with improved scaling characteristics compared to bulk devices. The goal of this work is to develop of procedure for the transfer of a germanium layer to bulk silicon by means of wafer bonding and hydrogen-induced layer transfer.
by John Hennessy.
S.M.
2

Gay, Diane Lorraine. "Silicon on insulator fabrication using silicon germanium etch stop and polish stop techniques." Thesis, Queen's University Belfast, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.388096.

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3

Kah, Masamba. "Comparative study of boron activation in silicon, silicon-on-insulator and silicon-germanium substrates." Thesis, University of Surrey, 2011. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.540711.

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4

Ozguven, Nevran. "Interdiffusion studies in silicon-germanium heterostructures and selective oxidation for fabricating Ge-on-insulator /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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5

England, Troy Daniel. "Silicon-germanium BiCMOS and silicon-on-insulator CMOS analog circuits for extreme environment applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51806.

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Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.
6

Yuk, Hyung-Sang. "A novel fabrication technique of silicon germanium-on-insulator (SGOI) for SIGe heterostructure CMOS technology." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.416442.

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7

Bellini, Marco. "Operation of silicon-germanium heterojunction bipolar transistors on." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28206.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Cressler, John D.; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephen; Committee Member: Shen, Shyh-Chiang; Committee Member: Zhou, Hao Min.
8

Feng, Jia. "High-performance germanium-on-insulator MOSFETs for three-dimensional integrated circuits based on rapid melt growth /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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9

Hutin, Louis. "Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0159.

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Jusqu’au début des années 2000, les règles de scaling de Dennard ont permis de réaliser des gains en performance tout en conservant la structure de la brique de base transistor d’une génération technologique à la suivante. Cependant, cette approche conservatrice a d’ores et déjà atteint ses limites, comme en témoigne l’introduction de la contrainte mécanique pour les générations sub-130nm, et les empilements de grille métal/high-k pour les nœuds sub-65nm. Malgré l’introduction de diélectriques à forte permittivité, des limites en termes de courants de fuite de grille et de fiabilité ont ralenti la diminution de l’épaisseur équivalente d’oxyde (EOT). De façon concomitante, la diminution de la tension d’alimentation (VDD) est devenue une priorité afin de réduire la densité de puissance dissipée dans les circuits intégrés. D’où le défi actuel : comment continuer de réduire à la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dégrader le rapport de performances aux états passant et bloqué (ON et OFF) ? Diverses solutions peuvent être proposées, passant par des architectures s’éloignant du MOSFET conventionnel à canal Si avec source et drain dopés tel que défini en 1960. Une approche consiste en réaliser une augmentation du courant passant (ION) tout en laissant le courant à l’état bloqué (IOFF) et la tension de seuil (Vth) inchangés. Concrètement, deux options sont considérées en détail dans ce manuscrit à travers une revue de leurs motivations historiques respectives, les résultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) à leur mise en œuvre : i/ la réduction de la résistance parasite extrinsèque par l’introduction de source et drain métalliques (architecture transistor à barrière Schottky) ; ii/ la réduction de la résistance de canal intrinsèque par l’introduction de matériaux à haute mobilité à base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intégration Dual Channel n-sSi/p-sSiGe). En particulier, nous étudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivé par : la préservation de l’intégrité électrostatique pour les nœuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs à base de Ge (qui est un matériau à faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal à base de Germanium peut être avantageuse vis-à-vis du CMOS Silicium conventionnel
Until the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS
10

Passanante, Thibault. "Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI." Thesis, Aix-Marseille, 2014. http://www.theses.fr/2014AIXM4020.

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Ce travail de thèse est consacré à l’étude expérimentale des mécanismes de démouillage de films solides d’épaisseur nanométrique conduisant à la transformation d’un film mince en une assemblée d’îlots tridimensionnels. L’utilisation de la microscopie à électrons lents (LEEM) nous a permis d’étudier la morphologie et la cinétique in situ et en temps réel du démouillage de films de Si/SiO2 (SOI) et de Ge/SiO2 (GOI) obtenus par collage moléculaire (procédé Smart Cut™). Ces mesures expérimentales ont été complétées par des analyses par diffusion centrale des rayons X en incidence rasante (GISAXS) et des observations ex situ par microscopie à force atomique (AFM). Les mécanismes de démouillage de SOI et GOI sont thermodynamiquement pilotés par la capillarité et cinétiquement contrôlés par la diffusion de surface. L’étude complémentaire du démouillage à partir de fronts cristallographiquement orientés obtenus par lithographie nous a permis d’analyser le rôle central du facettage, de l’anisotropie cristalline et des processus de formation du bourrelet de démouillage. En particulier, le rôle de la nucléation 2D sur la cinétique d’épaississement (couche par couche) du bourrelet a pu être mis en évidence. Les résultats expérimentaux ont pu être confrontés à des modèles analytiques et des simulations de type Monte Carlo cinétique. Nous en avons déduit les valeurs des paramètres physiques pertinents et avons attribué les différences de morphologies entre SOI et GOI à la présence de facettes spécifiques
This work is devoted to the experimental study of the dewetting mechanisms of ultrathin solid films by which a metastable film transforms into an assembly of tridimensional crystallites. Using low energy Electron Microscopy (LEEM) we analyse, in situ and in real time, the morphology and the kinetics of the dewetting of Si/SiO2 (SOI) and Ge/SiO2 (GOI) systems obtained by molecular bonding (Smart Cut™ process). Further information has been obtained by Grazing Incidence Small Angle X–ray Scattering (GISAXS) and Atomic Force Microscopy (AFM) measurements. We show that the dewetting is driven by surface free energy minimization and mediated by surface diffusion. A complementary study of artificial well-oriented dewetting fronts obtained by lithography enables us to analyze the important role played by facets, the crystal anisotropy and the rim thickening mechanism. We show that the rim thickening proceeds in a layer-by-layer mode and is limited by 2D nucleation. Thanks to analytical models and Kinetics Monte Carlo simulations, numerical values of the pertinent physical parameters involved in the dewetting process are obtained and the morphological differences between SOI and GOI are attributed to the presence of specific facets
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Книги з теми "Germanium on insulator":

1

Nielsen, Hans Frede. The continental backgrounds of English and its insular development until 1154. Odense, [Denmark]: Odense University Press, 1998.

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Частини книг з теми "Germanium on insulator":

1

Gamble, H., B. M. Armstrong, P. T. Baine, Y. H. Low, P. V. Rainey, S. J. N. Mitchell, and D. W. McNeill. "Germanium Processing." In Semiconductor-On-Insulator Materials for Nanoelectronics Applications, 3–29. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-15868-1_1.

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2

Takai, M., T. Tanigawa, K. Gamo, and S. Namba. "Single Crystal Germanium Island Formation on Insulator by Zone Melting." In Silicon-on-Insulator, 159–67. Dordrecht: Springer Netherlands, 1985. http://dx.doi.org/10.1007/978-94-009-5311-6_12.

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3

Landwehr, G., and S. Uchida. "The Germanium Grain Boundary: A Disordered Two-Dimensional Electronic System." In Localization and Metal-Insulator Transitions, 379–91. Boston, MA: Springer US, 1985. http://dx.doi.org/10.1007/978-1-4613-2517-8_31.

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4

Yoshizumi, Shozo, David Mael, Theodore H. Geballet, and Richard L. Greene. "The Metal-Insulator Transition and Superconductivity in Amorphous Molybdenum-Germanium Alloys." In Localization and Metal-Insulator Transitions, 77–87. Boston, MA: Springer US, 1985. http://dx.doi.org/10.1007/978-1-4613-2517-8_7.

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5

Colinge, C. A., K. Y. Byun, I. P. Ferain, R. Yu, and M. Goorsky. "Low-Temperature Fabrication of Germanium-on-Insulator Using Remote Plasma Activation Bonding and Hydrogen Exfoliation." In Semiconductor-On-Insulator Materials for Nanoelectronics Applications, 31–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-15868-1_2.

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6

Sugiyama, N., and T. Tezuka. "Formation of silicon–germanium on insulator (SGOI) substrates." In Silicon–Germanium (SiGe) Nanostructures, 171–89. Elsevier, 2011. http://dx.doi.org/10.1533/9780857091420.2.171.

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7

TAN, CHUAN SENG. "Engineered Substrate of Germanium-on-Insulator (GOI) Through Epitaxy, Bonding and Layer Transfer." In Encyclopedia of Packaging Materials, Processes, and Mechanics, 255–82. World Scientific, 2019. http://dx.doi.org/10.1142/9789811209680_0012.

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8

Börjars, Kersti, Nigel Vincent, and Sam Wolfe. "New prepositions in the house." In Continuity and Variation in Germanic and Romance, 472–94. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780198841166.003.0019.

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In the literature on semantic and categorial change French chez and Mainland Scandinavian hos are often cited together as parallel examples of locative prepositions deriving from nouns referring to the concept ‘house’. In this paper we compare in detail the philological records and the more recent development of the two items as well as that of the cognate Insular Scandinavian hjá. We show that while there are similarities in the development of Latin CASA / French chez and hos, as frequently suggested in the literature, there are also significant divergences. We argue in favour of a reevaluation of the origin of hos aligning it with hjá rather than casa as suggested in Noreen (1892), and show that if so revised, the differences can be shown to arise from the different meanings of the source terms: Latin casa ‘hut, house’ and later ‘place’ as opposed to Old Swedish hos and Old Icelandic hjá ‘group of people, company’. We then go on to explore the consequences of these different diachronic trajectories for our general understanding of the connected semantic and syntactic developments and the time course of categorial change.
9

Gannon, Anna. "Animal Iconography." In The Iconography of Early Anglo-Saxon Coinage. Oxford University Press, 2003. http://dx.doi.org/10.1093/oso/9780199254651.003.0010.

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Pagan Germanic art had favoured the representation of animals and invested it with apotropaic qualities. The new Christian animal iconography (Evangelists’ symbols, doves, peacock, the fauna in the vine-scrolls, etc.) was accepted and integrated into a tradition which saw it not as purely decorative, but as a potent symbolic image. It is not surprising that, just as in contemporary sculpture, manuscripts, metalwork, and embroidery, many of the reverses of the Secondary series show animals, real or fantastic. These representations must be analysed in the context of the culture of the time, and therefore as potential for metaphors. Whilst the gold coinage, following Merovingian numismatic prototypes, had crosses as reverses, the Primary coins of Series B introduced birds to this iconography. Birds will indeed dominate amongst the reverses of the whole of the early Anglo-Saxon coinage, and their importance can be understood in a Christian context. Several groups of coins sharing the iconography of a bust or head with diadem and spiky hair on the obverse, and of a bird surmounting a cross on the reverse, are gathered under the classification of Series B. Some issues have unintelligible legends on both sides, cordoned by a torque of pellets, sometimes snake-headed, and though they differ in details, their iconography is consistent (Fig. 4.1). Rigold regarded the coin iconography of the bird on a cross as original Anglo-Saxon, rejecting any Merovingian numismatic precedent. Conceptually close models may have developed in imitation of Roman and Christian standards or sceptres. Coptic bronze lamps present us with several examples where the reflector above the handle is in the shape of a cross topped with a bird (Fig. 4.1c), and there is also an interesting bronze lamp in the shape of a ram with a cross and bird on its head. Following Early Christian precedents, the bird on the coins can be identified as a dove, in a Christian context a symbol of the Holy Spirit, appropriately set on a cross. In Insular metalwork there are two three-dimensional dove-shaped mounts that may perhaps have similarly topped crosses.

Тези доповідей конференцій з теми "Germanium on insulator":

1

Dehlinger, G., J. D. Schaub, S. J. Koester, Q. C. Ouyang, J. O. Chu, and A. Grill. "High-speed germanium-on-insulator photodetectors." In 2005 IEEE LEOS Annual Meeting. IEEE, 2005. http://dx.doi.org/10.1109/leos.2005.1548000.

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2

Chao, Yu-Lin, Roland Scholz, Manfred Reiche, Ulrich M. Gosele, and Jason C. S. Woo. "Fabrication and characteristics of Germanium-on-Insulator." In 2004 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2004. http://dx.doi.org/10.7567/ssdm.2004.c-4-3.

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Choi, D., B. Luther-Davies, T. Kim, K. Belay, D. Llewellyn, and R. G. Elliman. "Strain relaxation in germanium-on-insulator fabricated by a modified germanium condensation." In Devices (COMMAD). IEEE, 2010. http://dx.doi.org/10.1109/commad.2010.5699714.

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4

Jin, Hai-Yan, Eric Z. Liu, and Nathan W. Cheung. "Fabrication and characteristics of Germanium-On-Insulator substrates." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734626.

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Lin, J. Y. Jason, Arunanshu M. Roy, Yun Sun, and Krishna C. Saraswat. "Metal-Insulator-Semiconductor Contacts on Ge: Physics and Applications." In 2012 International Silicon-Germanium Technology and Device Meeting (ISTDM). IEEE, 2012. http://dx.doi.org/10.1109/istdm.2012.6222473.

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Xu, Xuejun, Keisuke Nishida, Kentarou Sawano, Takuya Maruizumi, and Yasuhiro Shiraki. "Resonant photoluminescence from Ge microdisks on Ge-on-insulator." In 2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM). IEEE, 2014. http://dx.doi.org/10.1109/istdm.2014.6874670.

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Vivien, L., M. Rouviere, D. Marris-Morini, J. Mangeney, P. Crozat, E. Cassan, X. le Roux, et al. "Germanium photodetector integrated in a Silicon-On-Insulator microwaveguide." In 2007 4th IEEE International Conference on Group IV Photonics. IEEE, 2007. http://dx.doi.org/10.1109/group4.2007.4347743.

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Li, Wei, P. Anantha, Kwang Hong Lee, Jin Zhou, Xin Guo, Hong Wang, and Chuan Seng Tan. "Germanium-on-insulator Pedestal Waveguide for Midinfrared Sensing Applications." In Bragg Gratings, Photosensitivity and Poling in Glass Waveguides and Materials. Washington, D.C.: OSA, 2018. http://dx.doi.org/10.1364/bgppm.2018.jtu2a.58.

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Loiacono, Renzo, Graham T. Reed, Russell Gwilliam, Goran Z. Mashanovich, Liam O'Faolain, Thomas Krauss, Giorgio Lulli, Chris Jeynes, and Richard Jones. "Germanium implanted Bragg gratings in silicon on insulator waveguides." In OPTO, edited by Joel A. Kubby and Graham T. Reed. SPIE, 2010. http://dx.doi.org/10.1117/12.839502.

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Tani, K., S. Saito, Y. Lee, K. Oda, T. Mine, T. Sugawara, and T. Ido. "Light Detection and Emission in Germanium-On-Insulator Diodes." In 2011 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2011. http://dx.doi.org/10.7567/ssdm.2011.i-8-4.

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