Дисертації з теми "High mobility channels"
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1
Palmer, Martin John. "Investigation of high mobility pseudomorphic SiGe p channels in Si MOSFETS at low and high electric fields." Thesis, University of Warwick, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246761.
2
Hutin, Louis. "Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0159.
Анотація:
Jusqu’au début des années 2000, les règles de scaling de Dennard ont permis de réaliser des gains en performance tout en conservant la structure de la brique de base transistor d’une génération technologique à la suivante. Cependant, cette approche conservatrice a d’ores et déjà atteint ses limites, comme en témoigne l’introduction de la contrainte mécanique pour les générations sub-130nm, et les empilements de grille métal/high-k pour les nœuds sub-65nm. Malgré l’introduction de diélectriques à forte permittivité, des limites en termes de courants de fuite de grille et de fiabilité ont ralenti la diminution de l’épaisseur équivalente d’oxyde (EOT). De façon concomitante, la diminution de la tension d’alimentation (VDD) est devenue une priorité afin de réduire la densité de puissance dissipée dans les circuits intégrés. D’où le défi actuel : comment continuer de réduire à la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dégrader le rapport de performances aux états passant et bloqué (ON et OFF) ? Diverses solutions peuvent être proposées, passant par des architectures s’éloignant du MOSFET conventionnel à canal Si avec source et drain dopés tel que défini en 1960. Une approche consiste en réaliser une augmentation du courant passant (ION) tout en laissant le courant à l’état bloqué (IOFF) et la tension de seuil (Vth) inchangés. Concrètement, deux options sont considérées en détail dans ce manuscrit à travers une revue de leurs motivations historiques respectives, les résultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) à leur mise en œuvre : i/ la réduction de la résistance parasite extrinsèque par l’introduction de source et drain métalliques (architecture transistor à barrière Schottky) ; ii/ la réduction de la résistance de canal intrinsèque par l’introduction de matériaux à haute mobilité à base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intégration Dual Channel n-sSi/p-sSiGe). En particulier, nous étudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivé par : la préservation de l’intégrité électrostatique pour les nœuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs à base de Ge (qui est un matériau à faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal à base de Germanium peut être avantageuse vis-à-vis du CMOS Silicium conventionnelUntil the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS
3
Sun, Xiao. "Characterization and Fabrication of High k dielectric-High Mobility Channel Transistors." Thesis, Yale University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3578458.
Анотація:
As the conventional scaling of Si-based MOSFETs would bring negligible or even negative merits for IC's beyond the 7-nm CMOS technology node, many perceive the use of high-mobility channels to be one of the most likely principle changes, in order to achieve higher performance and lower power. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, InGaAs, GaSb, GaN...) to replace Si CMOS technology.
In this thesis, the distinct properties of the traps in the high-k dielectric/high-mobility substrate system is discussed, as well as the challenges to characterize and passivate them. By modifying certain conventional gate admittance methods, both the fast and slow traps in Ge MOS gate stacks is investigated. In addition, a novel ac-transconductance method originated at Yale is introduced and demonstrated with several advanced transistors provided by collaborating groups, such as ultra-thin-body & box SO1 MOSFETs (CEA-LETI), InGaAs MOSFETs (IMEC, UT Austin, Purdue), and GaN MOS-HEMT (MIT).
By use of the aforementioned characterization techniques, several effective passivation techniques on high mobility substrates (Ge, InGaAs, GaSb, GeSn, etc.) are evaluated, including a novel Ba sub-monolayer passivation of Ge surface. The key factors that need to be considered in passivating high mobility substrates are revealed.
The techniques that we have established for characterizing traps in advanced field-effect transistors, as well as the knowledge gained about these traps by the use of these techniques, have been applied to the study of ionizing radiation effects in high-mobility-channel transistors, because it is very important to understand such effects as these devices are likely to be exposed to radiation-harsh environments, such as in outer space, nuclear plants, and during X-ray or UHV lithography. In this thesis, the total ionizing dose (TD) radiation effects of InGaAs-based MOSFETs and GaN-based MOS-HEMT are studied, and the results help to reveal the underlying mechanisms and inspire ideas for minimizing the TID radiation effects.
4
Chu, Rongming. "AlGaN-GaN single- and double-channel high electron mobility transistors /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20CHU.
Анотація:
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.Includes bibliographical references (leaves 74-82). Also available in electronic version. Access restricted to campus users.
5
Pearson, John Lawson. "Scattering and mobility in indium gallium arsenide channel, pseudomorphic high electron mobility transistors (InGaAs pHEMTs)." Thesis, University of Glasgow, 1999. http://theses.gla.ac.uk/6613/.
Анотація:
Extensive transport measurements have been completed on deep and shallow-channelled InGaAs p-HEMTS of varying growth temperature, indium content, spacer thickness and doping density, with a view to thorough characterisation, both in the metallic and the localised regimes. Particular emphasis was given to MBE grown layers, with characteristics applicable for device use, but low measurement temperatures were necessary to resolve the elastic scattering mechanisms. Measurements made in the metallic regime included transport and quantum mobility - the former over a range of temperatures between 1.5K to 300K. Conductivity measurements were also acquired in the strong localisation regime between about 1.5K and 100K.Experimentally determined parameters were tested for comparison with those predicted by an electrostatic model. Excellent agreement was obtained for carrier density. Other parameters were less well predicted, but the relevant experimental measurements, including linear depletion of the 2DEG, were sensitive to any excess doping above a 'critical' value determined by the model. At low temperature (1.5K), it was found that in all samples tested, transport mobility was strongly limited at all carrier densities by a large q mechanism, possibly intrinsic to the channel. This was ascribed either to scattering by the long-range potentials arising from the indium concentration fluctuations or fluctuations in the thickness of the channel layer. This mechanism dominates the transport at lower carrier densities for all samples, but at high carrier density, an additional mechanism is significant for samples with the thinnest spacers tested (2.5nm). This is ascribed to direct electron interaction with the states of the donor layer, and produces a characteristic transport mobility peak.
6
Krishnamohan, Tejas. "Physics and technology of high mobility, strained germanium channel, heterostructure MOSFETs." access full-text online access from Digital Dissertation Consortium, 2006. http://libweb.cityu.edu.hk/cgi-bin/er/db/ddcdiss.pl?3219310.
7
Sand, Stephan. "Joint iterative channel and data estimation in high mobility MIMO-OFDM systems." Berlin Logos-Verl, 2009. http://d-nb.info/100018501X/04.
8
Cabello, Fusarés Maria. "MOS interface improvement based on boron treatments for high channel mobility SiC MOSFETs." Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/668243.
Анотація:
Although silicon (Si) is used in most current commercial power semiconductor components, Si capabilities are insufficient for new energy conversion requirements. Some of its important limitations are related with power losses, operation temperature, radiation hardness and switching speed. Then, new semiconductor materials must be developed to face the future global energetic challenges, overcoming Si intrinsic limitations.
Silicon Carbide (SiC) is a proper wide bandgap (WBG) semiconductor with high critical electric field strength and a high saturation carrier’s drift velocity, which makes it able to sustain higher voltages with lower conduction losses. Furthermore, in a similar way to Si, SiC native oxide (SiO2) can be formed. However, a drawback of SiC MOSFETs is their poor oxide reliability and low channel mobility values attributed to a poor SiO2/SiC interface quality, with high density of interface traps (Dit) and near interface oxide traps (NIOTs). Nitridation processes, consisting in a nitric or nitrous oxide (NO, N2O) annealing is considered as the standard post oxidation annealing approach in 4H-SiC MOSFETs, being commonly used in commercial SiC power MOSFETs for reducing the Dit and NIOTs. However the nitridation interface passivation is not enough and, furthermore the limit of the improvement provided by nitridation has been reached.
This thesis is focused on 4H-SiC-based power devices, particularly, on one of the major issues in SiC technology: to find a suitable and reliable fabrication process that improves the gate oxide and SiO2/SiC interface quality and reliability. Regarding electrical performances, we will focus on two of the major challenges of this field: the improvement of the inversion channel mobility, and the gate oxide stability, in order to further reduce the on-resistance and enhance the gate oxide reliability. Both problems are related to the defects near the SiO2/SiC interface.
To meet these challenges and improve the current gate oxide quality state-of-the-art, several strategies were followed. We have worked on a newly interface passivation by oxynitridation methods combined with a boron diffusion treatment through the gate oxide. This novel approach allowed us to reach significantly high channel mobility values, up to 200 cm2/Vs. We also extensively studied the impact of the boron treatment parameters on the stability performances of our test structures, revealing some stability issues, especially at high temperature operation. In parallel, we have also worked on the improvement of the dielectric reliability by using a thin layer of a high-k material.
On the other hand, equally important, we studied the different fabrication issues found during the gate dielectric optimisation process. Taking into account the specific performances of our devices, we adapted the electrical and physical characterization processes required for a complete study of this kind of high mobility devices (for both, oxide and interface quality characterization, and final electrical MOSFET performance).
Finally, some studies which provide information about boron treatment impact on the oxide and interface traps, and about the global electrical behaviour of our devices are included in this thesis; concretely:
i) A study on MOSFET mobility anisotropy, having into account different scattering mechanisms involved in channel carrier’s mobility.
ii) The effect of MOSFET channel dimensions in the obtained channel mobility.
iii) A comparison of B passivation effect on MOSFETs fabricated over 4H-SiC and 6H-SiC polytypes.
As a result, despite our new boron doping process is still not mature to be used in commercial devices, it allowed us to progress in the understanding of some of the phenomena taking place at the SiO2/SiC interface, in the way to properly characterise and interpret them, and in the way to further improve the MOS structure on SiC.El silici (Si) és el semiconductor utilitzat en la majoria de components comercials de potència, no obstant, les seves propietats intrínseques són insuficients per als nous requeriments de conversió energètica, fent que sigui necessari el desenvolupament de nous materials semiconductors. Les seves limitacions estan relacionades amb les pèrdues tèrmiques, la temperatura de funcionament, la resistència a la radiació o la velocitat de commutació. Un material semiconductor adequat és el Carbur de Silici (SiC) el qual té un alt valor de camp elèctric crític i un alt valor de saturació de la velocitat de portadors, cosa que el fa capaç de mantenir altes tensions amb menors pèrdues per conducció. A més a més, com passa amb el Si, es pot formar diòxid de silici (SiO2) natiu sobre el SiC. Un inconvenient dels MOSFETs de SiC és la baixa fiabilitat del òxids i els baixos valors de mobilitat de canal, atribuïts a una mala qualitat de la interfície SiO2/SiC, que conté una alta densitat de trampes a la interfície (Dit) i al òxid proper a la interfície (NIOTs). Els MOSFETs comercials de 4H-SiC són sotmesos a un procés tèrmic standard post-oxidació. Aquest consisteix en un recuit en òxid nítric o òxid nitrós (NO, N2O), amb propòsit de reduir la Dit i els NIOTs. Tot i així, la passivació de la interfície assolida mitjançant la nitridació no és suficient i s'ha arribat al límit de millora que pot proporcionar aquest procediment. Aquesta tesi està dirigida a resoldre un dels principals problemes de la tecnologia en 4H-SiC: trobar un procés de fabricació adequat i fiable que millori la qualitat i la fiabilitat tant de l’òxid de porta com de la interfície SiO2/SiC, per a la seva aplicació en dispositius de potència. Pel que fa a les prestacions elèctriques, ens centrem en dos dels principals reptes d’aquest àmbit: la millora de la mobilitat del canal d’inversió i l’estabilitat de l’òxid de porta, per tal de reduir la resistència del canal drenador-font i millorar la fiabilitat de l’òxid de porta. Per assolir aquests reptes i millorar la tecnologia actual lligada a l’optimització de l'òxid de porta, seguim diverses estratègies: Per una banda, utilitzar una nova passivació d’interfície mitjançant mètodes d’oxinitridació combinats amb un tractament de difusió de bor (B) a través de l’òxid de la porta. Estudiant també quin és el seu impacte sobre l’estabilitat de les estructures tant a temperatura ambient com a altes temperatures. Aquest nou procés ha permès assolir valors de mobilitat del canal significativament elevats, fins a 200 cm2/Vs. Per altra banda hem treballat en la millora de la fiabilitat del dielèctric mitjançant una capa prima d’un material d’alta k. Paral·lelament, s’han estudiat diferents problemes de fabricació trobats durant el procés d’optimització del dielèctric. Tenint en compte les prestacions específiques dels nostres dispositius, vam adaptar els processos de caracterització elèctrica i física necessaris per a un estudi complet, tant de la qualitat de l’òxid i la interfície, com per al rendiment elèctric del MOSFET final. Finalment, en aquest treball s’inclouen alguns estudis que proporcionen informació sobre l’impacte que té la difusió de B sobre la Dit, els NIOTs i, en general el comportament elèctric dels nostres dispositius. Concretament: i) L’anisotropia de la mobilitat dels MOSFETs, tenint en compte els diferents mecanismes de dispersió implicats en la mobilitat dels portadors. ii) L’efecte de les dimensions del canal sobre la mobilitat obtinguda. iii) Comparació de l’efecte de passivació que té el B sobre MOSFETs fabricats en els politipus 4H-SiC i 6H-SiC. Malgrat el procés de dopatge de bor presentat encara no està suficientment madur per ser utilitzat en dispositius comercials, ens ha permès progressar en la comprensió d'alguns dels fenòmens que tenen lloc a la interfície SiO2
9
Leitz, Christopher W. (Christopher William) 1976. "High mobility strained Si/SiGe heterostructure MOSFETs : channel engineering and virtual substrate optimization." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8440.
Анотація:
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2002.Includes bibliographical references (leaves 163-174).
High quality relaxed silicon-germanium graded buffers are an important platform for monolithic integration of high speed heterostructure field-effect transistors and III-V-based optoelectronics onto silicon substrates. In this thesis, dislocation dynamics in compositionally graded SiGe layers are explored and mobility enhancements in strained Si/SiGe metal-oxide-semiconductor field-effect transistors (MOSFETs) are evaluated. These results demonstrate the dramatic increases in microelectronics performance and functionality that can be obtained through use of the relaxed SiGe integration platform. By extending and modifying a model for dislocation glide kinetics in graded buffers to SiGe/Si, a complete picture of strain relaxation in SiGe graded buffers emerges. To investigate dislocation glide kinetics in these structures, a series of identical samples graded to 30% Ge have been grown at temperatures between 650ʻC and 900ʻC on (001)-, (001) offcut 6ʻ towards an in-plane <110>-, and (001) offcut 6ʻ towards an in-plane <100>-oriented Si substrates. The evolution of field threading dislocation density (TDD) with growth temperature in the on-axis samples indicates that dislocation nucleation and glide kinetics together control dislocation density in graded buffers. The TDD of samples grown on offcut substrates exhibits a more complicated temperature dependence, due to their reduced tendency towards dislocation pile-up formation at low temperature and dislocation reduction reactions at high temperature. Finally, by evaluating field threading dislocation density and dislocation pile-up density in a wide variety of SiGe graded buffers, a correlation between dislocation pile-up formation and increases in field threading dislocation density emerges.
(cont.) Record mobility strained Si p-MOSFETs have been fabricated on relaxed 40% Ge virtual substrates. Hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with mobility enhancements over twice that of co-processed bulk Si devices. In contrast, hole mobility in strained Si p-MOSFETs displays no strong dependence on strained layer thickness. These results indicate that strain is the primary variable in determining hole mobility in strained Si p-MOSFETs and that symmetric electron and hole mobility enhancements in strained Si MOSFETs can be obtained for virtual substrate compositions beyond 35% Ge. The effect of alloy scattering on carrier mobility in tensile strained SiGe surface channel MOSFETs is measured directly for the first time. Electron mobility is degraded much more severely than hole mobility in these heterostructures, in agreement with theoretical predictions. Dual channel heterostructures, which consist of the combination of buried compressively strained SiilyGey buried channels and tensile strained Si surface channels, grown on relaxed SilxGex virtual substrates, are explored in detail for the first time. Hole mobilities exceeding 700 cm2/V-s have been achieved by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. This layer sequence exhibits nearly symmetric electron and hole mobilities, both enhanced relative to bulk Si ...
by Christopher W. Leitz.
Ph.D.
10
Liu, Dongmin. "Design, Fabrication and Characterization of InAlAs/InGaAs/InAsP Composite Channel HEMTs." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1213299848.
11
Hennessy, John 1980. "High mobility germanium MOSFETs : study of ozone surface passivation and n-type Dopant channel implants combined with ALD dielectrics." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58174.
Анотація:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 107-111).
Germanium offers higher electron and hole mobility than silicon, making it an attractive option for future high-performance MOSFET applications. To date, Ge p-channel device behavior has shown promise, with many reports of measured hole mobilities exceeding that of Si. However, Ge n-channel devices have shown poor performance due to an asymmetric distribution of interface state density (Dit) that degrades electrostatic behavior and carrier mobility. In this work, two methods are investigated for improving the performance of Ge MOSFETs. First, the formation of an interfacial passivation layer via in-situ ozone oxidation is explored. Long channel Ge p- and n-MOSFETs are fabricated with A12 0 3 and HfO2 gate dielectrics deposited by atomic layer deposition (ALD). The ozone surface passivation is observed to result in significant mobility enhancement for all devices, with particularly dramatic improvement in the n-FETs compared to devices with no passivation layer. Measurements of interface state density show a reduction across the entire Ge bandgap. Further improvement of the interface quality has been observed to occur in the presence of n-type channel implants in Ge n-FETs and this effect is studied. All n-type species investigated in this work (P, As, Sb) are seen to result in significant electron mobility enhancement, particularly at low inversion densities. Ge n-FETs receiving channel implants of As or Sb along with the ozone surface passivation exhibit effective electron mobilities higher than Si electron mobility under some conditions of surface electric field for the first time. Substrate bias measurements and low temperature characterization both suggest a reduction in Dit, primarily of acceptor-like trap states near the conduction band.
by John J. Hennessy.
Ph.D.
12
Bouallegue, Kaïs. "Contribution à la radio intelligente à forte mobilité : adaptation spectrale et allocation dynamique des ressources." Thesis, Valenciennes, 2017. http://www.theses.fr/2017VALE0023.
Анотація:
Les objectifs essentiels des opérateurs ferroviaires sont d'augmenter la sécurité, de réduire les coûts d'exploitation et de maintenance, d'accroître l'attrait et le profit en offrant de nouveaux services aux passagers. Ces objectifs seront atteintsgrâce à une énorme augmentation des échanges de flux de données entre les infrastructures existantes et les technologies présentes utilisées au bord du train. L'efficacité spectrale, l'optimisation des ressources radioélectriques ainsi que l'interopérabilité mais aussi la fiabilité des communications sont des éléments majeurs pour les applications ferroviaires. Ces contraintes ainsi que l'utilisation sporadique des bandes fréquentielles à disposition ont donné le jour à la radio intelligente. Cette dernière se présente comme une technologie émergente qui améliore les performances des systèmes radio existants en intégrant l'intelligence artificielle avec la radio logicielle. Un système radio intelligent est défini par sa capacité à être conscient de son environnement radioélectrique. En effet, afin d'optimiser au maximum les opportunités spectrales qui lui sont offerts, le dispositif radio intelligent doit être capable de transmettresur des bandes laissées libres tout en réalisant un sondage spectral afin de ne pas interférer avec les utilisateurs ayant la priorité sur la bande mais aussi pour détecter d'autres fréquences vacantes. Dans le cadre de cette thèse, nous proposons de nous concentrer sur la problématique de détection de spectre dans un environnement à très forte mobilité. Certaines contraintes sont à prendre en compte, telles que la vitesse. À cela s'ajoute les contraintes de réglementation concernant les critères de détection, telles que la norme IEEE 802.22 WRAN qui stipule que la détection d'un utilisateur prioritaire doit être réalisée à -21dB dans un laps de temps de 2 secondes. L'objectif est donc de concevoir un terminal radio intelligent dans les conditions physiques et réglementaires de transmission dans un environnent ferroviaireThe main objectives of railway operators are to increase safety, reduce operating and maintenance costs, increase attractiveness and profit by offering new services to customers. These objectives will be achieved through a huge increase of data fluxes between existing infrastructure and the technologies currently used on the train. Spectral efficiency, optimization of radio resources, interoperability and reliability of communications are major elements for railway applications. These constraints and the sporadic use of available frequency bands have gave rise to cognitive radio. Cognitive radio is an emerging technology that improves the performance of existing radio systems by integrating artificial intelligence with software radio. A cognitive radio system is defined by its ability to be aware of its radio environment. Indeed, to optimize as much as possible the available spectral opportunities, the cognitive radio device must be able to transmit on free bands while performing a spectrum sensing to not interfere with users having priority on the band and to detect other vacant frequencies. As part of this thesis, we propose to focus on the problem of spectrum detection in a highly mobile environment. Some constraints should be considered, such as speed. Added to this, there are regulatory constraints on detection criteria, such as the IEEE 802.22 WRAN standard, which stipulates that detection of a priority user must be performed at -21 dB within a period of 2 seconds. The objective is therefore to design an intelligent radio terminal in the physical and regulatory conditions of transmission in a railway environment
13
Kim, Tong-Ho. "Solid source molecular beam epitaxy of InP-based composite-channel high electron mobility transistor structures of microwave and millimeter-wave power applications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14859.
14
von, Haartman Martin. "Low-frequency noise characterization, evaluation and modeling of advanced Si- and SiGe-based CMOS transistors." Doctoral thesis, KTH, Mikroelektronik och Informationsteknik, IMIT, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3888.
Анотація:
A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static electrical measurements and low-frequency noise characterizations in this thesis. These novel field-effect transistors (FETs) include (i) compressively strained SiGe channel pMOSFETs, (ii) tensile strained Si nMOSFETs, (iii) MOSFETs with high-k gate dielectrics, (iv) metal gate and (v) silicon-on-insulator (SOI) devices. The low-frequency noise was comprehensively characterized for different types of operating conditions where the gate and bulk terminal voltages were varied. Detailed studies were made of the relationship between the 1/f noise and the device architecture, strain, device geometry, location of the conduction path, surface cleaning, gate oxide charges and traps, water vapour annealing, carrier mobility and other technological factors. The locations of the dominant noise sources as well as their physical mechanisms were investigated. Model parameters and physical properties were extracted and compared. Several important new insights and refinements of the existing 1/f noise theories and models were also suggested and analyzed. The continuing trend of miniaturizing device sizes and building devices with more advanced architectures and complex materials can lead to escalating 1/f noise levels, which degrades the signal-to-noise (SNR) ratio in electronic circuits. For example, the 1/f noise of some critical transistors in a radio receiver may ultimately limit the information capacity of the communication system. Therefore, analyzing electronic devices in order to control and find ways to diminish the 1/f noise is a very important and challenging research subject. We present compelling evidence that the 1/f noise is affected by the distance of the conduction channel from the gate oxide/semiconductor substrate interface, or alternatively the vertical electric field pushing the carriers towards the gate oxide. The location of the conduction channel can be varied by the voltage on the bulk and gate terminals as well by device engineering. Devices with a buried channel architecture such as buried SiGe channel pMOSFETs and accumulation mode MOSFETs on SOI show significantly reduced 1/f noise. The same observation is made when the substrate/source junction is forward biased which decreases the vertical electric field in the channel and increases the inversion layer separation from the gate oxide interface. A 1/f noise model based on mobility fluctuations originating from the scattering of electrons with phonons or surface roughness was proposed. Materials with a high dielectric constant (high-k) is necessary to replace the conventional SiO2 as gate dielectrics in the future in order to maintain a low leakage current at the same time as the capacitance of the gate dielectrics is scaled up. In this work, we have made some of the very first examinations of 1/f noise in MOSFETs with high-k structures composed by layers of HfO2, HfAlOx and Al2O3. The 1/f noise level was found to be elevated (up to 3 orders of magnitude) in the MOSFETs with high-k gate dielectrics compared to the reference devices with SiO2. The reason behind the higher 1/f noise is a high density of traps in the high-k stacks and increased mobility fluctuation noise, the latter possibly due to noise generation in the electron-phonon scattering that originates from remote phonon modes in the high-k. The combination of a TiN metal gate, HfAlOx and a compressively strained surface SiGe channel was found to be superior in terms of both high mobility and low 1/f noise.QC 20100928
15
Persson, Stefan. "Modeling and characterization of novel MOS devices." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3720.
Анотація:
Challenges with integrating high-κ gate dielectric,retrograde Si1-xGexchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si1-xGex surface-channel and different high-κgate dielectric are examined. Si1-xGex ρMOSFETs with an Al2O3/HfAlOx/Al2O3nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si1-xGexρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si1-xGexρMOSFETs.
Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si1-xGexincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si1-xGex/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi2-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi1-xGex is found to form on selectively grown p-typeSi1-xGexused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi1-xGex/p-type Si1-xGexcontacts is 5´10-8Ωcm2, which satisfies the requirement for the 45-nmtechnology node in 2010.
When the Si1-xGexchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi1-xGexretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled.
Key Words:MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.
16
Lin, San-Fu, and 林三富. "Investigation of InAlAs/InxGa1-xAs Metamorphic High Electron Mobility Transistors (MHEMT’s) With Pseudomorphic and Symmetrically-graded Channels." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/88877658973428286549.
Анотація:
碩士國立成功大學
微電子工程研究所碩博士班
93
In this thesis, the characteristics of the In0.425Al0.575As/InxGa1-xAs metamorphic high electron mobility transistors (MHEMT’s) with two different channel designs, grown by a molecular beam epitaxy (MBE) system have been studied. The studied devices exhibit high-frequency circuit applications, including the drain-source saturation current density (IDSS = 511 mA/mm), maximum extrinsic transconductance (gm,max =315 mS/mm), microwave performance (fT = 55.4 GHz, and fmax = 77.5 GHz), and low-noise characteristics (NFmin=0.88 dB at 2.4 GHz) have been achieved for the pseudomorphic channel MHEMT (PC-MHEMT). Therefore, PC-MHEMT is suitable for high-frequency and low-noise applications. On the other hand, due to higher conduction-band discontinuities (ΔEc) and good carrier confinement, the high-temperature device characteristics with good thermal stability is achieved for the deviations of IDSS and gm,max are 21.9﹪and 17.7﹪with increasing the temperature from 300 K to 500 K, respectively. In addition, the V-shaped symmetrically-graded channel MHEMT (SGC-MHEMT) due to the effective energy-gap is larger than that of PC-MHEMT, improved breakdown characteristics (BVGD = -16.05 V, BVoff = 14.64 V, and BVon=10.9 V) and the deviations of BVGD is 26﹪ with increasing the temperature from 300 K to 500 K. Therefore, SGC-MHEMT is suitable for high-power and high-linearity circuit applications, including improved gate-voltage swing (GVS = 1.3 V), small-signal power gain (Gs =19.2 dB), and output power (Pout =14.9 dBm).
17
Chien-HungChen and 陳建宏. "The Investigations and 3D Simulations of the Characteristics of Advanced HKMG Bulk FinFETs and SiGe Channels with High Mobility." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/afyf39.
Анотація:
博士國立成功大學
電機工程學系
103
For these years, according to ITRS roadmap, the size of device keeps scaling. It comes to nanodevice’s generation, each step of process technology has become more complicated, and this is based on more breakthrough of technology. If we want to keep scaling based on Moore’s Law technology, in addition to the breakthroughs and innovations for traditional process technology, the innovation of transistor structure for sub-nano-or even nanoscale transistors is the key-point. Bulk FinFET is one of the candidates for device in sub-22 nm technology node, because of its good cut-off characteristics, short channel effect control and better scalability by double gate mode operation. Recent researches on FinFET devices were reported, but there are few reports discuss the influence of layout parameter, such as fin width, fin height, and the fin numbers, on the electrostatic characteristic of the devices. In the first part of this thesis, we experimentally fabricate and characterize high-k metal gate (HKMG) bulk FinFET devices, and simulate the fin profile with different tapers and rounding. The effect of the fin taper and rounding profile on the C-V characterization is assessed by extracting the fabrication parameters accordingly. The capacitance-voltage electrical characteristics of fin field-effect transistor (FinFET) varactors which have fins with different taper angles and rounding radiuses are investigated. By fitting the results of the three-dimensional correction simulation with those of an experimentally fabricated FinFET varactor, two key factors of process simulations (taper angles θ and rounding radius r) are extracted. It is found that the the capacitance of the FinFET varactor changes when the fin cross-sectional profile varies. The examination presented here is useful in the fabrication of FinFETs. It clarifies the fin cross-sectional profile effect on the FinFET varactor capacitance. The effects of the depletion capacitance of a varactor between fin field-effect Transistor (FinFET) and bulk planar devices are investigated. The depletion capacitance of an NMOS varactor in FinFETs is lower than that of the conventional bulk planar one. Thus, the NMOS FinFET varactor provides a larger tuning range than the bulk planar one. The simulation results of the proposed 3D devices with FinFET and bulk planar varactors show that the depletion layer width of the NMOS varactors in FinFETs is more sensitive to the applied gate voltage than the bulk planar one. We for the first time explore the dependence of the silicon fin width on the electrostatic characteristic of HKMG bulk FinFET devices. On the same layout area, our study indicates that the narrow fin width possesses worse flat band voltage shift and large variation of gate capacitance owing to increased substrate resistance. In the second part of this thesis, the interface roughness between the Si(1-x)Gex (x=0.25) and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy. The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices. We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility. The Ge concentration play an important role in SiGe channel Fin-FET device. A fast, more convenient, and nondestructive analysis method, three-dimensional spectroscopic ellipsometry-optical critical dimension metrology (3D SE-OCD), is used to extract Ge concentrations of SiGe channel FinFETs. The refractive index (n) and extinction index (k) of SiGe with different Ge concentrations investigated under wavelengths ln = 370 nm and lk = 525 nm. Results show that the Ge concentration of SiGe channel can be accurately measured using a 3D SE-OCD.
18
Pei-Ling, Wang. "High Mobility Strained-Ge Channel Field Effect Transistor." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0607200511512400.
19
Wang, Pei-Ling, and 王珮齡. "High Mobility Strained-Ge Channel Field Effect Transistor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/87913171355459893365.
Анотація:
碩士國立臺灣大學
電子工程學研究所
93
A novel structure with a 4-nm-thick Ge layer epitaxially grown on Si substrate (100) was simulated and characterized for applications to high-speed transistors. Raman spectra confirmed the compressive strain (~1.25%) in the Ge channel. The ultra thin Ge (~ 4 nm) channel on Si substrate has advantages of low defect density and hole mobility enhancement due to the compressive strain. No conspicuous defect observed in transmission electron microscope (TEM) and the strong electroluminescence (EL) from epi-Ge (ε-Ge) indicates the low defect density. For numerical simulations of strained-Ge channel devices, strain effects on the band alignments and bandgaps of the Si-cap/ε-Ge heterostructure have been analyzed. The corresponding parameters calculated by theories are applied in the simulations. Optimization of structure design regarding Ge layer thickness TGe and Si-cap layer thickness TSiCap have been carried out in order to achieve better performance. Thinner TGe can’t confine hole wavefunction effectively while thicker TGe leads to more dislocations. On the other hand, thinner TSiCap are preferred since it can increase gate-to-channel capacitance, but may worsen Ge diffusion as well as non-uniform oxide/semiconductor interface. Simulations and theoretical results reveal that 1-nm-thick TSiCap and 4-nm-thick TGe are appropriate and thus are targeted in this work. The drive current improvements of the conventional implanted source/drain strained-Ge channel p-MOSFETs compared with that of bulk Si are found to be ~2x at saturation region. The holes confinement shoulder is observed on the capacitance-voltage characteristics at inversion region, indicating that a thin layer of Si-cap remains after the device process. Conventional implanted source/drain strained-Ge channel n-MOSFETs are also investigated. The Si-cap is thin (~1nm) enough to enable the electron wave function to penetrate into high mobility buried Ge layer. It exhibits ~40% current enhancement as compared to the bulk Si device. Schootky barrier MOSFETs(SBMOSFETs) is a promising application in the future. The Pt Schottky barrier strained-Ge channel p-MOSFETs with the conventional SiO2 as gate dielectrics reveal a ~3.2x mobility enhancement. The successful combination of strained-Ge channel and SBMOSFETs shows great potential in the CMOS technology.
20
林騰毅. "Channel Estimation in High Mobility OFDM Transmission Systems." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/61522954670718525794.
21
Lu, Tsung-Hsing, and 呂宗興. "Simulation and Analysis for Dual-channel and Composite-channel High Electron Mobility Transistors." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/03007710653566445261.
Анотація:
碩士雲林科技大學
光學電子工程研究所
96
High electron mobility transistor (HEMT) device is one of the most important semiconductor devices for military and commercial communication applications at millimeter-wave frequencies. In this thesis, dual-channel HEMT and composite HEMT structures are studied using the two-dimension device simulation program MEDICI. Electrical characteristics with different thickness of the barrier layers and spacer layers, and also with different concentration of the delta-doping layer, are simulated and compared. From the simulation result, the optimized layer structures for higher drain current and transconductance are obtained.
22
Nassar, Joanna M. "Transformational Electronics: Towards Flexible Low-Cost High Mobility Channel Materials." Thesis, 2014. http://hdl.handle.net/10754/316698.
Анотація:
For the last four decades, Si CMOS technology has been advancing with Moore’s law prediction, working itself down to the sub-20 nm regime. However, fundamental problems and limitations arise with the down-scaling of transistors and thus new innovations needed to be discovered in order to further improve device performance without compromising power consumption and size. Thus, a lot of studies have focused on the development of new CMOS compatible architectures as well as the discovery of new high mobility channel materials that will allow further miniaturization of CMOS transistors and improvement of device performance.
Pushing the limits even further, flexible and foldable electronics seem to be the new attractive topic. By being able to make our devices flexible through a CMOS compatible process, one will be able to integrate hundreds of billions of more transistors in a small volumetric space, allowing to increase the performance and speed of our electronics all together with making things thinner, lighter, smaller and even interactive with the human skin. Thus, in this thesis, we introduce for the first time a cost-effective CMOS compatible approach to make high-k/metal gate devices on flexible Germanium (Ge) and Silicon-Germanium (SiGe) platforms.
In the first part, we will look at the various approaches in the literature that has been developed to get flexible platforms, as well as we will give a brief overview about epitaxial growth of Si1-xGex films. We will also examine the electrical properties of the Si1-xGex alloys up to Ge (x=1) and discuss how strain affects the band structure diagram, and thus the mobility of the material. We will also review the material growth properties as well as the state-of-the-art results on high mobility metal-oxide semiconductor capacitors (MOSCAPs) using strained SiGe films.
Then, we will introduce the flexible process that we have developed, based on a cost-effective “trench-protect-release-reuse” approach, utilizing the industry’s most used bulk Si (100) wafers, and discuss how it has been used for getting flexible and semi-transparent SiGe and Ge platforms.
Finally, we examine the electrical characteristics of our materials through the fabrication of high-k/metal gate MOSCAPs with SiGe and Ge as channel material. We present their electrical performance on both non- flexible and flexible platform and discuss further improvement that has to be made in order to get better behaving devices for future MOSFET fabrication.
23
LEE, CHIN-CHUN, and 李靖群. "Channel Identification of OFDM System in Very High Mobility Environment." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/33496862415888669817.
Анотація:
碩士國立暨南國際大學
通訊工程研究所
96
This thesis probes for the very high mobility environment mainly. In medium or low mobility environment，we usually assume that the channel is time-invariant during each OFDM symbol which we transmit and demodulate. Because the very high mobility environment for TAIWAN HIGH SPEED RAIL (300km/hr) leads to critical doppler effect，the system suffers from the fast fading effect severely. In OFDM used large FFT points transmission architecture，the channel will change during each OFDM symbol.The bit error rate of conventional transmission and demodulation for time-variant channel will increase substantially ,so the major issues that how to transmit pilots and demodulate in receiver to decrease the bit error rate. This thesis uses ML channel estimation to estimate channel value and do interpolation in time domain to modify the channel situation. Finally ，we Use linear minimum mean square error equalizer to resist ICI effect. Besides , the channel is impossible to be known in real environment,so using power detection to distinguish the longest channel impulse length and noise location is the other major issue.
24
Fu-Min, Wang, and 王富民. "Investigation of AlGaN/GaN Doping-Channel High Electron Mobility Transistors." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/75941597127919252758.
Анотація:
碩士國立高雄師範大學
電子工程學系
103
Investigation of AlGaN/GaN Doping-Channel High Electron Mobility Transistors Fu-Min Wang* Jung-Hui Tsai** Department of Electronics, National Kaohsiung Normal University, Kaohsiung, Taiwan, R.O.C Abstract In this dissertation, we will fabricate and investigate the impact of doping channel on the AlGaN/GaN doping-channel high electron mobility transistors, and the influence of doped thickness on AlGaN/GaN doping-channel high electron mobility transistors will be included. The structures were designed as follows: (1) AlGaN/GaN doping-channel high electron mobility transistor with channel doping region thickness of 20 nm (called Device A). (2) AlGaN/GaN high electron mobility transistor without GaN doping-channel layer (called Device B). (3) AlGaN/GaN doping-channel high electron mobility transistor with a channel doping region thickness of 19.5, 19, 17.5, 15, 10, and 5 nm, respectively, and with a spacer close to the AlGaN/GaN heterojunction of 0.5, 1, 2.5, 5, 10, and 15 nm, respectively (called Devices C, D, E, F, G, and H). The device (Device A) was fabricated by metal-organic chemical vapor deposition system on a sapphire substrate. The experimental results exhibit a maximum drain saturation current of 506.9 mA/mm and a maximum transconductance of 52.475 mS/mm. Also, we will simulate the DC performance of device A with doping channel according to the experimental data. The simulated characteristics are close to the experimental results by choosing the proper parameters. Simulation results show that the 2DEG concentration of the device A is higher than the device B without the doping-channel layer. The doping channel will enable the 2DEG concentration to increase. However, the impurity scattering of carriers in the doping channel will lead to the electron mobility to decrease. The results show that the device A with a doping channel has poor output saturation current, transconductance, gate leakage current, breakdown voltage, and high-frequency characteristics. In addition, the doping layer of devices C, D, E, F, G, and H are away from the 2DEG. It can decrease the effect of impurity scattering. The result exhibits that the DC and high-frequency characteristics of the devices F, G, and H are better than the device B. In the devices F, G, and H, the 2DEG carrier concentrations are 1.158 × 1020, 1.155 × 1020, and 1.154 × 1020 cm-3, the maximum output currents are of 672, 682, and 689.7 mA/mm, and transconductance are 84.4, 87, and 89.4 mS/mm, respectively. Furthermore, the unity gain cut-off frequencies are 17.8, 18.1, and 18.3 GHz, and maximum oscillation frequencies are 28.3, 29.1, and 29.2 GHz respectively. * Author ** Advisor KEYWORDS : AlGaN/GaN, high electron mobility transistor, doping channel, impurity scattering
25
Wu, Tsung-Yeh, and 吳宗曄. "A Novel Dilute Antimony InGaAsSb Channel High Electron Mobility Transistor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/08327497435796958237.
Анотація:
碩士國立成功大學
微電子工程研究所碩博士班
94
This work reports, a high electron-mobility transistor (HEMT) using a dilute antimony In0.2Ga0.8As(Sb) channel, grown by the molecular beam epitaxy (MBE) system. The advantages by introducing the surfactant-like Sb atoms during growth of InGaAsN/GaAs quantum well (QW) consist of the suppression of the three-dimensional growth and the improved interfacial quality of the QW heterostructure. Besides, the present device exhibits better dc characteristics, highly stable thermal and frequency characteristics due to the improvement in the channel layer quality by using an In0.2Ga0.8As(Sb) channel. Distinguished device characteristics for GaAs/In0.2Ga0.8As(Sb) HEMT and conventional GaAs/In0.2Ga0.8As HEMT, with the gate dimensions of 1.2*200um2, include thermal threshold coefficient (¶Vth/¶T) is low to be -1.54 (-1.77) mV/K, gate-voltage swing (GVS) of 1.17 (1.15) V, peak extrinsic transconductance (gm, max) of 178 (166) mS/mm, and the current drive capability (IDSS) of 171 (157) mA/mm. The microwave characteristics for GaAs/In0.2Ga0.8As(Sb) HEMT and conventional GaAs/In0.2Ga0.8As HEMT, the unity gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are 25.6 (20.6) GHz and 28.3 (25.6) GHz, respectively.
26
Deen, David A. "Fabrication of ultra-shallow channel AlN/GaN high electron mobility transistors." 2007. http://etd.nd.edu/ETD-db/theses/available/etd-04262007-153718/.
Анотація:
Thesis (M.S.E.E.)--University of Notre Dame, 2007.Thesis directed by Huili (Grace) Xing for the Department of Electrical Engineering. "April 2007." Includes bibliographical references (leaves 72-73).
27
Shih, Pao-chen, and 施寶鎮. "Channel Estimation and Equalization for DVB-T in High-mobility Environment." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/62842899722177665736.
Анотація:
碩士國立中央大學
通訊工程研究所
95
DVB-T is an OFDM system, which exhibits outstanding characteristics in terms of simplicity in combating multi-path transmission and efficiency in spectral utilization. The ISI effect results from the multi-path interference could be successfully eliminated by the insertion of cyclic-prefix and the use of multi-carriers. In high-mobility environment, DVB-T signals pass the time-varying channel, and a loss of sub-carrier orthogonality due to Doppler spread of received signals leads to inter-carrier interference (ICI).This ICI effect degrades the maximum allowed velocity of reception. For eliminating this ICI effect due to high-mobility reception, this thesis modifies other’s methods and introduces a method about channel estimation and equalization, which is suitable high-mobility reception. Some ICI estimation schemes, which using first order linear model to approximate the channel variations, have been developed. This thesis compares three different schemes of ICI estimation, which two is first order model and the other is second order model, and iteratively repeats ICI cancellation to improve the maximum allowed velocity of reception. This modified method improves the normalized Doppler frequency from 8.6% to 13% for DVB-T signals in 8K mode、16QAM、code-rate=1/2.
28
Chiu, Pei-chin, and 邱培晉. "Molecular Beam Epitaxial Growth of Antimonide-based High Mobility Channel Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/72515159639586580231.
Анотація:
博士國立中央大學
電機工程學系
102
Along with the increase in device density of Si-based integrated circuits, power consumption and heat dissipation have become key issues that cannot be ignored any more. Replacing Si with high mobility materials to realize high performance transistors with low operating voltage and power consumption is thus a subject under extensive investigations. Among the materials under investigations, III-V compounds are considered one of the most promising candidates. Sb-based compounds have therefore received a lot of attention due to their high intrinsic carrier mobility and low bandgap. However, high performance p-channel transistors and the integration of Sb-based devices on Si substrates remain challenging. To explore the feasibility of the approach above, this work aims at the growth of high quality n-channel InAs/AlSb quantum-well (QW) and p-channel InGaSb/AlSb QW heterostructure field-effect transistors (HFETs) on GaAs and Si substrates by molecular beam epitaxy. Through the adjustments in layer structures and growth parameters, InAs/AlSb QW HFETs grown on GaAs substrates show electron mobility greater than 27,000 cm2/V•s at room temperature. As for InGaSb/AlSb QW HFETs grown on GaAs substrates, hole mobility higher than 1,000 cm2/V•s at room temperature has also been achieved. It is found that the buffer layers employed for the growth of InAs/AlSb QW HFETs on GaAs substrates do not give satisfactory results when used for the growth on Si substrates. In this study, AlSb/GaSb and GaAs/GaAsSb/GaSb are used as the initial buffer layer for the growth on Si substrates and how the buffer layer affect the properties of QW HFETs is explored. In the case of AlSb/GaSb buffer, there occur numerous edge dislocations, which do not propagate to the channel, at the AlSb/Si interface to accommodate the lattice mismatch. This buffer also generates numerous planar defects, i.e. twins, which deteriorate the growth of the InAs channel and the electrical properties of the transistors. Besides, parallel conduction of this buffer layer due to its low resistivity is observed. In contrast, the GaAs/GaAsSb/GaSb buffer layer can effectively block the planar defects at GaAsSb/GaSb interface and suppress parallel conduction of the buffer. As a result, the anisotropic transport behavior is greatly reduced. With an approximately 2 m-thick buffer layer, electron mobility as high as 18,100 cm2/V•s has been achieved on InAs/AlSb QWs grown on Si. P-channel InGaSb/AlSb QW HFETs grown on Si with GaAs/GaAsSb/GaSb buffer layers are also investigated. The growth temperature of InGaSb/AlSb QW is found to be a key parameter for obtaining high hole mobility. By optimizing the growth temperature and layer structure, room-temperature hole mobility of 838 cm2/V•s with sheet carrier density of 9.5×1011 cm-2 has been reached. It is also found that the effects of twins on the electrical properties of InGaSb/AlSb QW HFETs are unobvious. In collaboration with Professor Yu-Ming Hsin, devices with a gate length of 0.25 m are fabricated and exhibit a maximum drain current of 81 mA/mm and a peak transconductance of 75 mS/mm.
29
Liu, Ju-Chieh, and 劉如傑. "Channel Tracking Techniques for the High-Mobility Wireless Access in Vehicular Environments." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/89250474019104851485.
Анотація:
碩士國立中正大學
通訊工程研究所
95
The industrial standard of Wireless Access Vehicular Environment (WAVE), or called the IEEE 802.11p standard, is an example of the orthogonal frequency division multiplexing (OFDM) technique applied to the high-mobility environment. In addition to the multipath effect, the high-mobility environment introduces severe fading to the received signals. Tracking of the channel state information becomes the critical issue for such high-mobility system. Based one the conventional decision-directed channel tracking (DDCT) algorithm, we proposes a modified decision-directed channel tracking (MDDCT) algorithm. Our proposed algorithm is shown to have approximately equal uncoded bit error rate (BER) to that of the conventional DDCT algorithm, but have significant lower packet error rate than that of the conventional DDCT algorithm under a variety of high-mobility environments. After comparing the error patterns of the uncoded bits that are demodulated by the conventional and our MDDCT algorithms, we observe that our MDDCT algorithm mitigates the burst error; hence, the following error correction decoder works more effectively to improve its packet error rate. Finally, our MDDCT is of very low complexity, and is of practical use.
30
Kao, Shiang-Lun, and 高祥倫. "Joint Time and Frequency Domain Channel Estimation for High-Mobility OFDM Systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/4c87pj.
Анотація:
碩士國立交通大學
電信工程系所
95
In time-variant OFDM systems, channel estimation usually relies on pilot subcarriers. However, the number of pilot subcarriers is usually limited. Channel estimation is then a critical task for receiver design. In this thesis, we first propose a two-dimension slide-window channel estimator for IEEE802.16e systems. The estimator can outperform conventional approaches and requires low-complexity. To further improve the performance, we then propose a high-performance least-squares (LS) channel estimator, joint operated in the time and frequency domains. The main idea is use the channel response, estimated in the frequency domain, to locate significant time-domain channel taps, and then use the LS method to estimate the responses in those taps. With an iterative algorithm, we can then obtain accurate channel estimate with computational complexity much lower than the conventional time domain LS estimator.
31
Hsu, Hua-Lin, and 徐華璘. "Channel Estimation and Equalization for multiple antennas OFDM System in High-mobility Environment." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/40862646414350085067.
Анотація:
碩士國立中央大學
通訊工程研究所
96
DVB-T is an OFDM system, which exhibits outstanding characteristics in terms of simplicity in combating multi-path transmission and efficiency in spectral utilization. The ISI effect results from the multi-path interference could be successfully eliminated by the insertion of cyclic-prefix and the use of multi-carriers. In high-mobility environment, DVB-T signals pass the time-varying channel, and a loss of sub-carrier orthogonality due to Doppler spread of received signals leads to inter-carrier interference (ICI).This ICI effect degrades the maximum allowed velocity of reception. For eliminating this ICI effect due to high-mobility reception, this thesis modifies other’s methods and introduces a method about channel estimation and equalization, which is suitable high-mobility reception. In this thesis, we refer to the DVB-T standard, and further make it suitability for high mobility environment.We use multiple antennas technique and ICI cancellation,compares three different scheme for channel and ICI estimation. This thesis proposed method improve the maximum allowed velocity as high as 250km/h for DVB-T receiver with SISO in 8K mode、16QAM、code-rate=1/2,and multiple antennas DVB-T reception improve the maximum allowed velocity more then 300km/h.Finally, reception use group pilot estimation technique SISO-DVB-T-like can work as 300km/h.
32
Chen, Lu-An, and 陳履安. "Investigation of InGaP/InGaAs/GaAs Double Channel Pseudomorphic High Electron Mobility Transistors (DCPHEMTs)." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/12622329745360255337.
Анотація:
碩士國立宜蘭大學
電子工程學系碩士班
96
In this thesis, the device characteristics of InGaP/InGaAs/GaAs double channel pseudomorphic high electron mobility transistors (DCPHEMTs) with triple delta-doped sheets are systematically investigated. The triple delta-doped sheets densities and Schottky barrier layer thickness are important factors to affect device performance. Based on a two-dimensional simulator of Atlas, we report on detailed calculations and studies including energy band diagrams, distribution of carrier, DC and microwave performance. Due to the employed InGaAs DC structure and Schottky and buffer behaviors of InGaP “insulator”, good pinch-off and saturation characteristics, high current drivability, large transconductance and excellent microwave performance are obtained. For comparison, a practical DCPHEMT with good device performance is fabricated successfully. Generally, good agreements between experimental results and theoretical simulations are found. Therefore, it is concluded that the DCPHEMT with appropriate triple delta-doped sheets densities offers the promise for microwave device applications.
33
Ro, En-Go, and 羅炎國. "Investigation of InP-based high electron mobility transistor using InGaAs and InGaAsP channel." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/32333495645205187797.
Анотація:
碩士國立成功大學
微電子工程研究所碩博士班
91
In this paper, we have successfully improved the breakdown characteristics of InP lattice matched HEMT by using the undoped cap layer and triple channel respectively. By using undoped cap layer we can reduce the electric field between drain and gate. Due to its lower electric field, kink effect can be reduced. By using triple channel, we can combine the advantages of InP (higher mobility in high field and larger bandgap than InGaAs) and InGaAs (high peak mobility in low field). Besides, InP (1.34 eV) and InGaAsP (0.8 eV) layers can increase effective channel bandgap when compared to InGaAs (0.75 eV) channel. Our experiments show that the breakdown voltage can be improved from 8 V (our lattice match HEMT) to 16.6 V (undoped cap HEMT) and 18.1 V (triple channel HEMT). In addition, we have also improved the microwave performance of our InP lattice matched HEMT by using the graded channel and pseudomorhpic respectively. Comparing with our InP lattice matched HEMT, the graded channel can confine carriers at the bottom of the channel thus reduce the interface scattering and electric field. Comparing with our InP lattice matched HEMT, pseudomorhpic HEMT can also improve the performances because of its better carrier confinement and lower effective carrier mass. Our experiments show fT can be improved from 15.2 GHz (InP lattice matched HEMT) to 21.2 GHz (graded channel) and 20.5GHz (pseudomorphic).
34
Su, Ning-Xing, and 蘇寧興. "Investigation of AlInAs/GaInAs High Electron Mobility and Doped-Channel Field-Effect Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/389v57.
Анотація:
碩士國立高雄師範大學
物理學系
97
In this thesis, the ternary compound semiconductor devices, i.e., AlInAs/GaInAs high electron mobility transistor (HEMT) and doped-channel field-effect transistor (DCFET) are analyzed and compared. The electron distribution DC and the high-frequency characteristics are depicted and demonstrated. First, the AlInAs/GaInAs HEMT employs a delta-doped sheet inserted between AlInAs barrier layer and spacer layer, to from more carriers in the triangle quantum well and enables the two-dimensional electron gas (2DEG) to increase. Comparably, HEMT has better transconductance and high-frequency characteristics. However, it shows the poor device linearity. But, due to HEMT have parallel-conduction existence, which will introduce considerably large gate current, and lower gate turn-on voltage. In addition, due to the high channel resistance value, therefore the drain output current is small. The channel of device AlInAs/GaInAs DCFET is uniformly doped. Although the high electron mobility is not so high the channel effective carrier concentration is big effectively. Its channel resistance is low, so it exhibits high drain output current. Furthermore, the gate is directly sitting on the undoped layer, and it shows larger gate turn-on voltage and broad gate swing. Significantly, not obvious gate leakage current is observed. Also, it shows good device linearity. But has the lower transconductance and high-frequency characteristics. Under simulated results, for the DCFET not parallel-conduction exists, and the gate is directly sitting on the undoped barrier layer. Thus, it has the better DC characteristics than the HEMT. However, for the HEMT due to the high 2DEG it shows large transconductance and the good high-frequency characteristics.
35
Chang, Chia-Yuan, and 張家源. "The Study of InAs-Channel High Electron Mobility Transistors for High Frequency and Ultra-Low Power Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/70478511755630612263.
Анотація:
博士國立交通大學
材料科學與工程學系
98
High performance InAs-channel high electron mobility transistors (HEMTs) have been fabricated and characterized for high frequency and high speed logic low-power consumption applications. The performance of the InAs-channel HEMTs was improved by optimizing the device structure and using a sub-micron gate. The epi-structure, layout design and electrical measurements of the devices are discussed in details in this dissertation. In this study, a 70-nm In0.52Al0.48As/In0.6Ga0.4As power MHEMT with double δ-doping was fabricated and evaluated. The device has a high transconductance of 827 mS/mm. The saturated drain-source current of the device is 890 mA/mm. A current gain cutoff frequency (fT) of 200 GHz and a maximum oscillation frequency (fmax) of 300 GHz were achieved due to the nanometer gate length used and the high Indium content in the channel. When measured at 32 GHz, the 0.07 × 160 μm¬2 device demonstrates maximum output power of 14.5 dBm (176 mW/mm) and P1dB of 11.1 dBm (80 mW/mm) with 9.5 dB power gain. The excellent DC and RF performance of the 70-nm MHEMT shows a great potential for Ka-band power applications. In order to further enhance the performance, the indium content of the InxGa1-xAs channel was increased to 100 % to form an InAs-channel HEMT. A high current gain cutoff frequency (ft) of 310 GHz and a high maximum oscillation frequency (fmax) of 330 GHz were obtained at VDS = 0.7 V due to the high electron mobility in the InAs channel. Performance degradation was observed on the cutoff frequency (ft) and the corresponding gate delay time for logic applications caused by impact ionization due to a low energy bandgap in the InAs channel. DC and RF characterizations on the device have been performed to determine the proper bias conditions in avoidance of the performance degradations due to the impact ionization. With the design of InGaAs/InAs/InGaAs composite channel, the impact ionization was not observed until the drain bias reached 0.7 volt, and at this bias the device demonstrated very low gate delay time of 0.63 psec. The high performance of the InAs/InGaAs HEMTs demonstrated in this study shows its great potential for high speed and very low power logic applications. In the issue of power consumption, InAs-channel HEMT for ultralow-power low-noise amplifier (LNA) applications has been characterized. Small-signal S-parameter measurements performed on the InAs-channel HEMT at a low drain-source voltage of 0.2 V exhibited an excellent fT of 120 GHz and an fmax of 157 GHz. At an extremely low level of dc power consumption of 1.2 mW, the device demonstrated an associated gain of 9.7 dB with a noise figure of less than 0.8 dB at 12 GHz. Such a device also demonstrated a higher associated gain and a lower noise figure than other InGaAs-channel HEMTs at extremely low dc power consumption. These results indicate the outstanding potential of InAs-channel HEMT technology for ultralow-power space-based radar, mobile millimeter-wave communications and handheld imager applications. In search of an alternative device for beyond Si-CMOS, n-type metal-oxide-semiconductor HEMT (MOS-HEMT) devices with an InAs-channel using atomic-layer-deposited Al2O3 as gate dielectric have been fabricated and characterized. Device performance of a set of scaled transistors with and without high-k gate dielectric Al2O3 have been compared to determine the optimum device structure for low-power and high-speed applications. Measurement results revealed that the high-performance InAs-channel MOS-HEMTs with ALD Al2O3 gate dielectric can be achieved if the structure is designed properly.
36
Cheng, Chia-Chen, and 鄭佳臻. "Channel Tracking and Signal Recovery of the MIMO-OFDM System Under High-Mobility Environment." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/39190176809544785575.
Анотація:
碩士國立中正大學
通訊工程學系
98
The multiple antennas and OFDM technologies are being considered as a possible solution to provide high data rate for the high-throughput wireless local area network (WLAN). Channel model is time-variant fading channel due to the multipath and doppler effects in high-mobility wireless environment. Based on the spatial channel model, several channel tracking and signal recovery techniques are compared in this thesis. Initially, least squared (LS) criterion is exploited to the received long training sequences in the preamble of IEEE 802.11n frame. Several adaptive channel tracking algorithms follow to track the variation of the channel/weight frequency responses. Our simulation results show that using recursive least square algorithm to track the variation of the channel frequency responses is yield better performance than to track the variation of the weight frequency responses. The ordered successive interference cancellation algorithm can be utilized to improve performance at the cost of higher computational complexity.
37
Yuan, Wen-Hao, and 袁文浩. "A Study on Channel Estimation Algorithms for WCDMA System in Very High Mobility Environment." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/01774728996074187961.
38
Wu, Shu-Hua, and 吳杼樺. "Theoretical Investigation of Electrostatic Integrity for Tri-Gate MOSFETs with High Mobility Channel Materials." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/s7thdn.
Анотація:
博士國立交通大學
電子工程學系 電子研究所
104
This dissertation provides an analytical subthreshold model for tri-gate MOSFETs with thin buried-oxide (BOX). This model shows a fairly good scalability in substrate bias (Vbs) and BOX thickness, which is crucial to the prediction of multi-threshold (multi-Vth) modulation through Vbs. In addition, we demonstrate the application of our model in multi-Vth device design for tri-gate germanium-on-insulator (GeOI) p-MOSFETs with the body-effect coefficient (γ) over a wide range of design space efficiently examined. We have shown an enhanced multi-Vth modulation behavior in tri-gate GeOI p-MOSFETs. Our study indicates that, for a given subthreshold swing and γ, the GeOI tri-gate p-MOSFET can possess a higher fin aspect-ratio than the silicon-on-insulator (SOI) counterpart. Through theoretical calculation by analytical solution corroborated with TCAD numerical simulation, we investigate the intrinsic drain-induced barrier lowering (DIBL) characteristics for tri-gate GeOI p-MOSFETs. It is found that, relative to the SOI counterpart, there exists a built-in negative substrate bias in the GeOI PFET. This built-in effective substrate bias is intrinsic to the GeOI p-MOSFET with Si substrate. It stems from the large discrepancy in the source-to-substrate work-function difference between the GeOI and SOI PFET because of the smaller bandgap of Ge, thus pulling the carriers toward the channel/BOX interface and degrading the DIBL of the GeOI PFET beyond what permittivity predicts. In addition, the built-in effective substrate bias also impacts the DIBL of Ge tri-gate PFETs on bulk substrate. This new mechanism has to be considered when designing or benchmarking tri-gate Ge p-MOSFETs. Besides, this effect also explains the enhanced multi-Vth modulation behavior in tri-gate GeOI p-MOSFETs. A quantum-mechanical subthreshold model for tri-gate devices is also proposed and verified with numerical simulation in this dissertation. The wavefunction penetration into high-k gate-dielectric and BOX has been considered, and the impact of short-channel effects on the eigen-energy has also been included through the treatment of perturbation. By using our quantum-mechanical subthreshold model together with numerical simulation, we investigate the intrinsic DIBL characteristics of highly-scaled tri-gate n-MOSFETs with InGaAs channel based on ITRS 2021 technology node. Our study indicates that, when studying short-channel effects in III-V FETs, one has to account for quantum-confinement, or else predictions will be pessimistic. Due to 2-D quantum-confinement, the DIBL of the InGaAs tri-gate devices can be significantly suppressed and be comparable to the Si counterpart. Besides, for highly-scaled InGaAs tri-gate NFETs, the impact of buried-oxide thickness on DIBL becomes minor, and the DIBL sensitivity to the fin-width and gate-length variations can also be suppressed by the quantum-confinement effect. Our study may provide insights for tri-gate device design using III-V high-mobility channel materials.
39
Liao, Keng-te, and 廖耕德. "Improvment of Channel Estimation and Equalization for MISO OFDM System in High Mobility Environment." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/23018288731098586695.
Анотація:
碩士國立中央大學
通訊工程研究所
99
OFDM systems exhibit advantageous characteristics in combating multi-path transmission and spectral efficiency, which use cyclic-prefix to overcome the inter-symbol interference (ISI) effect caused in multi-path transmission and multi-carriers with orthogonality to achieve high spectral efficiency. In high mobility environment, when the orthogonal multi-carrier signal passes through time-varying channel, inter-carrier interference (ICI) is resulted due to the loss of orthogonality of subcarriers. The degradation of the system performance due ICI is proportional to the Doppler spread, and thus a limitation in the velocity of the mobile receiver is inferred in OFDM systems. In this thesis we study on using transmitter diversity to improve the performance of OFDM systems in high mobility environment. We propose a modification of the transmitter diversity technique in DVB-T2 standard, which is designed originally for fixed reception, to make it more suitable for high mobility reception. vi
40
Chung, Wei-Cheng, and 張偉成. "Improved Symmetric Graded InxGa1-xAs (x=0.12→0.18→0.12) Channel High Electron Mobility Transistor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/48189080068037583851.
Анотація:
碩士國立成功大學
微電子工程研究所碩博士班
93
In this thesis, the symmetrical graded channel AlGaAs / InxGa1-xAs (x=0.12→0.18→0.12) High Electron Mobility Transistors have been successfully fabricated by metal organic chemical vapor deposition (MOCVD) system, and we improved their characteristics. By thinning undoped AlGaAs Schottky layer, the device performance can be proved. The results show that the thinner Schottky layer can enhance the pinch-off characteristic and extrinsic transconductance obviously. The maximum extrinsic transconductance is about 178 mS/mm and it，s ft and fmax is 19.3 GHz and 50.1 GHz. At 2.4 GHz, the output power is 16.37dBm, and the NFmin is 0.72dB. In order to improve the characteristics of our devices, we reduce the recess width. Their recess width is 3 µm, 5 µm, and 7_3 µm (double recess), respectively. It，s maximum extrinsic transconductance could be from 178 mS/mm to 220 mS/mm. It，s maximum drain current density is from 420 mA/mm to 480 mA/mm. It，s ft could be from19.3 GHz to 23.75 GHz and it，s fmax could be from 50.1 to 71.6 GHz. Although HEMTs with recess width =3 µm could ameliorate a great part of DC performance, their breakdown voltage is from -32V to -11V. The result limits the power characteristics. The output power is from 16.37 dBm to 15.78 dBm. So we use the double-recess process. Although we sacrifice a little extrinsic transconductance (202 mS/mm)，we could get higher breakdown voltage (-28V) and improve it，s power characteristics. The output power is from 16.37 dBm to 17.42 dBm. The temperature-dependent characteristics of symmetrical graded channel AlGaAs / InxGa1-xAs (x=0.12→0.18→0.12) HEMTs with different recess width and double-recess [10-15] width have also been studied. Because of improving DC characteristics of symmetrical graded channel AlGaAs / InxGa1-xAs ( x=0.12→0.18→0.12) HEMTs，the RF, power, and noise characteristics could be ameliorated effectively.
41
Huang, Xiang-yuan, and 黃祥原. "Practical Channel Tracking and Signal Recovery for the OFDM System Under High-Mobility Environment." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/16209554312044403159.
Анотація:
碩士國立中正大學
通訊工程研究所
96
WAVE (IEEE802.11p) standard is proposed to use in high-mobility environment and used OFDM as the modulation scheme. Because of the high-mobility, the received signal is interfered by the multipath and Doppler. The time-variant fading channel model is considered. In this paper, a channel tracking and recovery technique is proposed for high-mobility environment. With an initial channel estimation based on preamble by Least Square (LS) algorithm, the channel frequency response is tracked by adaptive filters. We can find some conclusions after analyzing simulations. The first, Recursive Least Square (RLS) algorithm, robust Recursive Least Square (rRLS) algorithm, and Adaptive forgetting factor Recursive Least Square (AFRLS) algorithm can efficiently slow down the phenomenon of error floor than Least Mean Square(LMS) algorithm, Normalized Least Mean Square(NLMS) algorithm, and Adaptive step size Least Mean Square(ASLMS) algorithm. The second, rRLS, RLS, and AFRLS have better performance when under the environment of accelerating the speed of vehicle or increasing the packet length. The third, After a comparison of robust Recursive Least Square (rRLS) algorithm, Recursive Least Square (RLS) algorithm, and Adaptive forgetting factor Recursive Least Square (AFRLS) algorithm can find that rRLS have better performance than RLS and rRLS have lower computation complexity than AFRLS. Finally, we can find the best value of forgetting factor of RLS by [5] under the time-variant fading channel model.
42
Che-Fang, Yeh, and 葉哲芳. "Design and Simulation of A New Channel Estimation Method for High Mobility OFDM Systems." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/82225822106576676202.
Анотація:
碩士國立交通大學
電信工程系所
94
Channel estimation is an important issue for high mobility OFDM systems in multipath fading channels. In demand of high data transmission rate, a channel estimation method without loss of too much bandwidth efficiency is critical, especially in fast fading channels. We propose a semi-blind channel estimation method which consists of an MPIC-based initial channel estimator, followed by an adaptive Newton tracker to track channel variations in the subsequent OFDM symbols. It is worth to mention that only sparse pilots are needed to track channel impulse responses. Moreover, there are no restrictions on the preamble structure in the initial channel estimator and no restrictions on the locations of the sparse pilots in the tracking stages as well. Thus, the semi-blind channel estimation method can be generally applied to OFDM systems. In this thesis, the initial channel estimator is simulated with the preamble defined in IEEE 802.16 OFDM mode, and the adaptive Newton tracker is verified in high mobility channels (120 km/hr and 240 km/hr).From the simulation results, we can find that the semi-blind channel estimation method performs very well in terms of bit error rate. In conclusion, the semi-blind channel estimation method can achieve both bandwidth efficiency and estimation accuracy.
43
Yang, Kun-How, and 楊坤浩. "Successive ICI Cancellation and Recursive Channel Re-Estimation for High-Mobility MIMO-OFDM Systems." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/17348529292852866608.
Анотація:
碩士國立交通大學
電信工程系所
94
Conventionally, the channel response for an OFDM system is assumed to be quasi-static, i.e., time-invariant in an OFDM symbol. In high-speed mobile environments, however, the assumption is no longer hold. The time-variant channel will destroy the orthogonality of subcarriers and result in intercarrier interference (ICI). Successive ICI cancellation (SIC) has been successfully applied to mitigate this problem. However, its performance greatly depends on the accuracy of channel estimation. In this thesis, we propose recursive channel re-estimation schemes to enhance the performance of SIC. The main idea is to use the successive outputs from SIC as additional pilots and conduct channel re-estimation recursively. One problem associated with the SIC is its large processing delay. To solve the problem, we then propose a windowing design such that the ICI effect can be reduced and a simplified SIC method can be applied. Simulations show the proposed methods can effectively mitigate the ICI effect induced by the high mobility problem.
44
Wu, Jan-Yang, and 巫朝陽. "The Setup of Temperature-Dependent Hall Measurement System and the Study of High Mobility Channel." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/54932881733824003793.
Анотація:
碩士國立交通大學
電子工程系所
97
In this work, we construct a temperature-dependent Hall measurement system which contains a cryostat and electromagnet with a current source changable in amplitude and direction to measure the modulation-doped high electron mobility sample grown by molecular beam epitaxy(MBE) . With changing the gate voltage ,we obtained dependence between sample mobility and concentration.By use of temperature-dependent and gate voltage-dependent Hall measurement ,we know that which scattering mechanisms dominate in sample mobility.In additional,we could also figure out the shallow and deep doping level in the sample.After replacing the O-ring of cyro-pump to gasket in MBE system,the sample mobility have been improved greatly. Under low temperature and high magnetic field, we measured quantum Hall effect of high mobility sample and found that the decreasing of ionized impurities in newly grown sample results in higher mobility. Finally, we fabricate split gate by electron-beam lithography in higher mobility sample and the split gate pinched off successfully.
45
Chiu, Han-Chin, та 邱漢欽. "High-κ dielectrics on high carrier mobility InGaAs: achieving low interfacial density of states and high-performance self-aligned inversion-channel MOSFETs". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/44870147171774566358.
46
Zhao, Han 1982. "A study of electrical and material characteristics of III-V MOSFETs and TFETs with high-[kappa] gate dielectrics." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2184.
Анотація:
The performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over three decades. As Si complementary metal-oxide-semiconductor (CMOS) scaling is approaching the physical and optical limits, the emerging technology involves new materials for the gate dielectrics and the channels as well as innovative structures. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Hence, there have been tremendous research activities to explore the prospects of III-V materials for CMOS applications. Nevertheless, the key challenges for III-V MOSFETs with high-[kappa] oxides such as the lack of high quality, thermodynamically stable insulators that passivate the gate oxide/III-V interface still hinder the development of III-V MOS devices. The main focus of this dissertation is to develop the proper processes and structures for III-V MOS devices that result in good interface quality and high device performance. Firstly, fabrication processes and device structures of surface channel MOSFETs were investigated. The interface quality of In[subscript 0.53]Ga[subscript 0.47]As MOS devices was improved by developing the gate-last process with more than five times lower interface trap density (D[subscript it]) compared to the ones with the gate-first process. Furthermore, the optimum substrate structure was identified for inversion-type In[subscript 0.53]Ga[subscript 0.47]As MOSFETs by investigating the effects of channel doping concentration and thickness on device performance. With the proper process and channel structures, the first inversion-type enhancement-mode In[subscript 0.53]Ga[subscript 0.47]As MOSFETs with equivalent oxide thickness (EOT) of ~10 Å using atomic layer deposited (ALD) HfO₂ gate dielectric were demonstrated. The second part of the study focuses on buried channel InGaAs MOSFETs. Buried channel InGaAs MOSFETs were fabricated to improve the channel mobility using various barriers schemes such as single InP barrier with different thicknesses and InP/InAlAs double-barrier. The impacts of different high-[kappa] dielectrics were also evaluated. It has been found that the key factors enabling mobility improvement at both peak and high-field mobility in In[subscript 0.7]Ga[subscript 0.3]As quantum-well MOSFETs with InP/InAlAs barrier-layers are 1) the epitaxial InP/InAlAs double-barrier confining carriers in the quantum-well channel and 2) good InP/Al₂O₃/HfO₂ interface with small EOT. Record high channel mobility was achieved and subthreshold swing (SS) was greatly improved. Finally, InGaAs tunneling field-effect-transistors (TFETs), which are considered as the next-generation green transistors with ultra-low power consumption, were demonstrated with more than two times higher on-current while maintaining much smaller SS compared to the reported results. The improvements are believed to be due to using the In[subscript 0.7]Ga[subscript 0.3]As tunneling junction with a smaller bandgap and ALD HfO₂ gate dielectric with a smaller EOT.text
47
Lee, Ching-Sung, and 李景松. "Analytic Modeling for Device Characteristics of Doped-Channel Field-Effect Transistors and High Electron Mobility Transistors." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/bv4mpb.
Анотація:
博士國立成功大學
電機工程學系碩博士班
90
In this dissertation, we have proposed analytic theories for the δ-HEMT and PDCFET by solving the two-dimensional Poison equation in a straightforward manner. The velocity overshoot phenomenon associated within the low effective mass and large Γ-L separation in the channel compounds has also been included in deriving the device model. Device optimization from the analytic modeling the PDCFET has been studied. In addition, one of the significant short-channel effects, the drain-induced barrier-lowering (DIBL) phenomenon, has also been investigated explicitly based on the proposed model. For characterizing the δ-HEMT device performance, the self-consistent method was employed to develop the two-dimensional electron gas (2DEG) on the gate voltage according to the charge control law. With the aids of the Giblin-Scherer-Wierich (GSW) velocity-field relation, the current-voltage characteristics have been calculated and discussed. The current contribution from the gate-drain spacing has been included to improve the device model by solving the 2D Poisson equation. Moreover, the analytic model has been presented for the first time to characterize the off-state two-terminal gate-drain breakdown phenomenon of the δ-HEMT devices. The combined effects of the thermionic-field emission induced tunneling gate current and the impact-ionized Auger multiplication along the gate-drain transverse electric field have resulted in the off-state breakdown criteria. Comparable expectations from the proposed analytic models have been achieved with respect to the experimental results. Since the potential profile of the gate-drain regime can be well described by directly solving the 2D Poisson equation, this model can be extended for various HFET structures. In summary, the presented analytic models can provide in-depth understanding of the device physics in explicit mathematical expressions. The calculated results demonstrate in excellent agreement with the empirical work. By means of the analytic device model, convenient design platform can be realized to optimize the device performance. The promising extensions of this work have also been concluded for future research including the direct application for extracting the microwave device parameters, for characterizing the graded-composition channel or step-graded multi-channels HFET’s, and for investigating the subthreshold current for complementary HFET’s.
48
Chien, Wei-Ting, and 簡煒庭. "Investigation on Double Recess of InAlAsSb/InGaAsSb Metamorphic High Electron Mobility Transistor with Symmetrically-Graded Channel." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/62604101294490967695.
Анотація:
碩士逢甲大學
電子工程所
98
This work reports, high electron mobility transistors (HEMTs) using a In0.34Al0.66As0.85Sb0.15 Schottky contact layer and dilute-Sb symmetrically-graded InxGa1-xAs1-ySby channel , grown by molecular beam epitaxy (MBE) system. Introducing Sb can be further integrated into InGaAs channel to serve as a surfactant-like dopant to smooth the interface and further reduce the effective bandgap of the InGaAs channel. Besides, a high wide-gap InAlAsSb Schottky contact layer was devised to reduce the gate leakages and improved device performance. Comparisons of device performances by using different gate recess and gate alloys have been made, including forming a Ni/Au gate on the InP layer, a Ni/Au gate on the InAlAsSb layer, and a Pt/Au gate on the InAlAsSb layer, respectively. They have demonstrated superiorly the maximum extrinsic transconductance (gm, max) of 280 (304/349) mS/mm, two-terminal gate-drain breakdown (BVGD) of -5.3(-9.7/-15) V, turn on voltage (Von) of 0.71(0.87/1.08)V, threshold voltage (Vth) of -2.44(-2.35/-2.23)V, the unity current gain cut-off frequency fT 33.74(40.1/47.4) GHz, the maximum oscillation frequency fmax of 45.3(50.2/60.2) GHz and the P.A.E. characteristic 29.6 (36.7/46.5) % at 300 K, with the gate dimensions of 1.2 × 100 µm2. From experimental results, using the devised dilute-Sb symmetrically-graded channel and the structure of a Pt/Au-gate on InAlAsSb layer exhibited the lowest output conductance, the highest voltage gain, the best breakdown voltage and power performances. Consequently, the InAlAsSb/InGaAsSb MHEMTs is suitable for high-power with best breakdown MMIC applications. Keywords: InGaAsSb, Symmetrically-graded channel, InAlAsSb Schottky contact layer
49
Chang, Pen, та 張翔筆. "Interface engineering between high-κ dielectrics and III-V high mobility channel materials for passivation enabling the technology beyond Si CMOS". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/26050156900427811103.
Анотація:
博士國立清華大學
材料科學工程學系
100
The High-κ/Metal-Gate plus III-V high mobility channel materials is regarded as a urgent issue for achieving high performance and low power dissipation complementary metal-oxide-semiconductor (CMOS) technology beyond 15 nm node. A combination of electrical, chemical, and structural characterization methods to evaluate the MOS interface passivation quality. The interface engineering of in-situ directly deposited not only rare-earth oxide (REOs) but also HfO2-based high-κ dielectrics on III-V surface exhibited the successful passivation, in terms of low interfacial density of states (Dit) below 10e12 eV-1cm-2 without midgap peak, low equivalent oxide thickness (EOT) below 1 nm, low leakage current, both conduction band offset (ΔEc) and valence band offset (ΔEv) are larger than 1.5 eV, and truly high thermal stability higher than 800 oC. Moreover, high performance of self-aligned gate first inversion-channel MOS field-effect-transistors (MOSFETs) have achieved steep subthreshold swing (SS) value below 100 mV/dec, a maximum drain current (Id,max) of 1.5 mA/μm, a maximum transconductance (Gm) of 0.77 mS/μm, and a peak field-effect mobility (μFE) of 2100 cm2/Vs. This work suffices the key for realizing ultimately scaled devices with really high performance.
50
Chen, Yunn-Wen, and 陳韻文. "Joint Channel Estimation and Data Detection Based on Polynomial Model and MMSE Equalization for High-Mobility OFDM Systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/68305852948216233548.
Анотація:
碩士國立交通大學
電機學院碩士在職專班電信組
96
For an orthogonal frequency division multiplexing (OFDM) systems applied in high mobility communication environment, time-variations of multi-path channel in one OFDM symbol duration destroys the orthogonality among subcarriers, resulting in intercarrier interference (ICI) and performance degradation. The affect becomes more severe when vehicle speed, carrier frequency or OFDM symbol interval increases. In this paper, a joint channel estimation and data detection method based on polynomial parametric channel model and MMSE equalization is proposed. We derive this method by formulating the joint channel estimation and data detection problem in a maximum likelihood estimation framework and adopt Newton’s method to find a search direction vector that is used to update the second order polynomial channel parameter, then utilize the MMSE equalization to achieve the purpose of ICI suppression. Computer simulation results are provided to verify the performance of the proposed method in high-mobility radio multipath fading channels.