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1
Zaka, Alban. "Carrier injection and degradation mechanisms in advanced NOR Flash memories." Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT118/document.
2
Tran, Thi-Phuong-Yen. "CMOS 180 nm Compact Modeling Including Ageing Laws for Harsh Environment." Thesis, Bordeaux, 2022. http://www.theses.fr/2022BORD0185.
Анотація:
Au cours des dernières décennies, la demande de fonctionnalités complexes et d'intégration haute densité pour les Circuits Intégrés (CI) a mené à une réduction de la taille des dispositifs métal-oxyde-silicium (MOS). Dans ce scénario, les problèmes de fiabilité sont les préoccupations considérables par suite de la miniaturisation de l'appareil, telles que Hot Carrier Injection (HCI) et Bias Temperature Instability (BTI) qui ont un impact sérieux sur les performances de l'appareil. Dans certains domaines d'application où le coût des pannes est extrêmement élevé, comme l'espace, les champs pétrolifères ou les soins de santé, l'appareil doit pouvoir fonctionner de manière stable et fiable, en particulier dans une plage de températures étendue. Bien que les mécanismes de défaillance des dispositifs aient été intensivement étudiés dans le passé, les investigations de ces mécanismes à hautes températures sont rarement étudiées.L'objectif de cette thèse est de développer les lois de vieillissement de la technologie CMOS 0.18µm afin d'optimiser la conception des circuits pour une durée de vie ciblée sous des températures extrêmes. Nous avons mené une campagne intensive de tests de vieillissement pour nMOS et pMOS avec plusieurs longueurs de grille. Les mécanismes HCI et BTI intrinsèques ont été caractérisés et modélisés sous des tensions de polarisation de fonctionnement typique pour éviter le risque de sur-accélération d'autres mécanismes d'usure qui ne sont pas censés être expérimentés dans l'application pratique. Notre expérimentation est un test à longue durée avec un temps de stress allant jusqu'à 2,000 heures. Cette thèse présente des résultats de mesure jusqu'à 230°C qui n'ont jamais été étudiés auparavant dans la littérature pour cette technologie.Les lois de vieillissement sont finalement intégrées dans un environnement de conception assistée par ordinateur (EDA) pour prédire l'évolution des paramètres électriques dégradés du transistor/circuit et l'estimation de la durée de vie en conséquence des effets du vieillissement. De plus, le test de fiabilité au niveau du circuit a été réalisé pour valider et vérifier les modèles de vieillissement proposés. Cette approche offre la possibilité d'évaluer et de simuler la dérive de spécification du CI due à l'effet du vieillissement dans la phase de conception précoceIn the past decades, the demand for complicated functionality and high-density integration for Integrated Circuits (ICs) has resulted in metal-oxide-silicon (MOS) devices' scaling down. In this scenario, the reliability problems are the considerable concerns due to the device miniaturization, such as Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) that seriously impact the device performance. In some application fields where the cost of failure is extremely high such as space, oilfield, or healthcare, the device must be able to stably and reliably work, especially at an extensive temperature range. Although device failure mechanisms have been intensively investigated in the past, the investigations of these mechanisms at high temperatures are seldom studied.This thesis aims to develop the aging laws for 0.18µm CMOS technology to optimize circuit design for a targeted lifetime under extreme temperatures. We conducted an intensive aging test campaign for both nMOS and pMOS featuring several gate lengths. The intrinsic HCI and BTI mechanisms were characterized and modeled under typical operating voltage biases to avoid the risk of overaccelerating other wear-out mechanisms that are not supposed to be experienced in practical application. Our experiment is a long-term test with a stress time of up to 2,000 hours. This thesis presents measurement results up to 230°C that have never been studied before in the literature for this technology.The aging laws are finally integrated into an electronic design automation (EDA) environment to predict the evolution of the degraded transistor/circuit electrical parameters and the lifetime estimation due to the aging effects. In addition, the reliability test at the circuit level has been performed to validate and verify the proposed aging models. This approach offers the possibility to assess and simulate the IC specification drift due to the aging effect in the early design phase and optimize the circuit design over lifetime
3
Li, Binhong. "Etude de l'effet du vieillissement sur la compatibilité électromagnétique des circuits intégrés." Thesis, Toulouse, INSA, 2011. http://www.theses.fr/2011ISAT0033/document.
Анотація:
Avec la tendance continue vers la technologie nanométrique et l'augmentation des fonctions complexes intègres dans les électroniques systèmes embarqués, Assurant la compatibilité électromagnétique (CEM) des systèmes électroniques est un grand défi. CEM est devenu une cause majeure de redesign des Circuits intègres (CI). D’ailleurs, les performances des circuits pourraient être affectés par les mécanismes de dégradation tels que hot carrier injection (HCI), negative bias temperature instability (NBTI), gate oxide breakdown, qui sont accélérés par les conditions d'exploitation extrême (haute / basse température, surcharge électrique, le rayonnement). Ce vieillissement naturel peut donc affecter les performances CEM des circuits intégrés.Les travaux développés dans notre laboratoire vise à clarifier le lien entre les dégradations induites par le vieillissement et les dérives CEM, de développer les modèles de prédiction et de proposer des "insensibles au cours du temps" structures pour CEM protection, afin de fournir des méthodes et des guidelines aux concepteurs d'équipements et CI pour garantir la CEM au cours de durée de vie de leurs applications. Ce sujet de recherche est encore sous-exploré en tant que communautés de recherche sur la «fiabilité IC» et «compatibilité électromagnétique IC» n’a souvent pas de chevauchement.Ce manuscrit de thèse introduit une méthode pour quantifier l'effet du vieillissement sur les CEM des circuits intégrés par la mesure et la simulation. Le premier chapitre donne un aperçu du contexte général et le deuxième chapitre est dédié a l’état de l'art de CEM des circuits intégrés et de problèmes de fiabilité IC. Les résultats expérimentaux de circuits CEM évolution sont présentés dans le troisième chapitre. Ensuite, le quatrième chapitre est consacré à la caractérisation et la modélisation des mécanismes de dégradation du CI. Un EMR modèle qui inclut l'élément le vieillissement pour prédire la dérive du niveau CEM de notre puce de test après stress est proposéWith the continuous trend towards nanoscale technology and increased integration of complex electronic functions in embedded systems, ensuring the electromagnetic compatibility (EMC) of electronic systems is a great challenge. EMC has become a major cause of IC redesign. Meanwhile, ICs performance could be affected by the degradation mechanisms such as hot carrier injection (HCI), negative bias temperature instability(NBTI), gate oxide breakdown, which are accelerated by the harsh operation conditions (high/low temperature, electrical overstress, radiation). This natural aging can thus affect EMC performances of ICs. The work developed in our laboratory aims at clarifying the link between ageing induced IC degradations and related EMC drifts, developing prediction models and proposing “time insensitive” EMC protection structures, in order to provide methods and guidelines to IC and equipment designers to ensure EMC during lifetime of their applications. This research topic is still under-explored as research communities on “IC reliability” and “IC electromagnetic compatibility” has often no overlap. The PhD manuscript introduced a methodology to quantify the effect of ageing on EMC of ICs by measurement and simulation. The first chapter gives an overview of the general context and the second chapter states the EMC of ICs state of the art and IC reliability issues. The experimental results of ICs EMC evolution are presented in the third chapter. Then, the fourth chapter is dedicated to the characterization and modeling IC degradation mechanism. An EMR model which includes the ageing element to predict our test chip’s EMC level drift after stress is proposed
4
Bertolini, Clément. "Estimation à haut-niveau des dégradations temporelles dans les processeurs : méthodologie et mise en oeuvre logicielle." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2013. http://tel.archives-ouvertes.fr/tel-00952867.
Анотація:
Actuellement, les circuits numériques nécessitent d'être de plus en plus performants. Aussi, les produits doivent être conçus le plus rapidement possible afin de gagner les précieuses parts de marché. Les méthodes rapides de conception et l'utilisation de MPSoC ont permis de satisfaire à ces exigences, mais sans tenir compte précisément de l'impact du vieillissement des circuits sur la conception. Or les MPSoC utilisent les technologies de fabrication les plus récentes et sont de plus en plus soumis aux défaillances matérielles. De nos jours, les principaux mécanismes de défaillance observés dans les transistors des MPSoC sont le HCI et le NBTI. Des marges sont alors ajoutées pour que le circuit soit fonctionnel pendant son utilisation, en considérant le cas le plus défavorable pour chaque mécanisme. Ces marges deviennent de plus en plus importantes et diminuent les performances attendues. C'est pourquoi les futures méthodes de conception nécessitent de tenir compte des dégradations matérielles en fonction de l'utilisation du circuit. Dans cette thèse, nous proposons une méthode originale pour simuler le vieillissement des MPSoC à haut niveau d'abstraction. Cette méthode s'applique lors de la conception du système c.-à-d. entre l'étape de définition des spécifications et la mise en production. Un modèle empirique permet d'estimer les dégradations temporelles en fin de vie d'un circuit. Un exemple d'application est donné pour un processeur embarqué et les résultats pour un ensemble d'applications sont reportés. La solution proposée permet d'explorer différentes configurations d'une architecture MPSoC pour comparer le vieillissement. Aussi, l'application la plus sévère pour le vieillissement peut être identifiée.
5
Chen, Chang-Chih. "System-level modeling and reliability analysis of microprocessor systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53033.
Анотація:
Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.
6
Lakhdari, Hacène. "Etude par technique spectroscopique de capacite transitoire des defauts a l'interface semiconducteur-isolant." Paris 6, 1988. http://www.theses.fr/1988PA066341.
Анотація:
Explication du comportement inhabituel de certaines structures mos en dlts (non-saturation du spectre dlts pour un remplissage total de la densite d'etats d'interface) par une interaction par effet tunnel entre les porteurs libres du semiconducteur et les defauts des premieres couches d'oxyde (etats lents). Etude de la degradation des interfaces si-sio::(2) sous injection d'electrons chauds en comparant la cinetique de creation des etats lents et rapides. Etude des defauts induits par plasma ionique reactif
7
Tseng, Shun-Shing, and 曾順星. "ILFD Using Dual Injection MOSFETs and Hot-Carrier Effects." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/5tk2a9.
Анотація:
碩士國立臺灣科技大學
電子工程系
102
First, A wide operation range parallel resonant divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷3 ILFD circuit is realized with a parallel resonant cross-coupled n-core MOS LC-tank oscillator. A tunable MOSFET resistor is used to tune the oscillation frequency and widens the operation range. Two direct-injection MOSFETs in series are used as a frequency doubler and a dynamic linear mixer to widen the locking range. The core power consumption of the ILFD core is 4.896 mW. At the incident power of 0 dBm, and the supply voltage of 0.8V, the maximum locking range is 1.6 GHz, from 10.6 GHz to 12.2 GHz and the operation range percentage of 47.6%, from 5 GHz to 13 GHz Secondly, we A wide locking and operation range parallel resonant divide-by-2/4 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷4/2 ILFD circuit is realized with a parallel resonant cross-coupled n-core MOS LC-tank oscillator. The ILFD uses a tunable resonator to have both wide operation and wide locking range. At the supply voltage of 0.92V, the core power consumption of the ILFD core is 7.9 mW. At the incident power of 0 dBm, the divide-by-2 locking range is 6 GHz, from 4.9 GHz to 10.9 GHz and the divide-by-4 locking range is 1.8 GHz, from 10.4 GHz to 12.2 GHz. The ILFD resonator can operates as a dual-resonance resonator or a single-resonance resonator. Finally, we investigates hot carrier (HC) effect on the RF characteristics of a wide-locking range divide-by-4 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm CMOS process. High supply voltage stresses were applied at room temperature on the ILFD. The main observed degradation is a decrease in power consumption due to channel mobility degradation. It was also found that the phase noises in both the free-running and locked state increase with stress time. The locking range of ILFD decreases with stress time and the optimized bias of injection transistor for the largest locking range shifts versus stress time.
8
Lin, Fa-Bo, and 林法伯. "Design of Injection Locked Frequency Divider and Hot Carrier Effects of Injection Locked Frequency Divider." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/50431791342256963033.
Анотація:
碩士國立臺灣科技大學
電子工程系
102
This thesis presents two Injection Locked Frequency Dividers (ILFDs). First one is a wide-locking range Injection Locked Frequency Divider by 2. Second one is a wide-locking range Injection Locked Frequency Divider by 4. Finally, we present two Injection locked frequency divider’s hot-carrier effects experiment. The above circuits are fabricated in the TSMC 0.18 μm CMOS process and 0.18um SiGe process. Firstly, we present a novel wide locking range divide-by-2 injection-locked frequency divider (ILFD) and the divider is implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD is based on a cross-coupled voltage-controlled oscillator (VCO)consist of a parallel-tuned LC resonator as well as injection MOSFETs with source voltage coupled from VCO output and the injection MOSFET is a linear mixer. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 6.4 GHz, from the incident frequency 3.7 GHz to 10.1 GHz, the percentage is 92.75%. A novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in the thesis and was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-4 ILFD is based on a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator and injection MOSFETs with source voltage coupled from VCO output and the injection MOSFET is a linear mixer. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide-by-4 is 2.7 GHz, from the incident frequency 14.1 GHz to 16.8 GHz, the percentage is 17.47%. The core power consumption is 16.56 mW. The die area is 0.839 ×0.566 mm2. Secondly, a divide-by-2 injection-locked frequency divider (ILFD) is designed for hot-carrier stress experimental study. The ILFD is made of a parallel-tuned cross-coupled voltage-controlled oscillator and a capacitive direct-injection MOSFET composite, consisted two MIM capacitors in series with an injection MOSFET. The injection MOSFET is first dc-stressed, and degradation in locking range in the post-stress ILFD was found. Then the whole ILFD is overvoltage-stressed, and degradation in locking range in the post-stress ILFD was also found. The latter stress reduces the current consumption and output power, while the former increases the current consumption and output power. Finally, a divide-by-2 injection-locked frequency divider (ILFD) is designed in the 0.18μm CMOS technology for hot-carrier stress experimental study. The ILFD was tested at two bias conditions. At fixed supply voltage, the stress damage is larger when the gate of injection MOSFET is dc-biased below the supply voltage rather than equal to the supply voltage. The stress cause the degradation of locking range, current consumption and shifts the oscillation frequency.
9
Hsieh, Jen-Hsiang, and 謝仁翔. "Design and Hot Carrier Stress Effect ofNovel Injection-Locked Frequency Divider." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/42871692762723508514.
Анотація:
碩士國立臺灣科技大學
電子工程系
101
In the RF transceiver, PLL characteristics are very important, PLL to including Phase Frequency Detector (PFD),Charge Pump (CP),Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide operating frequency range, Among them, the most important performance of the VCO and Divider. First, this thesis presents two divider-by-3 injection locked frequency dividers. In the first circuit, we use internal feedback to enhance locking frequency, the ILFD was implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process, and the core power consumption is 13.2 mW at the dc drain-source bias of 0.8 V. and tuning range is from 3.079 to 3.163 GHz. At the input power of 0 dBm, the locking range is from 8.9 GHz to 10.8 GHz (19.28 %), the operation range is from 8.9 to 11 GHz(21.1%), and the die area is 0.620 * 0.871 mm2. Secondly, we presents a mixer twice in divider-by-3 injection locked frequency dividers, the ILFD was implemented with the TSMC 0.18 μm 1P6M CMOS process, and the core power consumption is 11.496 mW at the dc drain-source bias of 0.8 V. The tuning range is from 4.32 to 3.78 GHz, At the input power of 0 dBm, the locking range is from 10.5 GHz to 13.5 GHz (25 %), while the operation range is from 9.9 to 13.5 GHz(30.76%), The die area is 0.659 * 0.887 mm2. Then, we measure hot carrier stress effects on the different parameters of these two circuit of circuit architecture, such as phase noise, locking range, current, tuning range, we do analysis and discussion for the measured result. Finally, we presents a Triple-Band Voltage-Controlled Oscillator, the VCO was implemented with the TSMC 0.18 μm 1P6M CMOS process, and the core power consumption is 3.735 mW at the dc drain-source bias of 0.75 V. The VCO can generate differential signals in the frequency range of 6.98-7.41GHz, 5.28-5.31GHz, and 4.27-4.49GHz. The die area is 0.568*1.189 mm2.
10
Yih, Cherng-Ming, and 易成名. "Investigation of Hot-Carrier Injection Induced Reliability Issues in Flash Memories." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/73427801549497138777.
Анотація:
博士國立交通大學
電子工程系
87
Hot carrier induced reliability issues have become increasingly important for miniaturized flash memory design. These reliability issues include hot carrier related issues, such as oxide damage, program/erase cycling endurance, disturbance, and data retention. In this dissertation, the hot-carrier injection induced reliability problems in stacked-gate flash memories is investigated. First, a new model based on the charge-balance theory was proposed to accurately calculate the floating gate voltage. Based on the new model, the method to determine the capacitive coupling coefficients and a compact SPICE model was developed. Then, an oxide damage characterization method was developed for simultaneously determining the lateral distributions of interface states (Nit) and oxide charges (Qox) under both channel-hot-electron programming bias and source FN erase bias stress conditions. According to the extracted profiles of Nit and Qox, a new gate current model was successfully developed for the first time by taking the hot-electron stress generated Nit and Qox into account. In this model, we suggest that Nit filled with electrons will serve as a new scattering center and reduce the hot-electron injection probability. The generated Qox is also introduced as an additional factor affecting the potential barrier at the Si-SiO2 interface. Moreover, the oxide-field dependent stress-induced leakage current (SILC) as well as its related disturbance on the source FN erased flash memory has been studied by using a new approach. The salient features of the method are two fold. One is that the individual contributions of SILC and disturbance due to either carrier charging/discharging in the oxide or positive charge-assisted/trap-assisted tunneling (PCAT/TAT) of electrons into the floating gate can be separated. The other one is that it is very sensitive to determine the ultra-low SILC (< 10-20 A). In this study, we first observed that the generated Nit dominates the gate current degradation not only at the IB,max stress condition but also at the IG,max stress condition. The major programming degradation mechanisms of flash memory cells after P/E cycles due to Nit was also identified. In addition, we also observed that the carrier charging/discharging in the oxide is the main disturb mechanism at low oxide field. At high oxide field, PCAT/TAT of electrons into the floating gate is the major cause for the disturb failure.
11
Patel, Bhawar S. "Study of MOSFET degradation under substrate injection and hot carrier degradation." Thesis, 2003. http://library1.njit.edu/etd/fromwebvoyage.cfm?id=njit-etd2003-099.
12
Wu, Zhi-hong, and 吳志宏. "Hot-Carrier Effects and Design of Dual Band Injection-Locked Frequency Divider." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/55129453767380994537.
Анотація:
碩士國立臺灣科技大學
電子工程系
101
In wireless communication system, frequency synthesizers are used to implement the frequency up/down conversion of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal caused by close interfering tones. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption. First, this thesis presents a dual-band CMOS injection locked frequency divider, using the TSMC 0.18um 1P6M CMOS process. Measurement results show that at the supply voltage of 0.8 V, the core power consumption is 9.5mW. The free-running frequencies are from 3.571 to 3.974 GHz for the higher-frequency band and the free-running frequencies are from 2.278 to 2.349 GHz for the lower-frequency band. An external injected signal power of 0 dBm provides a low-band divide-by-2 locking range (57.7％) from 2.87 to 5.2GHz and a high-band divide-by-2 locking range (25.7％) from 7.1~9.2GHz. The divide-by-4 operation range is from 13.88 to 15.94GHz. The die area is 0.996 × 0.868 mm2. Secondly, we present the hot carrier effect on a dual-resonance injection-locked frequency divider. The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process and it was stressed at the supply voltage of 2.3V for 5 hours. It is shown that both the high-frequency and low-frequency band locking range decrease as the stress time increases. The measured data shows that the narrow locking range likely leads to circuit failure as RF stress enhances. Finally, presents a dual-band VCO using varactor-swiching mode, using the TSMC 0.18um SiGe BiCMOS process. Measurement results show that at the supply voltage of 0.6 V, the core power consumption is 4.68 mW. The free-running frequencies are from 5.46 to 5.68 GHz for the higher-frequency band and the free-running frequencies are from 2.73 to 3.44 GHz for the lower-frequency band. The figure of merit is -188.4/-186.6 dBc/Hz at high/low band at 1MHz offset frequency. The die area of the dual-band VCO is 1 × 0.861 mm2.
13
Magsarsuren, Luvsanperenlei, and Luvsanperenlei Magsarsuren. "Reliability test of high voltage SOI device under Hot carrier injection stress." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/60749395705720697161.
Анотація:
碩士亞洲大學
資訊工程學系碩士班
100
The Hot-carrier-induced on-resistance degradations of Locos PLDMOS and Tapered PLDMOS transistors are investigated in detail by MEDICI, a TCAD simulation and charge pumping test. For different stress conditions, degradation behaviors of PLDMOS transistors are analyzed and degradation mechanisms are presented. Then the effect of On and Off-state Breakdown voltage, IdVg and Ron degradations are investigated. Also HCI degradation result of PLDMOS transistors are compared with NLDMOS transistors results.
14
Tsai, Shih-wei, and 蔡世偉. "Study of Oxide and Interface Traps in Ultra-Thin Nitrided Oxide MOSFET Using Hot-Carrier Injection from a Buried Junction Injector." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/71789977958480601811.
15
"Surface Potential Modelling of Hot Carrier Degradation in CMOS Technology." Master's thesis, 2017. http://hdl.handle.net/2286/R.I.44270.
Анотація:
abstract: The scaling of transistors has numerous advantages such as increased memory density, less power consumption and better performance; but on the other hand, they also give rise to many reliability issues. One of the major reliability issue is the hot carrier injection and the effect it has on device degradation over time which causes serious circuit malfunctions.
Hot carrier injection has been studied from early 1980's and a lot of research has been done on the various hot carrier injection mechanisms and how the devices get damaged due to this effect. However, most of the existing hot carrier degradation models do not consider the physics involved in the degradation process and they just calculate the change in threshold voltage for different stress voltages and time. Based on this, an analytical expression is formulated that predicts the device lifetime.
This thesis starts by discussing various hot carrier injection mechanisms and the effects it has on the device. Studies have shown charges getting trapped in gate oxide and interface trap generation are two mechanisms for device degradation. How various device parameters get affected due to these traps is discussed here. The physics based models such as lucky hot electron model and substrate current model are presented and gives an idea how the gate current and substrate current can be related to hot carrier injection and density of traps created.
Devices are stressed under various voltages and from the experimental data obtained, the density of trapped charges and interface traps are calculated using mid-gap technique. In this thesis, a simple analytical model based on substrate current is used to calculate the density of trapped charges in oxide and interface traps generated and it is a function of stress voltage and stress time. The model is verified against the data and the TCAD simulations. Finally, the analytical model is incorporated in a Verilog-A model and based on the surface potential method, the threshold voltage shift due to hot carrier stress is calculated.Dissertation/Thesis
Masters Thesis Electrical Engineering 2017
16
Chuang, Chun-yu, and 莊淳郁. "Hot carrier effect and design of Wide Locking Range Series-Tuned Injection-Locked Frequency Divider." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/76072270271897129945.
Анотація:
碩士國立臺灣科技大學
電子工程系
101
First, A new wide locking range series-tuned divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷3 ILFD circuit is realized with a series-tuned cross-coupled n-core MOS LC-tank oscillator. Two direct-injection MOSFETs in series are used as a frequency doubler and a dynamic linear mixer to widen the locking range. The core power consumption of the ILFD core is 10.56 mW. The divider’s free-running frequency is tunable from 3.529 GHz to 3.828 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm the maximum locking range is 2.3 GHz (21.6%), from the incident frequency 9.5 GHz to 11.8 GHz. The operation range is 2.5GHz (23.7%), from 9.3GHz to 11.8 GHz. Second, investigates the hot carrier effects on the RF characteristics of a series-tuned divide-by-3 injection-locked frequency divider (ILFD). The ÷3 ILFD was implemented in the TSMC 0.18 μm CMOS process. High supply voltage was applied to excite high RF voltage stress on the ILFD. ILFD-core current and power consumptions decrease with stress time, this was attributed to the transconductance degradation of cross-coupled n-core MOS. The locking range degradation is caused by the transconductance degradation of injection MOSFETs and low ILFD voltage swing. Finally, introduce the Hot carrier (HC) effect on a divide-by-2/-4 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses one direct injection MOSFETs for coupling external signal to the LC resonator. It is shown that the divide-by-2/-4 locking range decreases and the oscillation frequency increases with stress time, and the phase noise in both the free-running and locked state increases with stress time.
17
Huang, Zhi Mu, and 黃智睦. "Physics, simulation and characterization of hot carrier injection induced reliability issues in submicron MOSFET''s." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/49237064299497257041.
18
Shih-Chen, Wang, and 王世辰. "Investigation on a New Embedded Flash Memory Cell Using a SPICE-compatible Hot Carrier Injection Model." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/71112768521637791024.
Анотація:
碩士國立清華大學
電子工程研究所
91
A new embedded-flash-memory cell consisting of two transistors fabricated by a standard CMOS process has been proposed by our lab. The cell is verified with good program and erase characteristics, but further investigation are not completed yet. Owing to the full compatibility with the standard CMOS process, such investigations can be fulfilled by SPICE simulations. Though accurate device characteristics is already obtained by the BSIM device model, but the lack of a sub-circuit model of the gate current injection mechanisms prohibits further studies of the cell behavior. Hence, a simulation tool compatible with SPICE is built up for cell structure optimization. There are two major aims in this study. One is the built-up of the circuit element of hot-carrier injection and a sub-circuit model to simulate the proposed cell. Fairly good agreements between simulation results and the measurement data are obtained with our sub-circuit model. The second aim of this study is to investigate the effect of various cell parameters on the cell behavior. Three kinds of design parameters — cell dimensions, operating voltages, and process variations — are discussed in this work. The influences of design parameters are verified with physical intuitions, hand calculation and simulation results. Through such discussions, the design direction of the novel cell is revealed. Those conclusions therefore can help further improvement of the array structure and new program / erase schemes to obtain better cell performance.
19
LIN, WEI-DE, and 林煒得. "The Device Performance and Reliability of Hot Carrier Injection of multi-fin with Different Work Functions." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/g6ppmc.
Анотація:
碩士國立高雄大學
電機工程學系碩博士班
107
Hence, It also increases the saturation current and decreases the threshold voltage. Under the hot carrier injection, because the metal work functions increase, the more influence of metal ions on the interface layer, the greater the probability of interface defects. Therefore, the reliability degradation is more significant. It is also discussed the impact of single and multi-fin structure in FinFET. Channel coupling effect leads to decline of the saturation current, but the fin bending (Contact Etch Stop Layer, CESL) causes the saturation current to rise. Therefore, there is a complicated phenomenon on the saturation current. However, under the hot carrier injection, the multi-fin had more reliability degradation than the single fin.
20
Fu, Cong-chao, and 傅從超. "Hot-Carrier Effect and Design of LC Divide-by-4 Injection-Locked Frequency Divider Using Two Linear Mixers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/11645794971741191388.
Анотація:
碩士國立臺灣科技大學
電子工程系
101
First, the thesis presents a novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator and an active-passive composite to serve as an injection device with the function of nonlinear mixer. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm the operation range of the divide-by-4 is 2.2 GHz, from the incident frequency 10.5 GHz to 12.7 GHz, the percentage is 18.96%. The locking range of the divide-by-4 is 1.6 GHz, from the incident frequency from 10.6 GHz to 12.2 GHz, the percentage is 14.035%. The core power consumption is 10.6 mW. The die area is 0.492×0.819 mm2. Secondly, we discuss the effect of ac hot-carrier stress on the performance of a wide locking range divide-by-4 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the resonators. It is shown that the locking range, operation range decrease with stress time. after RF stress at an elevated supply voltage for 5 hours have been examined by experiment. The measured locking range after RF stress shows significant degradation from the fresh circuit condition. Impact of hot carrier effect on the ILFD’s locking range is discussed. Finally, we investigates hot carrier (HC) effect on a divide-by-2 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the series-resonant resonator. It is shown that the locking range decreases and the oscillation frequency with stress time, and the phase noise in both the free-running and locked state increases with stress time. The measured operation range after RF stress also shows degradation from the fresh circuit condition.
21
Wang, Chia-Chun, and 王嘉俊. "A Triple-band Divide-by-2 Injection-Locked Frequency Divider Using 6th-Order Resonator And Hot Carrier Effect Research." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/11362872841722513898.
Анотація:
碩士國立臺灣科技大學
電子工程系
103
A triple-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses a cross-coupled nMOS pair and a 6th order LC resonator. At the drain-source bias of 1 V and the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-2 ILFD are 1.6GHz (40％) from 9.9 to 11.5 GHz, 3.1GHz (42.17％) from 5.8 to 8.9 GHz and 1.8GHz (14.95％) from 3.6 to 5.4 GHz respectively .The core power consumption is 21.54 mW. The die area is 1.198×1.155 mm2 A divide-by-2 injection-locked frequency divider (ILFD) is designed for hot-carrier stress experimental study. The ILFD is made of a capacitive cross-coupled voltage-controlled oscillator and capacitive direct-injection MOSFET composite that consist of two MIM capacitors in series with injection MOSFETs. The cross-coupled transistors are respectively dc-stressed, and degraded drain current is found. The degradation due to dc current in locking range of the ILFD was found, This degradation is contributed by MERELY the cross-coupled MOSFETs.
22
Jou, Yung-Cheng, and 周永晟. "High Efficiency Yellow Organic Light-Emitting Diodes with a Balanced Carrier Injection Co-host Structure." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/07951863486572150861.
Анотація:
碩士國立清華大學
材料科學工程學系
100
We demonstrate herein the design and fabrication of a highly efficient yellow organic light-emitting diode (OLED) with a balanced carrier injection device architecture having a zero electron-injection-barrier host blended with a hole-injection aiding co-host. The resultant yellow OLED showed, at 1,000 cd m-2 for example, an efficacy of 59 lm W-1, current efficiency of 71 cd A-1 and external quantum efficiency (EQE) of 23%, while 42 lm W-1, 47 cd A-1 and 15% EQE without co-host. The co-host effect that resulted in a much balanced carrier injection was also valid for other yellow OLED devices and their efficiency improvement was also very marked. With the use of a micro-lens, the device efficiency is further improved to 79 lm W-1, 96 cd A-1 and 30% EQE.
23
Kurniawan, Erry Dwi, and Erry Dwi Kurniawan. "Hot Carrier Injection (HCI) Reliability and Isolation Voltage Calibration of 80V High-Side NLDMOS and Transient Voltage Suppressor (TVS) Diode." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/fc38ww.
Анотація:
碩士亞洲大學
資訊工程學系
102
In this recent year, there has been a growing research interest in the area of power devices for various electronic applications, such as power management IC, ESD protection, switching devices, and Radio Frequency (RF) base station application. Lateral Diffused Metal Oxide Semiconductor (LDMOS) is the dominant device technology used in high power amplifiers and high voltage application. Power diode such as Transient Voltage Suppressor (TVS) diode also important for protecting sensitive semiconductors from damaging effects of transient voltages. This thesis consists of two parts: 80V High-side NLDMOS and Transient Voltage Suppressor (TVS) Diode. In part 1, Hot Carrier Injection (HCI) for reliability design and optimization of 80V High-side NLDMOS using n-drift region linear doping profile was discussed. The HCI simulation results can meet the specification and lifetime requirement. There are three important parameters for designing and optimizing High-side NLDMOS: breakdown voltage, on-resistance, and isolation voltage. In previous simulation, the isolation voltage can not match with experimental data. Using MonteCarlo implantation model, we found that our design with TCAD simulation software can be closely calibrated with experimental data in this thesis. In the part 2, Transient Voltage Suppressor (TVS) diode was designed and optimized. Three different structures of TVS were investigated. By adjusting the parameter using simulation tool, we can predict and analyze the behavior and electrical characteristic of the device to meet the specification target and give the trend curve of the devices.
24
Chang, Chou-Ming, and 張洲銘. "Divide-by-2 Injection-Locked Frequency Divider Implemented with Two Shunt 4th-Order Resonators and Hot-carrier Stress Effect on Divide-by-4 Class-C Injection-Locked Frequency Divider." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/09096740876831140108.
Анотація:
碩士國立臺灣科技大學
電子工程系
103
A three-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD using a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. Measured data has shown the ILFD has three locking ranges at fixed bias condition or by varactor bias switching.
25
Cheng, Cheng-Yin, and 鄭程尹. "Performance improvement of white phosphorescent organic light-emitting diodes by using composite host structure to enhance the carrier injection." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/s759an.
Анотація:
碩士國立虎尾科技大學
光電與材料科技研究所
98
The device characteristics of blue phosphorescent organic light-emitting diodes (PHOLEDs) with hole-buffer structure were investigated by inserting the hole transport-type host (TCTA) between hole transport layer (HTL) and emitting layer (EML). The hole transport-type host has lower hole mobility (μh~1.6×10-4 cm2/Vs) than HTL material, which could be effectively controlled the hole injection current from HTL to EML. Moreover, the highest occupied molecular orbital (HOMO) level of buffer layer material was between HTL and EML, lead to the reduced of hole injection barrier. The distributed recombination zone and balanced charge carrier injection within emissive layer were achieved through the thickness of buffer layer optimization, therefore the device performances were greatly enhanced. In addition, an bipolar transport-type host material (26DCzPPy) and a high triplet energy electron transport material (3TPYMB) with low-lying lowest unoccupied molecular orbital (LUMO) were used to reduce the driving voltage and effective confined the triplet excitons within emissive layer, which resulted in power efficiency effectively improved. At luminance 1000 cd/m2, the driving voltage decreased to 5.1 V , the yield of 23 cd/A and the power efficiency of 13.5 lm/W was achieved. Next, the highly efficiency white PHOLEDs were investigated by doping the orange-red dopant (Os(bpftz)2(PPh2Me)2) into the right-side of blue-EML(exciton generation zone),As the result, the white PHOLED exhibits a yield of 27 cd/A. and power efficiency of 15.5 lm/W at a luminance of 1000 cd/m2.The white device with a maximum yield of 27.8 cd/A, a power efficiency of 17.7 lm/W. and CIE coordinate of (0.33, 0.32) without color-shift can be achieved. Next, the device characteristics of blue PHOLEDs with composite host structure were investigated by co-doping the hole and electron transport-type host materials with an bipolar host (26DCzPPy).From the results, the performances of OLEDs were improved greatly due to the improved charge carrier injection and confined exciton into recombination zone of composite host structure. Moreover, a high efficiency white OLED was also fabricated by doping Os into bule emitting layer. The white OLED shows the efficiencies of 34.5 cd/A and 24 lm/W at a luminance of 1000 cd/m2. Furthermore, the efficiencies can be increased to 42.5 cd/A and 30 lm/W by attaching an outcoupling brightness enhancement film(BEF) onto substrate.
26
Deivasigamani, Ravi, and Ravi Deivasigamani. "An Innovated Design of 60-120V Sided-Isolation NLDMOS with Bench marked Ron for 0.35um CMOS Compatible Process and Hot Carrier Injection (HCI) Reliability Study." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/51018492231273986375.
Анотація:
碩士亞洲大學
資訊工程學系
105
Sided-Isolation NLDMOS: In intelligent power IC’s, it is very important to get a high breakdown with lowest possible specific on-resistance (Rsp) so as to keep heat dissipation as low as possible and thereby enhancing efficiency and reliability. The conventional LDMOS structure still produces high Rsp due to the drift length limit. The newly invented device structure using a very short drift length with Sided-Isolation can deliver the world benchmark Rsp performance, hence the device can have high efficiency and good reliability performance. So in our new innovated design we invented a good idea that the use of Sided-Isolation technique and it will help to keep Rsp very low keeping breakdown still good. N-blanket implantation help to get the low NPN beta and this intern helps to get better On-State IV performance that is enhanced on-state breakdown as one of the SOA parameters. Added PBL implantation beneath the P-body area helps to get rid of Kirk effect problem in on-state family curves. So by using these new innovative techniques we can have optimized the device and we have achieved higher breakdown voltage and world benchmarked Ron. The main difficult to get NPN beta less than 1 so that we can able to achieve good On-state performance with best Rsp also. This Sided-Isolation technique helped us to achieve benchmark Rsp performance without compromising the Off-sate breakdown. Hence, with all these performances this device becomes a good solution for smart power applications. The proposed multiple RESURF LDMOS is able to achieve a benchmark specific on-resistance while maintaining a breakdown voltage and additionally to achieve better ESOA performance. The key feature of this novel device is linear p-top rings which are located on the surface of n-drift region. Optimization of p-top mask design and n-drift region is performed in order to achieve benchmark on-resistance with the desired breakdown voltage. Hot Carrier Injection (HCI) Reliability Test: In long time reliability test of the device, the Hot Carriers those gains extra kinetic energy will trap into the silicon/silicon-di-oxide interface and cause Rsp and Idsat degradation. This mechanism we simulated and tested by using TCAD Sentaurus tool. We used appropriate models to simulate phenomena of charge trapping and degradations that take place in real silicon processes Hot Carrier Injection (HCI) is a mechanism that can generate an interface trap in the Si/SiO2 interface of the MOSFET device. The Generated interface trap will shift the device parameter and degrade its performance.As the device experience high electric field, carrier either electron for NMOSFET or hole for PMOSFET gain high kinetic energy so called hot carrier. This hot carrier will degrade on-resistance and saturation drain current of the device.Hot carrier injection degradation seems to be more significant on NMOSFET because the electron has a lower effective mass compare to hole so that it can gain more kinetic energy from the channel electric field. We perform HCI reliability test for 60V Sided-Isolation NLDMOS device we have measured Id current degradation @vg=5v, Vd=0.1v and Idsat degradation @Vdd=40V and Vg=5v and stress for time 1e3, 1e4, 1e5,1e6,6.93e6 seconds and measure corresponding Idsat and Rsp . Hence we can then know and calculate percentage Rsp and Idsat shift. This shift is due to Hot carriers that trapped into the Si/Sio2 interface region The New Innovated Sided isolation NLDMOS device design has poor HCI performance when we use STI Isolation.The STI isolation is generally used instead of LOCOS isolation due to the device size consideration. The STI can save the space and deliver the same isolation, but in less space. In our study of newly developed side-isolation LDMOS device structure, we have found the STI has a poor performance in the HCI life time test. STI may cause HCI issues due to high field at trench edges. We have found that after 1e4 seconds stress time Idsat Degradation is 15%. However, this new Sided-Isolation device has demonstrated with LOCOS can not only a better HCI improvement which can implement LOCOS by keeping the same drift region, and device size.We have found that after 6.93e6 seconds (0.22Years) stress time Idsat Degradation is only 0.47%. We plot and show the trap charges distribution along the interfaces and these trap charges are more with more stress
27
Chandrashekhar and 錢得如. "A New Innovated Design of 40-100V Sided-Isolation NLDMOS with Low Ron for CMOS-compatible(<0.5 micron) Process and Hot Carrier Injection (HCI) Reliability Test." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/63953481290108129896.
Анотація:
碩士亞洲大學
資訊工程學系
104
Sided-Isolation NLDMOS: In intelligent power IC’s, it is very important to get high breakdown with lowest possible specific on-resistance (Rsp) so as to keep heat dissipation as low as possible and thereby enhancing efficiency and reliability. The conventional LDMOS structure still produce high Rsp due to the drift length limit. The newly invented device structure using very short drift length with Sided-Isolation can deliver the world benchmark Rsp performance hence the device can have high efficiency and good reliability performance. So in our new innovated design we invented a good idea that use of Sided-Isolation technique and it will help to keep Rsp very low keeping breakdown still good. In addition added PBL and N-blanket implantation help to have good breakdown, safe operating area(SOA) and sensitivity. N-blanket implantation help to get low NPN beta and this intern help to get better on-state IV performance that is enhanced on-state breakdown as one of the SOA parameter. Added PBL implantation beneath the P-body area helps to get rid of Kirk effect problem in on-state family curves. So by using these techniques we can have optimized best results. The main difficult to get NPN beta less than 1 so that we can able to achieve good On-state performance with best Rsp also. This Sided-Isolation technique helped us to achieve benchmark Rsp performance without compromising the Off-sate breakdown. Hence with all these performance this device become a good solution for smart power applications. Hot Carrier Injection (HCI) Reliability Test: In long time reliability test of the device, the Hot Carriers those gain extra kinetic energy will trapped into the silicon/silicon-di-oxide interface and cause Rsp and Idsat degradation. This mechanism we simulated and tested by using TCAD Sentaurus tool. We used appropriate models to simulate phenomena of charge trapping and degradations that take place in real silicon processes. Electrons that gain high kinetic energy due to applied high electric field will trap into field-oxide region (drift-region) hence Id current will degrade so Rsp and Idsat degrade and Holes gain high kinetic energy will be trap into gate-oxide region causing threshold shift (Vth-shift). We perform HCI reliability test for 40V Sided-Isolation NLDMOS device and measure Id current degradation @vg=5v, Vd=0.1v and Idsat degradation @Vdd=40V and Vg=5v and stress for time 1e3, 1e4, 1e5 seconds and measure corresponding Idsat and Rsp . Hence we can then know and calculate percentage Rsp and Idsat shift. This shift is due to Hot carriers that trapped into Si/Sio2 interface region. We plot and show the trap charges distribution along the interfaces and these trap charges are more with more stress.