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Relevant bibliographies by topics / 32 Bit CSLA

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Academic literature on the topic '32 Bit CSLA'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "32 Bit CSLA"

1

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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2

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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3

Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (2018): 369. http://dx.doi.org/10.3390/electronics7120369.

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Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing bi

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Yogayata, Shrivastava, Verma Tarun, and Jain Rita. "Design and Implementation of Low Power High Speed 32-Bit HCSA." International Journal of VLSI and Embedded Systems 5 (April 17, 2014): 893–98. https://doi.org/10.5281/zenodo.33236.

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In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing

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5

Aditya, Srinivas, and Ramesh K.B. "Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder." Journal of Optoelectronics and Communication 6, no. 3 (2024): 18–26. https://doi.org/10.5281/zenodo.12720733.

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<em>Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced

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Kamna, nayak, and Patra K.Pitambar. "Study of High Speed 32-Bit Data Processing Using CSLA." Association for International Journal in Computer Science & Electronics 4, no. 3 (2015): 1–9. https://doi.org/10.5281/zenodo.33244.

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Modern applications demand extremely low power and fast speed in computer architectures for battery-operated devices like Laptop and others. In this work, the main focus is on the low power consumption and provides high speed to the processors. Low-power and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The selection behind the carry select adder is that it is very much efficient in terms of delay. The main focus in this work is to improve the speed of the 32-bit processor and in this case

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7

PinnikaVenkateswarlu and Kalpana Ragutla. "An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic." SSRG International Journal of Electronics and Communication Engineering 1, no. 8 (2014): 36–41. https://doi.org/10.5281/zenodo.33082.

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As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as wel

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8

Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic." Iraqi Journal for Electrical and Electronic Engineering 21, no. 2 (2025): 88–98. https://doi.org/10.37917/ijeee.21.2.9.

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Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode

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9

Malti, Aryanan, and Singh Chauhan Jaikaran. "Design Area-Efficient and high speed 32bit CSLA." International Journal of advancement in electronics and computer engineering 4, no. 8 (2015): 555–59. https://doi.org/10.5281/zenodo.45401.

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Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

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10

Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based o

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Conference papers on the topic "32 Bit CSLA"

1

Charulata, Saurabh Kharwar, and Sangeeta Singh. "Design & Comparison of 32-bit CSLA with Hybrid Logic." In 2021 International Conference on Simulation, Automation & Smart Manufacturing (SASM). IEEE, 2021. http://dx.doi.org/10.1109/sasm51857.2021.9841179.

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Amizhdhu, G. Thamizh, and P. Samundiswary. "Comparative analysis of 32-bit CSLA based on CMOS and GDI logic." In 2018 4th International Conference on Electrical Energy Systems (ICEES). IEEE, 2018. http://dx.doi.org/10.1109/icees.2018.8442407.

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Vijayalakshmi, V., R. Seshadri, and S. Ramakrishnan. "Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA." In 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT). IEEE, 2013. http://dx.doi.org/10.1109/icevent.2013.6496579.

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Afreen, N. Fahmina, M. Mahaboob Basha, and S. Mohan Das. "Design and implementation of area-delay-power efficient CSLA based 32-bit array multiplier." In 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2017. http://dx.doi.org/10.1109/rteict.2017.8256864.

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Bharadwaj, Abhi A., Manu K, Dhanush Upadhya R, Prabhavathi P, Lakshmi Bhaskar, and Daksh Pankaj Patel. "Implementation of a 32-bit MAC unit in AISC flow using Vedic Multiplier and CSA." In 2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE). IEEE, 2024. http://dx.doi.org/10.1109/iitcee59897.2024.10467383.

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