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Journal articles on the topic 'Area and delay efficient'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

S A Marimuthu, Sudha. "Design of Area-Delay-Power Efficient Adaptive Filter using Wallace Tree Multiplier." International Journal of Scientific Engineering and Research 2, no. 4 (2014): 121–25. https://doi.org/10.70729/j2013241.

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Mohanty, Basant Kumar, and Sujit Kumar Patel. "Area–Delay–Power Efficient Carry-Select Adder." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 6 (2014): 418–22. http://dx.doi.org/10.1109/tcsii.2014.2319695.

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3

J. Pravin adlin, J. Pravin adlin. "An Area and Delay Efficient Csla Architecture." IOSR Journal of Electronics and Communication Engineering 5, no. 3 (2013): 20–25. http://dx.doi.org/10.9790/2834-0532025.

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4

Perri, Stefania, Pasquale Corsonello, and Giuseppe Cocorullo. "Area-Delay Efficient Binary Adders in QCA." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 5 (2014): 1174–79. http://dx.doi.org/10.1109/tvlsi.2013.2261831.

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Saranya, R., B. Paulchamy, K. Kalpana, V. V. Teresa, and P. Logamurthy. "Area-Delay-Power-Efficient GDI Architecture Select Adder to Carry." E3S Web of Conferences 616 (2025): 02005. https://doi.org/10.1051/e3sconf/202561602005.

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The signal processing system is extremely popular in this day and age. All of the primary circuits in the digital signal processing system are built around the adder, which is the fundamental building block. Today’s needs for lowering the delay, space, and power consumption of adder circuits boost the overall efficiency of the system, propelling it to the next stage of technological development. Despite the fact that the Carry Select Adder (CSLA) takes up more space, it is being utilised in place of the ripple carry adder in order to reduce propagation delays. In other models, a Carry Select A

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6

Preetha, S. "Area-Delay Efficient Modified Majority Gate Binary Adders in Quantum-Dot Cellular Automata." International Journal of Scientific Engineering and Research 3, no. 5 (2015): 104–7. https://doi.org/10.70729/ijser15171.

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7

Li, Danqing, Huaguo Liang, Hong Zhang, et al. "BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC." Electronics 12, no. 23 (2023): 4853. http://dx.doi.org/10.3390/electronics12234853.

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Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA) variations, severely impacting circuit performance. Accurate measurement of circuit delay is essential. However, the additional hardware structures for measuring circuit delay add to the critical path delay. To address this issue, this paper proposes a bypass-based ring oscillator (BPath-RO) that reduces the impact on the critical path delay by moving the added measurement control structures to the bypass. The proposed measurement scheme requires only two transistors inserted into the critical path, wh

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Meher, Pramod Kumar, and Sang Yoon Park. "Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 2 (2014): 362–71. http://dx.doi.org/10.1109/tvlsi.2013.2239321.

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9

Li, Shuguo, and Jian Zhang. "Area-delay efficient parallel architecture for Fermat number transform." IEICE Electronics Express 6, no. 8 (2009): 449–55. http://dx.doi.org/10.1587/elex.6.449.

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10

. N. KakatkarD. Bobad, M. e, M. "Implementation on FPGA Area-Delay Efficient Architecture of CSLA." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, no. 06 (2015): 5135–42. http://dx.doi.org/10.15662/ijareeie.2015.0406032.

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11

Jung, Yongchul, Jaechan Cho, Seongjoo Lee, and Yunho Jung. "Area-Efficient Pipelined FFT Processor for Zero-Padded Signals." Electronics 8, no. 12 (2019): 1397. http://dx.doi.org/10.3390/electronics8121397.

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This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designe

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12

R., S. Keote, and Karule P.T. "Area Efficient Fixed Width Multiplier Design for DSP Applications." European Journal of Advances in Engineering and Technology 5, no. 11 (2018): 892–97. https://doi.org/10.5281/zenodo.10727379.

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<strong>ABSTRACT</strong> This paper presents an area efficient fixed width multiplier which receives two n-bit numbers and produces an n-bit product. The presented circuit is based on better error compensation bias to reduce the truncation error. Detailed area analysis, delay analysis, Power Delay product analysis between proposed n-bit fixed width multiplier and standard multiplier has been performed. The presented multiplier has been improved & 17.05% area efficient than the standard multiplier. Also the presented circuit finds application in realizing a digital FIR filter provide fines

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13

Chandrasekhar, Mandalagiri S., Robert H. McCharles, and David E. Wallace. "Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits." VLSI Design 5, no. 2 (1997): 125–40. http://dx.doi.org/10.1155/1997/30941.

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Traditionally logic synthesis and layout tools optimize designs without interaction between them. Lack of communication between the two tools often results in inferior post-layout circuit implementations. This paper presents three aspects of coupling synthesis with layout to minimize post-layout area and delay of circuits. It presents two new techniques for computing net-weights based on timing slacks, and shows how performance improvement with little overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logic equivalence information in circuits to minimize circuit

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14

Saravanakumar, Vijeyakumar, and Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems 7, no. 1 (2018): 43–47. https://doi.org/10.11591/ijres.v7.i1.pp43-47.

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder (CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA.  The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA a

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15

Mohammad, Sameena, and K. Rama Devi. "Design of Area-Power Efficient Parallel Fir Filter with Mux Based Full Adder." International Journal for Research in Applied Science and Engineering Technology 10, no. 9 (2022): 1756–61. http://dx.doi.org/10.22214/ijraset.2022.46913.

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Abstract: In this article, here we propose a new architecture of hardware for a high-speed finite impulse response (FIR) filter using seamless fine-grained pipelining. This proposed parallel full pipeline FIR filter can generate an output sample in a limited gate delays by fixing the pipeline registers in between components and also across the components. A precise critical path analysis at the gate level allows to create a suitable pipelining strategy depending on the throughput. This paper also presents modified full adder, based on multiplexers which establishes trade-offs in terms of area,

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16

Kavitha, V., and S. Mohanraj. "Power Efficient MAC Unit Based Digital PID Controllers." JOURNAL OF ADVANCES IN CHEMISTRY 12, no. 9 (2016): 4324–29. http://dx.doi.org/10.24297/jac.v12i9.4090.

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Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are mad

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17

Agrawal, Priya H., and Prashant R. Rothe. "Implementation of Area, Delay and Power Efficient Carry-Select Adder." IJIREEICE 3, no. 7 (2015): 163–66. http://dx.doi.org/10.17148/ijireeice.2015.3735.

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18

O'Donnell, Anne B., Chris J. Bleakley, and Seamas McGettrick. "Area-delay efficient arithmetic Mixed-Radix Conversion for Fermat moduli." IEICE Electronics Express 8, no. 13 (2011): 1040–46. http://dx.doi.org/10.1587/elex.8.1040.

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19

Ayatollahitafti, V., and M. A. Ngadi. "An Efficient Algorithm with Reduced Delay in Body Area Networks." International Journal of Applied Information Systems 4, no. 4 (2012): 19–23. http://dx.doi.org/10.5120/ijais12-450688.

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20

Patel, Riyaz A., Mohammed Benaissa, Neil Powell, and Said Boussakta. "Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 6 (2007): 1279–92. http://dx.doi.org/10.1109/tcsi.2007.895369.

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21

B., Sakthivel, and Padma A. "Area and delay efficient GDI based accuracy configurable adder design." Microprocessors and Microsystems 73 (March 2020): 102958. http://dx.doi.org/10.1016/j.micpro.2019.102958.

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22

Patel, Sujit Kumar, and Subodh Kumar Singhal. "Area–delay and energy efficient multi‐operand binary tree adder." IET Circuits, Devices & Systems 14, no. 5 (2020): 586–93. http://dx.doi.org/10.1049/iet-cds.2019.0443.

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23

Nalina, R., S. S. Ashwini, and M. Z. Kurian Dr. "Implementation of Unsigned Multiplier Using Area-Delay-Power Efficient Adder." International Journal for Research in Applied Science & Engineering Technology 3, no. 7 (2015): 429–32. https://doi.org/10.5281/zenodo.33100.

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Multiplication and addition are most widely and oftenly used arithmetic computations performed in all digital signal processing applications. Multiplication is the basic arithmetic operation which is present in many part of the digital computer especially in signal processing systems such as graphics and computation system. It requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. This paper deals with the basic multiplier that is shift and add multiplier. Accurate op

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24

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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25

Jay, M. Ventura, Fajardo Arnel, and P. Medina Ruji. "Priority based data transmission for wireless body area network." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3671–77. https://doi.org/10.11591/ijece.v9i5.pp3671-3677.

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Wireless Body Area Sensor Network (WBASN) or Wireless Body Area Network (WBAN) is a growing field in healthcare applications. It enables remote monitoring of patient’s physiological data through wireless communication. It is composed of sensor network which collects physiological data from the patient. There are several issues concerning WBAN such as security, power, routing protocol to address QoS metrics (reliability, end-to-end delay, and energy efficiency), etc. The focus of the study is the issue on different QoS metrics. There were several QoS aware routing protocol that has been p

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26

Iyobhebhe, Matthew, Aliyu D. Usman, A. M. Tekanyi, and Ezekiel Ehimen Agbon. "Hop-Count Aware Wireless Body Area Network for Efficient Data Transmission." Indonesian Journal of Computing, Engineering and Design (IJoCED) 4, no. 1 (2022): 47. http://dx.doi.org/10.35806/ijoced.v4i1.248.

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This work focuses on the clustering in Wireless Body Area Network (WBAN). Recently, it was found that less attention was given to Line-of-Sight (LoS) and Non-Line-of-Sight (NLoS) clustering in WBAN. Past works on LoS clustering WBAN consider the problem of enhancing the network throughput and end-to-end delay of the network. However, the problem of necessary hop count for packet transmission has not been considered. The non-consideration of necessary nodes hop count degrades the performance of cluster-based WBAN as throughput of the network is reduced in addition to high end-to-end delay. This

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27

Swami G, Narayan, Bhuvana D T, Keerthana M R, Ankita B, and Manoja E. "Optimization of Delay and Area for Approximate Radix-8 Booth Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39405.

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This paper investigates the optimization of Radix-8 Booth Multipliers, which are essential for efficient arithmetic operations in modern digital systems, particularly in applications such as digital signal processing, telecommunications, and image processing where rapid and accurate calculations are crucial. The study aims to enhance performance by focusing on reducing both delay and area while ensuring that acceptable accuracy levels are maintained for error-tolerant applications. To achieve these optimization goals, we compare three methodologies: the Carry Save Adder (CSA), the Kogge Stone

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28

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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29

Laxmi, Kumre1 Ajay Somkuwar2 and Ganga Agnihotri3. "POWER EFFICIENT CARRY PROPAGATE ADDER." International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 4, no. 3 (2019): 01–10. https://doi.org/10.5281/zenodo.3364247.

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Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We designed Carry Propagate Adder using GDI technique and compared its performance with CMOS technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and simulated using

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30

Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar, and V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier." Journal of Circuits, Systems and Computers 25, no. 04 (2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.

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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of parti

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31

Saravanakumar, Saravanakumar, Vijeyakumar Vijeyakumar, and Sakthisudhan Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (2018): 43. http://dx.doi.org/10.11591/ijres.v7.i1.pp43-47.

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder ha

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32

E.Kumar, M.Surekha, B.Jagadeesh, P.Venkata Sai Ramakrishna, N.V.S.S Sujith, and B.Manjunadha. "Design and Implementation of Area Efficient 16-bit Carry Skip Adder." international journal of engineering technology and management sciences 7, no. 2 (2023): 339–44. http://dx.doi.org/10.46647/ijetms.2023.v07i02.041.

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Adders are fundamental unit in many computer systems. One of the most efficient adder architectures in terms of delay and area is the carry-skip adder. In this paper an area efficient 16-bit carry-skip adder to achieve high speed and low area were designed. CSA is a rapid adder that is used in data processing systems to execute quick arithmetic operations. As a result, a Modified Carry Skip Adder (MCSA) is developed using a single Ripple Carry Adder (RCA) and a Binary to Excess-1 Converter (BEC) instead of twin RCAs to save size while sacrificing speed. The design is coded in VHDL and its area

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33

Jayakrishna, P., P. Sravani, R. Sakshitha Reddy, and S. Ashritha. "Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 6 (2023): 1353–61. http://dx.doi.org/10.22214/ijraset.2023.53550.

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Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the thre

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Sadaf, Sumaya, and V. Radha Krishna. "Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 667–78. http://dx.doi.org/10.22214/ijraset.2023.56018.

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Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 p

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35

J, Chandrabose. "Area Delay Power Efficient Carry Select Adder for Modern Signal Processors." International Journal for Research in Applied Science and Engineering Technology V, no. IV (2017): 607–10. http://dx.doi.org/10.22214/ijraset.2017.4107.

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36

D, Preethi. "An Area and Power Efficient Glitch-less Digitally Controlled Delay Lines." International Journal of Engineering Trends and Technology 9, no. 14 (2014): 697–704. http://dx.doi.org/10.14445/22315381/ijett-v9p332.

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37

Patel, R. A., M. Benaissa, S. Boussakta, and N. Powell. "Power-delay-area efficient modulo 2n+1 adder architecture for RNS." Electronics Letters 41, no. 5 (2005): 231. http://dx.doi.org/10.1049/el:20056837.

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38

Surya, P., C. Arunachalaperumal, and S. Dhilipkumar. "Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT." Measurement Science Review 25, no. 3 (2025): 134–40. https://doi.org/10.2478/msr-2025-0016.

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Abstract We present a novel parallel and pipelined fast Fourier transform (FFT) architecture for high-speed and low-power applications, a critical component in wireless communications and digital signal processors. The new FFT model implements a data-inverted Vedic multiplier in the FFT architecture, which reduces data switching activity in the input patterns to minimize dynamic power consumption and computational delay. The proposed architecture incorporates a low-power bit inversion (BI) multiplier scheme for a minimum number of complex multiplications with a high-speed partial product gener

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Xue, Pengfei, Yi Shen, Huimin Ma, and Miao Hu. "An Area-Aware Efficient Internet-Wide Port Scan Approach for IoT." Electronics 14, no. 7 (2025): 1267. https://doi.org/10.3390/electronics14071267.

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Internet of Things (IoT) devices usually face some difficulty in supporting complex security protocols or intrusion-prevention mechanisms, due to their limited system resources. As a result, IoT devices are fraught with significant security vulnerabilities and are vulnerable to cyberattacks. Correspondingly, the Internet-wide port scan (IWPS) technique has garnered significant attention for its ability to discover and probe Internet-wide connected IoT devices. However, the existing scanners for IWPSs are often not satisfactory in terms of scan efficiency. Improving the scan rate is an importan

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40

ALNAELI, RAMZI AYAD. "Modeling and simulation Of Campus Area Network (CAN) for The University of Zawia using OPNET." International Science and Technology Journal 36, no. 2 (2025): 1–14. https://doi.org/10.62341/raam2904.

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This research proposes the design and performance evaluation of a Campus Area Network (CAN) for the University of Zawia using OPNET Modeler Academic 14.5. The study focuses on the northern campus, which consists of seven colleges and administrative offices, aiming to enhance academic and administrative communication through efficient network design. The proposed network supports multiple services, including FTP, printing, VoIP, email, database applications, and HTTP under heavy traffic loads. The network performance was evaluated based on key Quality of Service (QoS) metrics, such as delay, th

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41

Ahmed, Rekib U., Sheba D. Thabah, Mridul Haque, and Prabir Saha. "Efficient Modulo Multiplier." Electronics ETF 27, no. 1 (2023): 18–24. http://dx.doi.org/10.53314/els2327018a.

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The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulatio

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42

Azeez, Saba, and Pankaj Rangaree. "FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder." International Journal of Advanced Science Computing and Engineering 3, no. 1 (2021): 10–17. http://dx.doi.org/10.30630/ijasce.3.1.34.

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Three operand binary adder is the basic functional unit to perform the pseudorandom bit generator algorithms and in various cryptography. The basic method used to perform the three-operand binary addition is carry save adder, which leads to high delay. For this a parallel prefix two operand adder such as Han-Carlson adder is used to reduce the delay but increases the hardware architecture i.e., area increases. To overcome this disadvantage, we need a new area efficient and high-speed adder architecture to be proposed using pre compute bitwise addition followed by carry prefix computation logic

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43

Azeez, Saba, and Pankaj Rangaree. "FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder." International Journal of Advanced Science Computing and Engineering 3, no. 1 (2021): 10–17. http://dx.doi.org/10.62527/ijasce.3.1.34.

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Three operand binary adder is the basic functional unit to perform the pseudorandom bit generator algorithms and in various cryptography. The basic method used to perform the three-operand binary addition is carry save adder, which leads to high delay. For this a parallel prefix two operand adder such as Han-Carlson adder is used to reduce the delay but increases the hardware architecture i.e., area increases. To overcome this disadvantage, we need a new area efficient and high-speed adder architecture to be proposed using pre compute bitwise addition followed by carry prefix computation logic

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44

OUERHANI, YOUSRI, MAHER JRIDI, and AYMAN ALFALOU. "AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE." Journal of Circuits, Systems and Computers 21, no. 06 (2012): 1240018. http://dx.doi.org/10.1142/s021812661240018x.

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In this paper we present a novel architecture for FFT implementation on FPGA. The proposed architecture based on radix-4 algorithm presents the advantage of a higher throughput and low area-delay product. In fact, the novelty consists on using a memory sharing and dividing technique along with parallel-in parallel-out Processing Elements (PE). The proposed architecture can perform N-point FFT using only 4/3N delay elements and involves a latency of N/4 cycles. Comparison in terms of hardware complexity and area-delay product with recent works presented in the literature and commercial IPs has

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Sajjan, Akash C., Suyash Gadhave, and Rahul Ratnakumar. "Design of Efficient Multiply-Accumulate Unit for Convolutional Neural Networks." Journal of Physics: Conference Series 2571, no. 1 (2023): 012020. http://dx.doi.org/10.1088/1742-6596/2571/1/012020.

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Abstract Convolutional Neural Networks (CNN) are used in a range of machine learning tasks, such as voice, image, and video processing. As the demand for faster response times in real-time applications grows, the need for high-speed implementation of CNNs is becoming more significant. However, the convolutional layer of CNNs is computationally demanding, leading to higher delays. Therefore, this study seeks to design an efficient and fast convolution block for the hardware implementation of the CNN algorithm. The proposed solution uses a Bit-Level Multiplier and Accumulator (BLMAC) unit that i

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S, Mohan Das, Ganesh Kumar M, and Shireesha G. "Low Power and Area Efficient 4-2 Compressor for Signal Processing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 7 (2020): 8–13. http://dx.doi.org/10.46647/ijetms.2020.v04i07.002.

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In this paper, two performance metrics power and delay are estimated for various XOR-XNOR circuits and Multiplexer for designing 4-2 compressor. The main objective is to design an energy efficient compressor for computing applications in FIR filter. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 4-2 compressors consist of six blocks out of which two XOR-XNOR blocks and four MUX blocks. The average power, delay and energy consumed by the proposed compressor which is based on 5T XOR-XNOR and G

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Al-Sofi, Soleen Jaladet, Salih Mustafa S. Atroshey, and Ismail Amin Ali. "Enhancing sustainable healthcare practices through energy-efficient wireless body area networks." Heritage and Sustainable Development 6, no. 2 (2024): 571–88. http://dx.doi.org/10.37868/hsd.v6i2.687.

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This paper explores how the integration and performance of Wireless Body Area Networks (WBANs) contribute to sustainable healthcare practices. WBANs play a crucial role in reducing the environmental footprint of healthcare systems by providing continuous monitoring that can prevent unnecessary hospitalizations and reduce the consumption of disposable medical supplies. Additionally, the design of WBANs using environmentally friendly materials, low-power devices, and recyclable components is discussed to optimize the sustainability of healthcare practices. To enhance infrastructure, services, an

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TaghipourEivazi, Shiva, Mehdi Hosseinzadeh, and Ahmad HabibizadNovin. "Efficient RNS Converter via Two-Part RNS." Journal of Circuits, Systems and Computers 24, no. 01 (2014): 1550016. http://dx.doi.org/10.1142/s0218126615500164.

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In this paper, a high speed residue to binary converter for three moduli set {2n - 1, 2n + 1, 2n} is presented in this paper, which uses two-part RNS and is based on mixed radix conversion (MRC). By using two-part RNS, the number of modulus in each part decreases; therefore the complexity of reverse converter is reduced. Also, the architecture of the proposed converter is based on subtractors and Multiplexers which are suitable for VLSI implementation. Reducing the number of modulus and simplifying the structure of the proposed converter lead to improvement of the latest presented converter in

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Vinodia, Ayushi. "Energy-Efficient Approximate Multiplier with Flexible Precision." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 741–51. http://dx.doi.org/10.22214/ijraset.2024.61704.

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Abstract: The method that can be utilized to increase accuracy and decrease energy use is approximate multiplication. A key component of many error-tolerant applications is multiplication. Approximate multipliers are increasingly utilized in energyefficient computing for applications tolerant of inaccuracy. Apart from multiplier performance, determining the appropriate approximate multiplier is challenging due to considerations of area and delay. Therefore, selecting the type of approximate full adder (FA) becomes a crucial decision-making factor. These adders are employed for summing partial

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Anuradha, M. G., and R. Arun Kumar. "A Novel and Efficient Left-to-Right Binary Adder Architecture for reduced Area and Power Metrics in VLSI Design." Engineering, Technology & Applied Science Research 15, no. 3 (2025): 22629–35. https://doi.org/10.48084/etasr.9840.

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Fast adders are utilized to cater for computationally intensive operations, and until recently, researchers have focused on optimizing the logic used in carry propagation. In the present study, a new methodology of implementation deploying the left-to-right Vedic addition method is proposed. The proposed methodology and the developed architecture add the number from the Most Significant Bit (MSB), where the carry generation is minimal, and reduce the complexity involved in the binary addition to optimize the area delay and power delay of the binary adder. The proposed left-to-right adder has b

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