Relevant bibliographies by topics / Arithmetic and Logic Unit (ALU)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Arithmetic and Logic Unit (ALU)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Arithmetic and Logic Unit (ALU)"

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Akansha, Singh, and B. Ramesh K. "Arithmetic and Logic Unit." Journal of Advances in Computational Intelligence Theory 5, no. 3 (2023): 1–6. https://doi.org/10.5281/zenodo.8009911.

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<em>This research paper explores the fundamental digital circuit known as the Arithmetic and Logic Unit (ALU). The ALU is an essential component of any central processing unit (CPU) and is responsible for executing arithmetic and logical instructions within a computer&#39;s architecture. The paper examines the ALU&#39;s function in detail, focusing on its ability to process data by executing mathematical and logical operations such as addition, subtraction, multiplication, division, logical AND, OR, NOT, and XOR. The paper also explores analyzing the internal structure and operation of an ALU,
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Yakunin, A. N., Aung Myo San, and Khant Win. "Improving Performance of a Multi-Bit Arithmetic Logic Unit." Proceedings of Universities. Electronics 26, no. 1 (2021): 40–53. http://dx.doi.org/10.24151/1561-5405-2021-26-1-40-53.

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In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with
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Eshan, Kumar Sao, and B. Ramesh K. "Design and Implementation of ALU Chip Using D3l Logic." Journal of Control System and its Recent Developments 5, no. 1 (2022): 1–5. https://doi.org/10.5281/zenodo.6387932.

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<em>Central Processing Unit (CPU) is the heart of Computer, which converts data into information and set of electronic circuitry that executes stored data instructions. Central Processing Unit includes Arithmetic Logic Unit (ALU), Control Unit (CU) and Memory Unit (MU).Arithmetic Logic Unit (ALU) is the integral part of computer processor, that perform arithmetic and logical operations. A Proposed new logic family of low power dynamic logic called Data Driven Dynamic logic (D3L). It is based on 16 Sutras which are discovered by Sri Bharti Krishna. We implement a 64-bit ALU chip design Vedic mu
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Thakral, Shaveta, and Dipali Bansal. "High functionality reversible arithmetic logic unit." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2329. http://dx.doi.org/10.11591/ijece.v10i3.pp2329-2335.

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Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are
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Shaveta, Thakral, and Bansal Dipali. "High functionality reversible arithmetic logic unit." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2329–35. https://doi.org/10.11591/ijece.v10i3.pp2329-2335.

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Energy loss is a big challenge in digital logic design primarily due to impending end of Moore"s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are
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Vikesh, Ukande* Ankit Pandit. "HIGH SPEED LOW POWER 32 BIT ALU IMPLEMENTATION." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 10 (2016): 64–69. https://doi.org/10.5281/zenodo.159286.

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The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 32 bit ALU which accepts two 32 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations are arithmetical, the coding was written in VHDL and verified in I-Sim. The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE.
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Pradnya, Kshirsagar. "ENERGY EFFICIENT IMPROVED 4-Bit ALU DESIGN." International Scientific Journal of Engineering and Management 04, no. 04 (2025): 1–9. https://doi.org/10.55041/isjem02789.

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The 4-bit Arithmetic Logic Unit (ALU) is a fundamental component in digital systems, responsible for executing a range of arithmetic and logic operations on 4-bit binary inputs. This ALU design methodology outlines the construction of a 4-bit ALU capable of per- forming operations such as addition, subtraction, bitwise AND, OR, XOR, and bit-shifting (left and right). The architecture utilizes a 4-bit adder/subtractor for arithmetic operations, implementing two’s complement for subtraction. Logic operations are handled through standard logic gates (AND, OR, XOR), while shifting operations are f
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Liu, Yuguo, Chenyang Zhang, and Haoyi Zhang. "The Mechanism of The Arithmetic Logic Unit." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 97–108. http://dx.doi.org/10.54097/qzqpap16.

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The Arithmetic Logic Unit is widely used in electrical components nowadays such as the CPU in computers. The traditional research is based on the theory of a combination of multiple logic units, the results are not performed intuitional. This paper provides an introduction to the Arithmetic Logic Unit and its mechanisms, which consist of multiple logic gates to perform binary operations and send commands to the computer. The article discusses binary operations using logic gates, starting from the simplest one-bit half-adder to the more complex four-bit ALU, encompassing functions like addition
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Rakshith, Saligram1 Shrihari Shridhar Hegde1 Shashidhar A. Kulkarni1 H.R.Bhagyalakshmi1 and M.K. Venkatesha. "DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC LOGIC UNIT." International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 4, no. 3 (2019): 01–16. https://doi.org/10.5281/zenodo.3342584.

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Reversible Logic is gaining significant consideration as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the outputs. Significant contributions have been made in the literature towards the design of fault tolerant reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is th
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Prahlada, P. Udupa, and B. Ramesh K. "VLSI Design and Verification of a Multi-Function Arithmetic Logic Unit." Journal of VLSI Design and its Advancement 7, no. 3 (2024): 37–47. https://doi.org/10.5281/zenodo.13709349.

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<em>Exploring an ALU Design in the VLSI Domain - Within modern processors like CPUs, FPUs, and GPUs, the Arithmetic Logic Unit (ALU) serves as a critical building block. In this review paper, we delve into the Very Large Scale Integration (VLSI) design of an ALU, exploring its functionality through meticulous simulation and testing. Leveraging the Xilinx ISE design suite 14.7, the study validates the proposed ALU's gate-level and chip-level implementation, ensuring its ability to execute nine essential operations: addition, subtraction, multiplication, shifting, comparison, AND, OR, NOT, and X
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Dissertations / Theses on the topic "Arithmetic and Logic Unit (ALU)"

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Kuprys, Simonas. "ALU SystemC modelių tyrimas ir kūrimas." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2007. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2007~D_20070816_143933-26512.

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Magistro darbe analizuojami aritmetinio loginio įtaiso (ALU) modeliai, operacijos ir architektūros. Išanalizavus mokslinę literatūrą, pasirenkama ALU architektūra bei atliekamų operacijų aibė. Realizuojamas dviejų pakopų sudalintos operacijų aibės ALU modelis. Atlikus apibendrinimą atliekami eksperimentai. Eksperimento modeliai modifikuojami – atliekamas ALU operacijų sudalinimas tarp ALU ir valdančios logikos (CU) operacijų poaibių. Nagrinėjami konkrečių ALU operacijų atlikimo pirmos arba antros pakopos modulyje pranašumai ir trūkumai. Sukurti parametrizuoti (bendriniai) ALU modeliai su kinta
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Bednář, Jaroslav. "Samočinný test ALU za provozu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-237176.

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This work deals with faults, errors and failures, which can occur during manufacturing and long term operation. Work describes the various failures and fault models. There are some approaches to get fault tolerant systems, mainly in hardware. The thesis continues with a summary of methods for ALU software testing. The last chapter is about tests generation for microcontroller MSP430.
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Tang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.

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Tångring, Ivar. "A Design Study of an Arithmetic Unit for Finite Fields." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1799.

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<p>This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. </p><p>Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. </p><p>A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, tha
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Midde, Bharath Reddy. "Design, analysis, and synthesis of 16 bit arithmetic logic unit using reversible logic gate." Thesis, California State University, Long Beach, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10099864.

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<p> In the modern world, an Arithmetic Logic Unit (ALU) is one of the most crucial component of an embedded system and is used in many devices like calculators, cell phones, computers, and so on. An ALU is a multi-functional circuit that conditionally performs one of several possible functions on two operands A and B depending on control inputs. It is nevertheless the main performer of any computing device. This project proposes the design of programmable reversible logic gate structures, targeted for the ALU implementation and their use in the realization of an efficient reversible ALU. This
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Kannan, Balaji Navalpakkam. "The design of an IC half precision floating point Arithmetic Logic Unit." Connect to this title online, 2009. http://etd.lib.clemson.edu/documents/1263396747/.

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Pinkiewicz, T. "Design of a 32-bit Arithmetic Unit based on Composite Arithmetic and its Implementation on a Field Programmable Gate Array." Thesis, Honours thesis, University of Tasmania, 1999. https://eprints.utas.edu.au/584/1/Honours_Thesis.pdf.

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As we advance into the new century, computers of the future will require new techniques for arithmetic operations, which take advantage of the modern technology and yield accurate results. Floating-point arithmetic has been in use for nearly forty years, but is plagued with inaccuracies and limitations which necessitate introduction of a new concept in computer arithmetic, called Composite Arithmetic. Composite Arithmetic combines fixed-point and floating-point arithmetic into one integrated concept where numbers are automatically assigned the right form. This negates the need for diffe
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Ratan, Amrita. "Hardware Modules for Safe Integer and Floating-Point Arithmetic." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

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Osseiran, Adam. "Définition, étude et conception d'un microprocesseur autotestable spécifique : cobra." Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320884.

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Description des différentes étapes de la conception d'un microprocesseur pour le contrôle des automatismes de sécurité, en particulier pour les systèmes de transport. Ce microprocesseur est autotestable, c'est-à-dire capable de détecter ses propres erreurs. La conception du circuit est basée sur les hypothèses de pannes au niveau analytique dans la technologie NMOS. Les blocs fonctionnels «Strongly Fault Secure» et les contrôleurs «Strongly Code Disjoint» sont à la base des circuits «Self-checking», dits autotestables. Le circuit COBRA démontre la faisabilité d'un microprocesseur autotestable.
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Gupte, Ruchir. "Interval arithmetic logic unit for DSP and control applications." 2006. http://www.lib.ncsu.edu/theses/available/etd-05312006-165133/unrestricted/etd.pdf.

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Books on the topic "Arithmetic and Logic Unit (ALU)"

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N, Levitt Karl, Cohen G. C, and Langley Research Center, eds. Toward a formal verification of a floating-point coprocessor and its composition with a central processing unit. National Aeronautics and Space Administration, Langley Research Center, 1991.

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Voltage Scalable High Speed Arithmetic and Logic Unit Architecture for Processor Design. ASDF International, 2017.

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Moezzi, Mahmanzar. An investigation of the influence of field programmable gate array technology on arithmetic logic unit addition techniques. 1995.

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Book chapters on the topic "Arithmetic and Logic Unit (ALU)"

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Vourkas, Ioannis, and Georgios Ch Sirakoulis. "High-Radix Arithmetic-Logic Unit (ALU) Based on Memristors." In Emergence, Complexity and Computation. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-22647-7_6.

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Deshpande, Anagh, and T. Vigneswaran. "Design of Arithmetic and Logic Unit (ALU) Using Subthreshold Adiabatic Logic for Low-Power Application." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_22.

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Jain, Samyakkumar, and Sachin Gajjar. "Design and Implementation of Fault Tolerance and Diagnosis Technique for Arithmetic Logic Unit (ALU) in Soft-Core Processor." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6780-1_10.

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Weik, Martin H. "arithmetic and logic unit." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_817.

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Shiva, Sajjan G. "Arithmetic/Logic Unit Enhancement." In Computer Organization, Design, and Architecture, 6th ed. CRC Press, 2025. https://doi.org/10.1201/9781003497202-10.

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Thakral, Shaveta, and Dipali Bansal. "Fault Tolerant Arithmetic Logic Unit." In Emerging Trends in Computing and Expert Technology. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32150-5_24.

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Bhusare, Saroja S., Veeramma Yatnalli, E. Shreyas, Shreeram Aithal, Gayana A. Jain, and O. Sreekaar. "Optimized Reversible Arithmetic and Logic Unit." In Communication and Intelligent Systems. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-2100-3_50.

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Sasamal, Trailokya Nath, Ashutosh Kumar Singh, and Anand Mohan. "Design of Arithmetic Logic Unit in QCA." In Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-1823-2_7.

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Rahul, Polani, Korada Prudhvi Raj, and S. Umadevi. "8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit." In Nanoelectronic Materials and Devices. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7191-1_20.

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Shinde, Jitesh R., Sanjeev Sharma, and Lipsa Dash. "An Optimization Design Approach for Arithmetic Logic Unit." In ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-8461-5_81.

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Conference papers on the topic "Arithmetic and Logic Unit (ALU)"

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Kumari, J. L. V. Ramana, V. Kranthi Kumar, M. Abhignya, and P. Shiva Rama Krishna. "Implementation of Leading Zero Count (LZC) for Arithmetic and Logic Unit (ALU) Operations." In 2024 4th International Conference on Intelligent Technologies (CONIT). IEEE, 2024. http://dx.doi.org/10.1109/conit61985.2024.10626583.

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Roy, Sébastien. "Efficient Arithmetic and Logic Unit (ALU) Design Based on Recursive Multi-Function Circuits." In 2024 58th Asilomar Conference on Signals, Systems, and Computers. IEEE, 2024. https://doi.org/10.1109/ieeeconf60004.2024.10943049.

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Singh, Manvendra, Manoj Kumar, and Vandana Nath. "Comparative Analysis of Reversible Arithmetic Logic Units (R-ALU) Using Verilog." In 2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP). IEEE, 2024. http://dx.doi.org/10.1109/icecsp61809.2024.10698408.

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Priyanka, V., Narla Surendranath Reddy, Gogineni Jeevana, and Mohd Aftab Arab. "Design of Arithmetic Logic Unit Using Reversible Logic Gates." In 2024 2nd World Conference on Communication & Computing (WCONF). IEEE, 2024. http://dx.doi.org/10.1109/wconf61366.2024.10692088.

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Jyothi, B., B. V. R. Reddy, and Mansi Jhamb. "Design of Arithmetic Logic Unit Using Energy Charge Recovery Adiabatic Logic Technique." In 2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP). IEEE, 2024. http://dx.doi.org/10.1109/icecsp61809.2024.10698278.

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Wei, Chunyuan, Chuan Yuan, Yu Qi, Bangjian Xu, and Xin Niu. "A Float-Point Arithmetic Logic Unit for High Performance RISC-V Processor." In 2024 6th International Conference on Frontier Technologies of Information and Computer (ICFTIC). IEEE, 2024. https://doi.org/10.1109/icftic64248.2024.10913377.

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D, Gracia, Abharnaa M. R, Pranav Nair D, and Ajay Anand P. "ECRL-Based Adiabatic Logic Design for the Logic Unit of an ALU in Medical Applications Using 45 nM CMOS Technology." In 2025 3rd International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA). IEEE, 2025. https://doi.org/10.1109/icaeca63854.2025.11012621.

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Ghodeswar, Ujwala, and Ashwini Gajbhiye. "Design of 8 bit Arithmetic Logic Unit for Signal Processing Applications using Verilog." In 2025 5th International Conference on Pervasive Computing and Social Networking (ICPCSN). IEEE, 2025. https://doi.org/10.1109/icpcsn65854.2025.11035908.

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S, Poornima H., Janani P, and Manasa A. "Next-gen 32-bit Arithmetic Logic Unit: Harnessing Cellular Automata using Quantum dots (QCA) Technology." In 2024 International Conference on Recent Innovation in Smart and Sustainable Technology (ICRISST). IEEE, 2024. https://doi.org/10.1109/icrisst59181.2024.10921840.

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Verma, Reshma, Hrishikesh C S, and Lakshmi Shrinivasan. "Functional Verification of Arithmetic Logic Unit and Instruction Fetch Unit of a 32-bit RV321M ISA based RISC-V Processor." In 2024 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2024. http://dx.doi.org/10.1109/conecct62155.2024.10677337.

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Reports on the topic "Arithmetic and Logic Unit (ALU)"

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Pleszkun, Andrew R. Lithium Niobate Arithmetic Logic Unit. Defense Technical Information Center, 1991. http://dx.doi.org/10.21236/ada236062.

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