Relevant bibliographies by topics / Brent-Kung adder

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Brent-Kung adder'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Brent-Kung adder"

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reddy*, M. Ramana. "Design of Static CMOS 16 Bit High Speeds and Low Power Consumption Hybrid Adder Circuit using Brent Kung Adder." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 6 (2020): 300–310. http://dx.doi.org/10.35940/ijrte.e6559.038620.

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This paper presents a static sixteen Bit CMOS Brent kung adder shape was designed, which famous a higher pace and decrease strength intake in comparison with those of the ripple deliver adders. The pace enhancement changed into done through modifying the shape through thru adding a Brent Kung adder, complete adders the usage of (28 transistor, Boolean exact judgment) that is masses speeder whilst in comparison to ripple supply adder and These pace adders will bring about growth in DSP processors. The time delays and power consumptions are lots much less with unique adders with the aid of imple
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RH, Naik, Ganesh D, Lakshmi Tirupathamma M, Siva Sai K, and Venkateswarlu D. "Optimized FFA-Based 3-Parallel Polyphase FIR Filter Using Modified Brent-Kung Adder and Booth Multiplier for VLSI Applications." International Journal for Modern Trends in Science and Technology 11, no. 03 (2025): 128–35. https://doi.org/10.5281/zenodo.15084889.

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Digital Signal Processing (DSP) plays a crucial role in biomedical applications, as well as in voice and image processing. Digital filters serve as fundamental building blocks for DSP applications, signal analysis, and estimation. With advancements in VLSI technology, the complexity of designing digital filters has been significantly reduced, enabling efficient on-chip architectures for DSP applications.Finite Impulse Response (FIR) filters, which have a finite-duration impulse response, are widely used in DSP systems due to their stability and linear-phase characteristics, in contrast to Infi
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Shaik, Maznu. "Design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 12 (2024): 825–30. https://doi.org/10.22214/ijraset.2024.65922.

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Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. Vedic mathematics has improved the performance of multiplier. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably comp
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Mahammad, Masood Ahmad, Appala Raju Uppala, Suggala Ram Prasad, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

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In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the
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Mahammad, Masood Ahmad, Appala Raju Uppala, Ram Prasad Suggala, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109–16. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

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In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the
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R, Anjali, Sorna Marium R, Sujithra M, and Mariammal K. "Fault-Resilient Brent-Kung Adder Design Using Advanced Built-in Self-Test (BIST) Architecture." Journal of Electronics and Informatics 7, no. 1 (2025): 1–18. https://doi.org/10.36548/jei.2025.1.001.

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In modern digital systems, ensuring both high performance and reliability is essential, especially in fault-sensitive environments. This research introduces the design and implementation of a fault-tolerant Brent-Kung adder, integrated with an advanced Built-In Self-Test (BIST) framework. The Brent-Kung adder, known for its efficient carry propagation and speed optimization, is augmented with BIST techniques to enhance its reliability and testability in digital systems. A Linear Feedback Shift Register (LFSR) is used to produce pseudo-random test patterns, while a Multiple Input Signature Regi
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Pushpalatha, B., T. Pavani, and A. Ushasree. "Efficient stable-width adder-sapling strategy using Brent Kung adder." Materials Today: Proceedings 42 (2021): 1492–97. http://dx.doi.org/10.1016/j.matpr.2021.01.443.

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Prihozhy, A. A. "Synthesis of parallel adders from if-decision diagrams." «System analysis and applied information science», no. 2 (August 18, 2020): 61–70. http://dx.doi.org/10.21122/2309-4923-2020-2-61-70.

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Addition is one of the timing critical operations in most of modern processing units. For decades, extensive research has been done devoted to designing higher speed and less complex adder architectures, and to developing advanced adder implementation technologies. Decision diagrams are a promising approach to the efficient many-bit adder design. Since traditional binary decision diagrams does not match perfectly with the task of modelling adder architectures, other types of diagram were proposed. If-decision diagrams provide a parallel many-bit adder model with the time complexity of Ο(log2n)
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Harish, Basavoju, Rukmini M.S.S., and Sivani K. "HIGH PERFORMANCE FIR FILTER BASED ON PIPELINED PARALLEL PREFIX ADDER FOR SIGNAL PROCESSING APPLICATIONS." ICTACT Journal on Microelectronics 8, no. 2 (2022): 1334–37. https://doi.org/10.21917/ijme.2022.0230.

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Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-ba
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Sivadurgarao, Parasa, Naga Venkata Tejaswini Paruchuri, Huzaifa Mohammad, Vardhini Vagu, Geethika Pakalapati, and Taraka Rama Shanmukh Sai Segu. "Design and validation of low power, high performance parallel prefix adders." i-manager’s Journal on Electronics Engineering 15, no. 3 (2025): 48. https://doi.org/10.26634/jele.15.3.21813.

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In the realm of designing digital systems through Very Large Scale Integration (VLSI), the digital adder takes center stage. However, low-power VLSI adder designs grapple with the Propagation Delay issue, leading to increased latency. This paper explores the viability of Parallel Prefix Adders (PPA) in addressing these challenges for low-power VLSI designs, emphasizing minimal propagation latency. The paper delves into the design and analysis of select PPA models, comparing their performance in terms of area, delay, and power. Utilizing Xilinx Vivado 2019.1, this study evaluates four prominent
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Dissertations / Theses on the topic "Brent-Kung adder"

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Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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<p>Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. </p><p>Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughp
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Dahlqvist, Michael, and Andreas Röst. "Modulgenerator för generering av Brent Kung-adderare." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1834.

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<p>För att snabba upp addering av tal, vilket är en vital del inom signalbehandling finns olika algoritmer. En sådan algoritm är Brent Kungs vilken har en tidsfördröjning proportionell mot log2(N). </p><p>I rapporten jämförs några olika varianter av adderare med avseende på grinddjup, vilket är proportionelltmot propageringstiden. En modulgenerator för Brent Kung-adderare implementeras med Skill-kod i Cadence. Modulgeneratorn kan genera adderare av obegränsad ordlängd och är även teknologi oberoende. Brent Kung-adderarens fysiska begränsningar studeras och förslag ges på lämpliga förbättringar
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Bhupatiraju, Raja D. V. "A comparative study of high speed adders." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175891877.

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Book chapters on the topic "Brent-Kung adder"

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Gunasekaran, K., D. Muthukumaran, K. Umapathy, and S. A. Yuvaraj. "FPGA Based Implementation of Brent Kung Parallel Prefix Adder." In Intelligent Systems Reference Library. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-90119-6_14.

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Saxena, Anmol, Vyom Saraf, and Rutu Parekh. "ASIC Implementation of a 16-Bit Brent–Kung Adder at 45 nm Technology Node." In Sustainable Technology and Advanced Computing in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4364-5_8.

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Kanagamalliga, S., K. Monika, P. Monika, R. Latha, and S. Rajalingam. "A Novel Approach for Power Efficiency with Wallace Tree Multiplier and Brent Kung Adder." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2025. https://doi.org/10.1007/978-981-96-3694-5_28.

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Lokesh Chowdary, M., A. Mallaiah, and A. Jaya Lakshmi. "Design of Wallace Tree Multiplier Using Sparse Kogge-Stone and Brent–Kung Adders." In Lecture Notes in Networks and Systems. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8204-7_20.

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Reddy, M. Ramana. "The Design of a Static CMOS 16 Bit High Speed and Low Power Consumption Hybrid Adder Circuit Using Brent Kung Adder: A Recent Study." In New Approaches in Engineering Research Vol. 8. Book Publisher International (a part of SCIENCEDOMAIN International), 2021. http://dx.doi.org/10.9734/bpi/naer/v8/9295d.

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Conference papers on the topic "Brent-Kung adder"

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Karthigadevi, K., M. Sakthimohan, S. Tamilselvan, Bhuvaneswari Thiyagarajan, G. Elizabeth Rani, and V. Sanjeevi Kumar. "Enhanced 16 × 16 Dadda Multiplier Using Kung-Brent Adder for Superior Parallel Processing Performance." In 2024 8th International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2024. https://doi.org/10.1109/iceca63461.2024.10801100.

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Prudhvi, Tummala, Dantla Sudhakar Reddy, Musala Sarada, and Kanapala Satish. "Approximate Brent Kung Adder For Image Processing Applications." In 2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM). IEEE, 2023. http://dx.doi.org/10.1109/itechsecom59882.2023.10435122.

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Potdukhe, Pappu P., and Vishal D. Jaiswal. "Design of high speed carry select adder using brent kung adder." In 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). IEEE, 2016. http://dx.doi.org/10.1109/iceeot.2016.7754762.

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M B, Veena, Pramath Akkamanchi, and Vighneshkumar Uttarkar. "Low Power High Speed Brent Kung Adder Using SPST." In 2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT). IEEE, 2022. http://dx.doi.org/10.1109/gcat55367.2022.9971848.

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Krishnamoorthy, Raja, S. Durgadevi, and S. Maheshwari. "Area and delay carry select adder using Brent Kung architecture." In 2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE). IEEE, 2017. http://dx.doi.org/10.1109/iceice.2017.8191915.

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Amin, Muhammad Aiman Azuan, Mira Kartiwi, Mashkuri Yaacob, Eki Ahmad Zaki Hamidi, Teddy Surya Gunawan, and Nanang Ismail. "Design of Brent Kung Prefix Form Carry Look Ahead Adder." In 2022 8th International Conference on Wireless and Telematics (ICWT). IEEE, 2022. http://dx.doi.org/10.1109/icwt55831.2022.9935137.

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Veena, M. B., N. Suhana Khanum, D. H. Soundaryya, and P. Mamatha Sarathi. "Energy Scalable Brent Kung Adder with Non-Zeroing Bit Truncation." In 2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT). IEEE, 2022. http://dx.doi.org/10.1109/gcat55367.2022.9972236.

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Saxena, Pallavi. "Design of low power and high speed Carry Select Adder using Brent Kung adder." In 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA). IEEE, 2015. http://dx.doi.org/10.1109/vlsi-sata.2015.7050465.

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Hepzibha, K. Golda, and C. P. Subha. "A novel implementation of high speed modified brent kung carry select adder." In 2016 10th International Conference on Intelligent Systems and Control (ISCO). IEEE, 2016. http://dx.doi.org/10.1109/isco.2016.7727130.

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Guo, Pixia, Guangjun Xie, Xiaoyue Chen, Jie Han, and Yongqiang Zhang. "A Variable Latency Ling Adder Based on Brent-Kung Parallel-Prefix Topology." In 2023 IEEE 23rd International Conference on Nanotechnology (NANO). IEEE, 2023. http://dx.doi.org/10.1109/nano58406.2023.10231157.

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