Relevant bibliographies by topics / Carry Look Ahead Adder (CLAA)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Carry Look Ahead Adder (CLAA)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Carry Look Ahead Adder (CLAA)"

1

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each
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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s
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Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add
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S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee
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Balasubramanian, Padmanabhan, and Weichen Liu. "High-speed and energy-efficient asynchronous carry look-ahead adder." PLOS ONE 18, no. 10 (2023): e0289569. http://dx.doi.org/10.1371/journal.pone.0289569.

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Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm
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Neeraj, Jain, Gour Puran, and Shrman Brahmi. "A High Speed Low Power Adder in Multi Output Domino Logic." International Journal of Computer Applications 105, no. 7 (2014): 30–33. https://doi.org/10.5281/zenodo.33240.

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Speed and power is the major constraint in modern digital design so it is required to design the high speed, less number of transistors as a prime consideration. The low power carry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass transistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit adders and then shortening the path to reduce the total critical path delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power cons
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Shishir, A. Bagal, R. Asamwar Saikiran, and Dhengre Sujal. "An Exhaustive Review on Optimization of Carry-Look-Ahead Adder Using Hybrid Logic." International Journal of Innovative Science and Research Technology (IJISRT) 10, no. 2 (2025): 1548–54. https://doi.org/10.5281/zenodo.14964543.

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A revolutionary method for designing contemporary digital circuits is the use of hybrid logic in the creation of carry-look ahead adders (CLAs), which combine CMOS and memristor technology. By combining the scalability and dependability of CMOS technology with the special qualities of memristors&mdash;such as their small size, low power consumption, and non-volatile nature&mdash;this review paper investigates developments in CLA architectures. The compiled studies demonstrate how hybrid memristor-CMOS designs can be used to get around drawbacks in conventional CLA implementations, such as decr
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Chirag, M., and K.B.Ramesh. "Design and Implementation of 4-bit Multiplier using Vedic System." Journal of VLSI Design and its Advancement 7, no. 2 (2024): 38–44. https://doi.org/10.5281/zenodo.12635137.

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<em>An efficient and fast 4-bit multiplier is designed, analyzed and presented. It is achieved using a Carry-Look Ahead adder, in short CLA adder, circuit. The ancient technique known presently as &lsquo;Vedic Mathematics&rsquo; and is based on </em><em>'Urdhva Tiryakbhyam sutra' algorithm. This type of modification increases the speed of the asked multiplication by nearly 45%. It further delves into the differences between the traditional method and the proposed method. This article expands further about all the topics mentioned above.</em>
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RamakrishnaReddy, Eamani, Nallathambi Vinodhkumar, and Asaithambi Sasikumar. "A low-power high speed full adder cell using carbon nanotube field effect transistors." A low-power high speed full adder cell using carbon nanotube field effect transistors 31, no. 1 (2023): 134–42. https://doi.org/10.11591/ijeecs.v31.i1.pp134-142.

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The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model
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YUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.

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Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 out
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Dissertations / Theses on the topic "Carry Look Ahead Adder (CLAA)"

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Khalus, Vladislav Ivanovich. "T-COUNT OPTIMIZATION OF QUANTUM CARRY LOOK-AHEAD ADDER." UKnowledge, 2019. https://uknowledge.uky.edu/ece_etds/141.

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With the emergence of quantum physics and computer science in the 20th century, a new era was born which can solve very difficult problems in a much faster rate or problems that classical computing just can't solve. In the 21st century, quantum computing needs to be used to solve tough problems in engineering, business, medical, and other fields that required results not today but yesterday. To make this dream come true, engineers in the semiconductor industry need to make the quantum circuits a reality. To realize quantum circuits and make them scalable, they need to be fault tolerant, theref
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Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.

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<p>Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.</p>
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Huang, Chung-Yi, and 黃忠義. "Carry Through - Modified Carry Look-ahead Adder." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/90343508237742401702.

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碩士<br>國立清華大學<br>產業研發碩士積體電路設計專班<br>95<br>The performance of digital processor depends on the speed of adder. In the past, high-speed adders have been continuous invented. Among that, CLA (Carry Look Ahead Adder) was the most well known high-speed adder. In recent years, an improved version of CLA called MCLA (Modified Carry Look Ahead Adder) was presented. However, carry propagation was still the bottle neck in both CLA and MCLA. In this thesis, a new type adder called CT-MCLA (Carry Through - Modified Carry Look Ahead Adder) is proposed to improve the carry propagation issue and uses less area
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Hsieh, Pei-Ying, and 謝沛穎. "High-Performance Variable Length Carry Through – Carry Look-ahead Adder." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/86784215523855938352.

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Wu, Tse-Ching, and 吳則慶. "Investigation and Analysis of Energy-Efficient 32-Bit Carry-Look-Ahead Adder and Latch Circuits with Hybrid TFET and FinFET Devices for Ultra-Low-Voltage Application." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/34731570716585159572.

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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>104<br>In this thesis, we investigate the hybrid TFET-FinFET implementation of 32-bit carry-look-ahead adder (CLA) and latch circuits using atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The circuit delay, dynamic power/energy, leakage power and power/energy-delay product (PDP/EDP) for hybrid implementations are compared with all FinFET and all TFET implementations in near-threshold region. For hybrid 32-bit CLA, TFETs are u
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Γιαννοπούλου, Λεμονιά. "Σχεδίαση παράλληλης διάταξης επεξεργαστών σε ένα chip : δημιουργία και μελέτη high radix RNS αθροιστή". Thesis, 2012. http://hdl.handle.net/10889/6136.

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Η άθροιση μεγάλων αριθμών είναι μια χρονοβόρα και ενεργοβόρα διαδικασία. Πολλές μέθοδοι έχουν αναπτυχθεί για να μειωθεί η καθυστέρηση υπολογισμού του αθροίσματος λόγω της μετάδοσης κρατουμένου. Τέτοιες είναι η πρόβλεψη κρατουμένου (carry look ahead) και η επιλογή κρατουμένου (carry select). Αυτές οι αρχιτεκτονικές δεν είναι επαρκώς επεκτάσιμες για μεγάλους αριθμούς (με πολλά bits) ή πολλούς αριθμούς, διότι παράγονται μεγάλα και ενεργοβόρα κυκλώματα. Στην παρούσα εργασία μελετάται η μέθοδος υπολοίπου (RNS), η οποία χρησιμοποιεί συστήματα αριθμών μεγαλύτερα από το δυαδικό. Ορίζεται μια βάση τριώ
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Book chapters on the topic "Carry Look Ahead Adder (CLAA)"

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Kumar, Vinay, Chandan Kumar Jha, Gaurav Thapa, and Anup Dandapat. "Design of Low Power and High Speed Carry Look Ahead Adder (CLAA) Based on Hybrid CMOS Logic Style." In Lecture Notes in Electrical Engineering. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2728-1_61.

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Murthy, P. H. ST, L. Madan Mohan, V. Sreenivasa Rao, and V. Malleswara Rao. "4T Carry Look Ahead Adder Design Using MIFG." In Information and Communication Technologies. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15766-0_80.

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Tiwari, Kanchan, Amar Khopade, and Pankaj Jadhav. "Optimized Carry Look-Ahead BCD Adder Using Reversible Logic." In Communications in Computer and Information Science. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-20209-4_37.

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Babu, P. Ashok, V. Siva Nagaraju, and Rajeev Ratna Vallabhuni. "8-Bit Carry Look Ahead Adder Using MGDI Technique." In IoT and Analytics for Sensor Networks. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2919-8_22.

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George, Dhanya, E. G. Anoop, N. R. Deepa, and Nimmy M. Philip. "Fast and Minimized Error Approximate Carry Look-Ahead Adder." In Advances in Automation, Signal Processing, Instrumentation, and Control. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-8221-9_202.

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Narayan, V. S., S. M. Pratima, V. S. Saroja, and R. M. Banakar. "High Speed Low Power VLSI Architecture for SPST Adder Using Modified Carry Look Ahead Adder." In Advances in Intelligent Systems and Computing. Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-0740-5_56.

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Jeevan, B., and K. Sivani. "A New High-Speed Multiplier Based on Carry-Look-Ahead Adder and Compressor." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_8.

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Thapliyal, Himanshu, H. V. Jayashree, A. N. Nagamani, and Hamid R. Arabnia. "Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder." In Transactions on Computational Science XVII. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-35840-1_4.

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Ameta, Shilpa, Vijendra Maurya, Ashik Hussain, and Navneet Agrawal. "Design and Analysis of 8-Bit Carry Look-Ahead Adder Using CMOS and ECRL Technology." In Advances in Intelligent Systems and Computing. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7386-1_5.

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Roy, Rupsa, Swarup Sarkar, and Sourav Dhar. "Design and Characterization of a Multilayer Reversible “Carry Look-Ahead Adder” by Using QCA Spin Technique." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6393-9_41.

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Conference papers on the topic "Carry Look Ahead Adder (CLAA)"

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Salem, Sanaz, and Amir Hossein Owji. "Fast and Low Power Modified Carry Look-Ahead Adder." In 2024 32nd International Conference on Electrical Engineering (ICEE). IEEE, 2024. http://dx.doi.org/10.1109/icee63041.2024.10668142.

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Balasubramanian, Padmanabhan, and Douglas Maskell. "A New Carry Look-Ahead Adder Architecture Enabling Improved Speed and Energy Efficiency." In 2024 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM). IEEE, 2024. http://dx.doi.org/10.1109/pacrim61180.2024.10690188.

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Kumar, Aruru Sai, N. Lakshman Pratap, N. Neelima, Tithi Chetan Mahajani, Valluru Kalyan Kumar, and Pachava Anunya. "An Optimised Design of a 4-bit Carry Look-Ahead Adder Using Novel Reversible Logic Gates." In 2024 International Conference on Intelligent Algorithms for Computational Intelligence Systems (IACIS). IEEE, 2024. http://dx.doi.org/10.1109/iacis61494.2024.10721739.

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M, Chezhiyan, and R. M. Bommi. "Design and Implementation of Carry Look-Ahead Adder Using PTL with Comparative Analysis Against Transmission Gate Logic." In 2025 3rd International Conference on Communication, Security, and Artificial Intelligence (ICCSAI). IEEE, 2025. https://doi.org/10.1109/iccsai64074.2025.11064142.

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Kalyani Garimella, Lalitha M., Sri R. Sudha Garimella, Kevin Duda, and Eric Fetzer. "New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A." In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2013. http://dx.doi.org/10.1109/mwscas.2013.6674915.

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Barman, Jayeeta, and Vinay Kumar. "Approximate Carry Look Ahead Adder (CLA)for Error Tolerant Applications." In 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2018. http://dx.doi.org/10.1109/icoei.2018.8553739.

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Kostrzewski, Andrew, Dai Kyun Kim, Yao Li, and George Eichmann. "An optical-carry, look-ahead adder based on a content-addressable memory." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.tuuu4.

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We will discuss a new optical parallel- arithmetic processing scheme that uses a nonholographic optoelectronic content-addressable memory (CAM). To increase the processing speed, a carry look-ahead addition (CLA) scheme can be used. We will also present the design of a 4-bit CAM-based optical-carry look-ahead adder, as well as our experimental results.
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Eichmann, George, Andrew Koslrzewski, Dai Hyun Kim, and Yao Li. "Optical higher-order symbolic recognition." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.tuuu8.

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We will discuss a new optical parallel-arithmetic processing scheme that uses a nonholographic optoelectronic content-addressable memory (CAM). To increase the processing speed, a carry look-ahead addition (CLA) scheme can be used. We will also present the design of a 4-bit CAM-based optical-carry look-ahead adder, as well as our experimental results.
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Chaitanya kumar, M. V. S., and J. Selva kumar. "Dual Mode Logic Carry Look ahead Adder." In 2014 International Conference on Advanced Communication, Control and Computing Technologies (ICACCCT). IEEE, 2014. http://dx.doi.org/10.1109/icaccct.2014.7019143.

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Suryawanshi, Jayesh, Deepak Gawade, Nidhi Tank, Shreya Worlikar, and Shridhar Sahu. "Vedic Multiplier Using Carry look ahead adder." In 2022 5th International Conference on Advances in Science and Technology (ICAST). IEEE, 2022. http://dx.doi.org/10.1109/icast55766.2022.10039667.

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