Relevant bibliographies by topics / Carry Select Adder (CSA)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Carry Select Adder (CSA)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Carry Select Adder (CSA)"

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Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed
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A., Mounika, and Srinivasa Reddy K. "Designing and Performance Evaluation of Carry Select Adder." International Journal of VLSI System Design and Communication systems 3, no. 5 (2015): 0754–57. https://doi.org/10.5281/zenodo.48670.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better tha
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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each
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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s
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Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add
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Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.32569.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des
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Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.33081.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des
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Swetha, Tarigoppula, Sravan K. Vittapu, Ravichand Sankuru, Balla Hindupriya, Bairagoni Anand, and Gangadi Chandra Vardhan Reddy. "Implementation of Area Efficient Carry Select Adder using Binary to Excess1 Code." Journal of VLSI Design and Signal Processing 9, no. 3 (2023): 29–36. http://dx.doi.org/10.46610/jovdsp.2023.v09i03.004.

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Adders are widely used as essential parts in the design of digital integrated circuits. The Carry Select Adder (CSA) is unique among conventional adder topologies in that it operates quickly. There is a need for speedier arithmetic units as well as ones that use less power and take up less space as the mobile sector grows quickly. The Carry-Select method for adder design with carry propagation achieves a good trade-off between performance and cost. However, because it uses two ripple carry adders (RCA), the traditional CSA design still has a significant area overhead. A Binary to Excess-1 code
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Priyanka, Sharma* K. Srinivasarao. "DESIGN AND IMPLEMENTATION OF CARRY SELECT ADDER USING KOGGE-STONE TECHNIQUE." International Journal OF Engineering Sciences & Management Research 3, no. 6 (2016): 62–69. https://doi.org/10.5281/zenodo.55861.

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In VLSI System design digital adder with optimum power is one of the important area of research. For many data processing purpose CSA perform fast air thematic function. So, it is clear that there is need to reduce the power consumption in CSA. This paper discusses about to reduce the power dissipation in CSA for many applications. For reduction purpose we use one of the most important approaches, which are Kogge –stone configuration. The proposed design with Kogge-stone adder CSA has reduced power dissipation compared with CMOS technology CSA. The simulation performed using SPICE circui
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Shanigarapu, Chaithanya, and M.Srujana. "Designing and Comparative Analyses of Carry Select Adders (CSL, CSL with BEC, CSL with CBL)." International Journal of Multidisciplinary Education Research 4, no. 7(2) (2015): 101–5. https://doi.org/10.5281/zenodo.33099.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adders used in many data - processing processors. The structure of CSA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSA. The result analysis shows that the proposed structure(csa CBL) is better than the conventional CSA and CSA with BEC.
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Dissertations / Theses on the topic "Carry Select Adder (CSA)"

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Meruguboina, Dronacharya. "EFFICIENT DESIGN OF CARRY SELECT ADDER USING DOMINO MANCHESTER CARRY CHAIN." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/theses/2125.

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Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will
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Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.

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<p>Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.</p>
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Allwin, Priscilla Sharon. "A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566754181334305.

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Chen, Wei-Cheng, and 陳威誠. "Design of Self-Repair Carry Select Adder." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/18930659095287123901.

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碩士<br>國立勤益科技大學<br>電子工程系<br>99<br>In this paper, the High Reliability and Low Cost Self-Repair (SR) Carry-Select Adder (CSA) design is proposed. The capability of architecture can on-line detect all single stuck-at faults and repair in normal operation mode. In the area, this paper choose a better way to reduce the area. A self-repair CSA constructed by n two-bit modules has merely one backup redundancy with fault diagnosis circuitry. Effectively reduce the number of transistors, and the proposed new circuit to improve the previous literature the problem of fault coverage. The design is based o
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Hsu, Chih Wei, and 徐志維. "Hardware Sharing Near Threshold Voltage Carry Select Adder Circuit Design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/q78uyy.

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Su, Fong-Jia, and 蘇峰加. "Self-Repair Carry Select Adder Design Based on Two-Rail Code." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/63228400005549086936.

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碩士<br>國立勤益科技大學<br>電子工程系<br>100<br>In the thesis, we propose both totally self-checking and self-repair functions for carry select adder (CSA) design. Based on this architecture, single fault existing in the CSA can be real-time detected and repaired in the normal operation mode. The full adder cores used to design CSA is designed by using complementary pass-transistor logic (CPL). Due to its complementary and symmetric characteristics, CPL is befitted in design of the backup circuit with reduced redundancy to achieve self-repair function for the carry select adder in case of fault occurred. Tw
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Bo-Ruei, Chen, and 陳柏瑞. "Design of Add-One Carry Select Adder with Self-Repair Mechanism." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/66455422583765708186.

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碩士<br>國立勤益科技大學<br>電子工程系<br>100<br>In this thesis, the self-repair (SR) carry-select adder (CSA) design is proposed. The proposed CSA circuit has the capability of on-line totally self-checking (TSC) all single stack-at faults occurred. There are two kinds of TSC circuits proposed, one is based on conventional CSA and the other is based on CSA with add-one circuit. Because of dual backup circuits be arranged in the self-repair mechanism, it has the capability for repairing single or dual faulty function unit. As a result, the proposed self-repair carry-select adder design has higher reliability
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Lee, Ming-En, and 李明恩. "Totally Self-Checking Carry-Select Adder Design Based on Two-Rail Code." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/30393058530093757192.

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碩士<br>國立勤益科技大學<br>電子工程系<br>98<br>In this paper, the Totally Self-Checking (TSC) Carry-Select Adder (CSA) design is proposed. The capability of TSC can on-line detect all single stuck-at faults in normal operation mode. The proposed CSA has not only self-checking capability but also reduced transistor count. The design is based on TSMC 0.18um process technology, and a real chip is implemented. The transistor count of proposed totally self-checking CSA design is less than conventional CSA, and even reduced 34.85% compared with [7] for thirty-two bits design. The reduced ratio of transistor-count
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Liao, Irene M. J., and 廖美貞. "A Carry-Select-Adder Optimization Technique for High-Performance Booth-Encoded Wallace-Tree Multipliers." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/45267729737681347070.

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碩士<br>國立清華大學<br>資訊工程學系<br>89<br>In this thesis, we present two carry-select adder partitioning algorithms for high-performance Booth-encoded Wallace-tree multipliers. By taking various data arrival times into account, we propose a branch-and-bound algorithm and a heuristic algorithm to partition an n-bit carry-select adder into a number of adder blocks such that the overall delay of the design is minimized. The experimental results show that our proposed algorithm can achieve on an average 9.1% delay reduction with less than 1% of area overhead on 15 multipliers ranges from 16X16-bit to 64X64-
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CHEN, YU-YUAN, and 陳鈺媛. "The Design of a ROMless Direct Digital Frequency Synthesizer-Carry Select Adder Design and Analysis." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/76882683464879755591.

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碩士<br>華梵大學<br>電子工程學系碩士班<br>96<br>In this thesis, we design a ROMless direct digital frequency synthesizer (DDFS). The chip contains a digital part with a 32-bit phase accumulator realized by a carry select adder. We use the full-custom IC design flow to truly grasps the circuit characteristics, first we use ModelSim to simulate the phase accumulator to confirm our design concept, Next we use HSPICE with TSMC 0.35um 2P4M CMOS model to simulate both the digital part and the analog part. The simulation results show that the current consumption is 8.617mA and the SFDR can reach 42dBc.
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Books on the topic "Carry Select Adder (CSA)"

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Gokhale, U. M., and Prajakta Wasekar. High Performance Carry Select Adder Using Binary Excess Converter. GRIN Verlag GmbH, 2015.

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Satpathy, Pinaki. Design and Implementation of carry select adder using T-Spice. Anchor Academic Publishing, 2016.

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Book chapters on the topic "Carry Select Adder (CSA)"

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Arunakumari, S., K. Rajasekahr, S. Sunithamani, and D. Suresh Kumar. "Carry Select Adder Using Binary Excess-1 Converter and Ripple Carry Adder." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2308-1_30.

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Kishore, Pinninti, P. V. Sridevi, and K. Babulu. "Low Power and Optimized Ripple Carry Adder and Carry Select Adder Using MOD-GDI Technique." In Lecture Notes in Electrical Engineering. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2728-1_15.

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Rongali, Siva, and Rajanbabu Mallavarapu. "Gate Diffusion Input-Based Design for Carry Select Adder." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_26.

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Rohini, D., M. Harsha Vardhan Reddy, and G. Kishor. "Power Optimized Carry Select Adder Using Reversible Logic Gates." In Advances in Engineering Research. Atlantis Press International BV, 2025. https://doi.org/10.2991/978-94-6463-662-8_63.

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Pritty and Mansi Jhamb. "Low Power and Highly Reliable 8-Bit Carry Select Adder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-4692-1_41.

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Kavitkar, Shivkumar, and A. Anita Angeline. "Design and Implementation of Multi-bit Self-checking Carry Select Adder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_12.

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Deepthi, Kummetha, Pratheeksha Bhaskar, M. Priyanka, B. V. Sonika, and B. N. Shashikala. "Design and Implementation of High-Speed Low-Power Carry Select Adder." In Cognitive Informatics and Soft Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1056-1_41.

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Jujjuru, Jaya Lakshmi, and Rajanbabu Mallavarapu. "Improved SQRT Architecture for Carry Select Adder Using Modified Common Boolean Logic." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_36.

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Ykuntam, Yamini Devi, Bujjibabu Penumutchi, and Srilakshmi Gubbala. "Design of Speed and Area Efficient Non Linear Carry Select Adder (NLCSLA) Architecture Using XOR Less Adder Module." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8865-3_7.

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Harirajkumar, J., R. Shivakumar, S. Swetha, and N. Sasirekha. "Design of Efficient Pipelined Parallel Prefix Lander Fischer Based on Carry Select Adder." In Advances in Data and Information Sciences. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-6906-7_38.

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Conference papers on the topic "Carry Select Adder (CSA)"

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Balasubramanian, Padmanabhan, and Douglas L. Maskell. "Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic." In 2024 9th International Conference on Mathematics and Computers in Sciences and Industry (MCSI). IEEE, 2024. https://doi.org/10.1109/mcsi63438.2024.00023.

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Allada, Sankara Rao, Dr Anjanee Kumar, Kandregula Jyoshna, Kirla Pravallika, B. Medisetti Chandrasekhar, and Konathala Venkat. "Optimized 64-Bit Carry Select Adder Using Enhanced Full Adder for Reduced Power and Delay." In First International Conference on Computer, Computation and Communication (IC3C-2025). River Publishers, 2025. https://doi.org/10.13052/rp-9788743808268a074.

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Thakur, Gunjan, Devanshi Patel, and Jay Patel. "Design of Optimized Carry Select Adder (OCSA) for Low-Power IoT Applications." In 2025 International Conference on Sustainable Energy Technologies and Computational Intelligence (SETCOM). IEEE, 2025. https://doi.org/10.1109/setcom64758.2025.10932418.

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V, Senbagaseelan, Ragul T, Subbulakshmi A, and R. Rajesh Kanna. "Design and Implementation of a 4-Bit Carry Select Adder using MTCMOS-Based Ripple Carry Adder with 10T Full Adders in 90nm Technology." In 2025 International Conference in Advances in Power, Signal, and Information Technology (APSIT). IEEE, 2025. https://doi.org/10.1109/apsit63993.2025.11086236.

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Jayesh, Gautham, and Sreenidhi Prabha Rajeev. "Design and Simulation of a Carry Save Adder (CSA) using NAND Gate in CMOS 180nm Technology." In 2025 International Conference on Advances in Modern Age Technologies for Health and Engineering Science (AMATHE). IEEE, 2025. https://doi.org/10.1109/amathe65477.2025.11080777.

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N., Sukrutha, Khushi Ligade, Preeti Ramanna Patil, and Premananda B.S. "Performance Analysis of 4-Bit Hybrid Low Power Carry Select Adder using FinFET Technology." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11009690.

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Chen, Yiran, Hai Li, Kaushik Roy, and Cheng-Kok Koh. "Cascaded carry-select adder (C2SA)." In the 2005 international symposium. ACM Press, 2005. http://dx.doi.org/10.1145/1077603.1077634.

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Chen, Y., Hai Li, K. Roy, and Chena-Kok Koh. "Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design." In ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design. IEEE, 2005. http://dx.doi.org/10.1109/lpe.2005.195498.

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Dinesh, S., and S. M. Ramesh. "Speed, area, power analysis of modified carry select adder with conventional carry select adder." In PHYSICAL MESOMECHANICS OF CONDENSED MATTER: Physical Principles of Multiscale Structure Formation and the Mechanisms of Nonlinear Behavior: MESO2022. AIP Publishing, 2023. http://dx.doi.org/10.1063/5.0144638.

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Sahu, Rupashree, and Asit Kumar Subudhi. "An area optimized Carry Select Adder." In 2015 IEEE Power, Communication and Information Technology Conference (PCITC). IEEE, 2015. http://dx.doi.org/10.1109/pcitc.2015.7438066.

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