Relevant bibliographies by topics / Carry Select Ahead Adder (CSAA)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Carry Select Ahead Adder (CSAA)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Carry Select Ahead Adder (CSAA)"

1

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each
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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s
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3

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee
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Aritra, Mitra, Bakshi Amit, Sharma Bhavesh, and Didwania Nilesh. "Design of a High Speed Adder." International Journal of Scientific & Engineering Research 6, no. 4 (2015): 918–21. https://doi.org/10.5281/zenodo.33243.

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In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder &amp; Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone &amp; Carry Select Algorithms. The circuits have been designed using Verilog HDL &amp; Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.
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5

Lavanya, P., B. Chinna Rao, and T. Vishnu Murty. "High Efficient Carry Select Adder using Zero Carry Look Ahead Adder." International Journal of Engineering Trends and Technology 18, no. 1 (2014): 42–46. http://dx.doi.org/10.14445/22315381/ijett-v18p208.

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6

Corsonello, P., S. Perri, and G. Cocorullo. "Hybrid carry-select statistical carry look-ahead adder." Electronics Letters 35, no. 7 (1999): 549. http://dx.doi.org/10.1049/el:19990375.

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7

Nikhita, Matti*1 Rohini Hongal 2. R. B. Shettar 3. "PERFORMANCE ANALYSIS OF DIFFERENT N-BIT ADDERS USING REVERSIBLE LOGIC ON FPGA BOARD USING CHIPSCOPE." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 8 (2017): 307–18. https://doi.org/10.5281/zenodo.843985.

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In current scenario, high-performance chips releasing large amounts of heat impose practical limitation. Reversible circuits that conserve information, by uncomputing bits instead of throwing them away. Reversible logic design attracting more interest due to its low power consumption. The paper gives brief idea to build variety of n-bit adders like Ripple carry adder, Carry look ahead adder, Carry save adder, Carry skip adder and Carry select adder circuits using the basic reversible gate like Peres gate, TSG, MTS, Taffoli, HNG etc. The designed adders are verified using chipscope on FPGA plat
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8

Rashmi, B. K., J. Rohith, Suresh Mudaladavar Shreya, Hosageri Supreet, and P. Mattada Mahantesh. "Performance and analysis of different adder topologies." i-manager’s Journal on Electronics Engineering 14, no. 3 (2024): 31. http://dx.doi.org/10.26634/jele.14.3.20675.

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This paper gives an overview of area, power, delay for four different 64-bit adders. The design metrics in VLSI are low area and delay alongside low power designs. Adder is one of the necessary components of almost every kind of digital and high- performance systems such as FIR filters, digital signal processors and microprocessors etc. Different types of adders are carry tree adder, carry save adder, carry look ahead adder and carry select adder. In this work we have designed, simulated and synthesized these adder topologies and compared the results in cadence tool.
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9

Haruehanroengra, Sansiri, and Wei Wang. "Efficient Design of QCA Adder Structures." Solid State Phenomena 121-123 (March 2007): 553–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.553.

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Optimizing arithmetic primitives such as quantum-dot cellular automata (QCA) adders is important for investigating high-performance QCA computers in this emerging nano-technological paradigm. In this paper, we demonstrate that QCA ripple carry adder and bit-serial adder designs actually outperform carry-look-ahead and carry-select adder designs because of the increase in required interconnects. Simulation results obtained by using the QCADesigner tool for the proposed adder designs are also presented.
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10

Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and&nbsp;are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology,&nbsp;researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder&nbsp;(RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry&nbsp;Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add
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Dissertations / Theses on the topic "Carry Select Ahead Adder (CSAA)"

1

Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.

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<p>Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.</p>
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Book chapters on the topic "Carry Select Ahead Adder (CSAA)"

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Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

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The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core
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Conference papers on the topic "Carry Select Ahead Adder (CSAA)"

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Teja, D. Surya, and P. Jagadeesh. "Evaluation of Novel 16-Bit Vedic Multiplier Using Carry Look Ahead Adder for High Speed and Low Area in Comparison with Carry Select Adder." In 2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE). IEEE, 2024. http://dx.doi.org/10.1109/iitcee59897.2024.10467821.

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Journal articles
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