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Journal articles on the topic 'Circuits - computer hardware'

Author: Grafiati

Published: 28 July 2024

Last updated: 31 July 2025

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1

Curtis, K. M. "Warnier-Orr: An Electronic Hardware Design Methodology." International Journal of Electrical Engineering & Education 26, no. 3 (1989): 197–205. http://dx.doi.org/10.1177/002072098902600302.

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The paper considers the application of a well-known computer programming methodology to the design of electronic circuits. Parallels are drawn between real-life situations, computer programs and electronic circuit design. Examples of the application of the methodology are given in each case.

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2

Weder, Benjamin, Johanna Barzen, Frank Leymann, and Marie Salm. "Automated Quantum Hardware Selection for Quantum Workflows." Electronics 10, no. 8 (2021): 984. http://dx.doi.org/10.3390/electronics10080984.

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The execution of a quantum algorithm typically requires various classical pre- and post-processing tasks. Hence, workflows are a promising means to orchestrate these tasks, benefiting from their reliability, robustness, and features, such as transactional processing. However, the implementations of the tasks may be very heterogeneous and they depend on the quantum hardware used to execute the quantum circuits of the algorithm. Additionally, today’s quantum computers are still restricted, which limits the size of the quantum circuits that can be executed. As the circuit size often depends on th

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3

Kreppel, Fabian, Christian Melzer, Diego Olvera Millán, et al. "Quantum Circuit Compiler for a Shuttling-Based Trapped-Ion Quantum Computer." Quantum 7 (November 8, 2023): 1176. http://dx.doi.org/10.22331/q-2023-11-08-1176.

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The increasing capabilities of quantum computing hardware and the challenge of realizing deep quantum circuits require fully automated and efficient tools for compiling quantum circuits. To express arbitrary circuits in a sequence of native gates specific to the quantum computer architecture, it is necessary to make algorithms portable across the landscape of quantum hardware providers. In this work, we present a compiler capable of transforming and optimizing a quantum circuit targeting a shuttling-based trapped-ion quantum processor. It consists of custom algorithms set on top of the quantum

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4

Castro, Lucas, and Rodolfo Azevedo. "Circuitly: A visual and constructive framework for teaching digital circuits." International Journal of Computer Architecture Education 9, no. 1 (2020): 10–15. http://dx.doi.org/10.5753/ijcae.2020.4839.

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This paper describes an interactive and student-friendly framework for teaching digital circuits and computer architecture topics. It aims to improve students learning process by providing a visual drag-and-drop circuit design editor, interactive simulation, signal monitoring and testbench tools - all integrated in a widely accessible application that runs in the browser. Circuitly does so in a programmatic way, to help students better understand the Hardware Description Languages they will encounter in the future.

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5

Odame, K., and P. E. Hasler. "Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping." VLSI Design 2010 (March 18, 2010): 1–8. http://dx.doi.org/10.1155/2010/687498.

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Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to de

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6

Zhu, D., N. M. Linke, M. Benedetti, et al. "Training of quantum circuits on a hybrid quantum computer." Science Advances 5, no. 10 (2019): eaaw9918. http://dx.doi.org/10.1126/sciadv.aaw9918.

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Generative modeling is a flavor of machine learning with applications ranging from computer vision to chemical design. It is expected to be one of the techniques most suited to take advantage of the additional resources provided by near-term quantum computers. Here, we implement a data-driven quantum circuit training algorithm on the canonical Bars-and-Stripes dataset using a quantum-classical hybrid machine. The training proceeds by running parameterized circuits on a trapped ion quantum computer and feeding the results to a classical optimizer. We apply two separate strategies, Particle Swar

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Gao, Hua Qiang, Yu Jing Wang, Shou Qiang Kang, Zhang Le, Jian Qing Wang, and Jing Jing Wei. "Realization of Digital Chaotic Signal Generation Circuits." Applied Mechanics and Materials 716-717 (December 2014): 1352–55. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1352.

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To overcome the shortcomings of realizing chaotic system by analog circuits, digital chaotic signal generation circuits based on DSP are designed. Computer simulation of chaotic system is performed firstly, and the discrete equations are obtained using discretization algorithm. On this basis, the design of hardware circuits based on DSP is made, and the corresponding C programs are constructed. Through the debugging of software and hardware, digital design of chaotic system based on DSP is achieved, and chaotic attractor is observed through an oscilloscope by digital-to-analog conversion circu

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8

Tezak, Nikolas, Armand Niederberger, Dmitri S. Pavlichin, Gopal Sarma, and Hideo Mabuchi. "Specification of photonic circuits using quantum hardware description language." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1979 (2012): 5270–90. http://dx.doi.org/10.1098/rsta.2011.0526.

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Following the simple observation that the interconnection of a set of quantum optical input–output devices can be specified using structural mode VHSIC hardware description language, we demonstrate a computer-aided schematic capture workflow for modelling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.

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9

Li, Zeyu, Junjie Wang, Zhao Huang, Nan Luo, and Quan Wang. "Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans based on Evolvable Hardware." Applied Sciences 12, no. 13 (2022): 6601. http://dx.doi.org/10.3390/app12136601.

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Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT

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10

Hu, Wei, Armaiti Ardeshiricham, and Ryan Kastner. "Hardware Information Flow Tracking." ACM Computing Surveys 54, no. 4 (2021): 1–39. http://dx.doi.org/10.1145/3447867.

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Information flow tracking (IFT) is a fundamental computer security technique used to understand how information moves through a computing system. Hardware IFT techniques specifically target security vulnerabilities related to the design, verification, testing, manufacturing, and deployment of hardware circuits. Hardware IFT can detect unintentional design flaws, malicious circuit modifications, timing side channels, access control violations, and other insecure hardware behaviors. This article surveys the area of hardware IFT. We start with a discussion on the basics of IFT, whose foundations

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Mohan, Navya, and J. P. Anita. "Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model." Cryptography 7, no. 1 (2023): 4. http://dx.doi.org/10.3390/cryptography7010004.

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The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel

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12

Chattopadhyay, Saranyu, Pranesh Santikellur, Rajat Subhra Chakraborty, Jimson Mathew, and Marco Ottavi. "A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (2021): 1–24. http://dx.doi.org/10.1145/3460004.

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Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts

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13

López-Magaña, Carlos, Jorge Rivera, Susana Ortega-Cisneros, Federico Sandoval-Ibarra, and Juan Luis Del Valle. "A Reduced Hardware SNG for Stochastic Computing." Electronics 12, no. 16 (2023): 3383. http://dx.doi.org/10.3390/electronics12163383.

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Stochastic Computing (SC) is an alternative way of computing with binary weighted words that can significantly reduce hardware resources. This technique relies on transforming information from a conventional binary system to the probability domain in order to perform mathematical operations based on probability theory, where smaller amounts of binary logic elements are required. Despite the advantage of computing with reduced circuitry, SC has a well known issue; the input interface known as stochastic number generator (SNG), is a hardware consuming module, which is disadvantageous for small d

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14

Mattioli, Michael. "FPGAs in Client Compute Hardware." Queue 19, no. 6 (2021): 66–88. http://dx.doi.org/10.1145/3512327.

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FPGAs (field-programmable gate arrays) are remarkably versatile. They are used in a wide variety of applications and industries where use of ASICs (application-specific integrated circuits) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.

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15

Balasubramanian, Padmanabhan, Raunaq Nayar, Okkar Min, and Douglas L. Maskell. "Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits." Computers 11, no. 1 (2022): 11. http://dx.doi.org/10.3390/computers11010011.

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Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be

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16

Hussain Hassan, Nashaat M., Mohamed Adel Esmaeel Salama, Aziza I. Hussein, and Mohamed Mourad Mabrook. "Design and implementation of a low-cost circuit for medium-speed flash analog to digital conversions." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 2 (2024): 2361. http://dx.doi.org/10.11591/ijece.v14i2.pp2361-2368.

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Despite the considerable advancements in analog-to-digital conversion (ADC) circuits, many papers neglect several crucial considerations: Firstly, it does not ensure that ADCs work well in the software or hardware. Secondly, it is not certain that ADCs have a wide range of amplitude responses for the input voltages to be convenient in many applications, especially in electronics, communications, computer vision, CubeSat circuits, and subsystems. Finally, many of these ADCs need to look at the suitability of the proposed circuit to the most extensive range of frequencies. In this paper, a desig

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17

Joshi, Aravind, Akshara Kairali, Renju Raju, Adithya Athreya, and Reena Monica P. "Quantum Circuit Optimization of Arithmetic Circuits using ZX Calculus." International Journal of Innovative Technology and Exploring Engineering 13, no. 2 (2024): 26–31. http://dx.doi.org/10.35940/ijitee.b9794.13020124.

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Quantum computing is an emerging technology in which quantum mechanical properties are suitably utilized to perform certain compute-intensive operations faster than classical computers. Quantum algorithms are designed as a combination of quantum circuits that each require a large number of quantum gates, which is a challenge considering the limited number of qubit resources available in quantum computing systems. Our work proposes a technique to optimize quantum arithmetic algorithms by reducing the hardware resources and the number of qubits based on ZX calculus. We have utilized ZX calculus

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18

Zhao, Xue Mei. "Realization of Serial Port Expansion Circuit." Applied Mechanics and Materials 271-272 (December 2012): 1597–601. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.1597.

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This article describes the design of a interface chip with serial port expansion circuit of computer in industrial applications. It is used to connect with 422 and RS232 interfaces. Circuits involved several major chip such as the interface of 422 and RS232 and UART(Universal Asynchronous Receiver Transmitter)16C550 Inside the computer. Paper describes the composition of the hardware circuit, theory and implementation and initialization programming of URAT interface chip. We use interface chip with the FIFO to the circuit, It improves the efficiency of the application software, And it solves t

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19

Karmakar, Gobinda, Dr Saroj Kumar Biswas, Dr Ardhendu Mandal, Arijit Bhattacharya, Akhil Kumar Das, and Ekram Alam. "Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters." Journal of University of Shanghai for Science and Technology 23, no. 09 (2021): 1313–25. http://dx.doi.org/10.51201/jusst/21/09690.

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Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of

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20

Hassan, Nashaat M. Hussain, Mohamed Adel Esmaeel Salama, Aziza I. Hussein, and Mohamed Mourad Mabrook. "Design and implementation of a low-cost circuit for mediumspeed flash analog to digital conversions." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 2 (2024): 2361–68. https://doi.org/10.11591/ijece.v14i2.pp2361-2368.

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Despite the considerable advancements in analog-to-digital conversion (ADC) circuits, many papers neglect several crucial considerations: Firstly, it does not ensure that ADCs work well in the software or hardware. Secondly, it is not certain that ADCs have a wide range of amplitude responses for the input voltages to be convenient in many applications, especially in electronics, communications, computer vision, CubeSat circuits, and subsystems. Finally, many of these ADCs need to look at the suitability of the proposed circuit to the most extensive range of frequencies. In this paper, a desig

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21

Czarnik, Piotr, Andrew Arrasmith, Patrick J. Coles, and Lukasz Cincio. "Error mitigation with Clifford quantum-circuit data." Quantum 5 (November 26, 2021): 592. http://dx.doi.org/10.22331/q-2021-11-26-592.

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Achieving near-term quantum advantage will require accurate estimation of quantum observables despite significant hardware noise. For this purpose, we propose a novel, scalable error-mitigation method that applies to gate-based quantum computers. The method generates training data {Xinoisy,Xiexact} via quantum circuits composed largely of Clifford gates, which can be efficiently simulated classically, where Xinoisy and Xiexact are noisy and noiseless observables respectively. Fitting a linear ansatz to this data then allows for the prediction of noise-free observables for arbitrary circuits. W

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22

Y. N., Sharath Kumar, and Dinesha P. "TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (2021): 2704. http://dx.doi.org/10.11591/ijece.v11i3.pp2704-2710.

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Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the

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23

Minev, Petar. "Visual Simulation of a Digital Hardware Model." Innovative STEM Education 6, no. 1 (2024): 115–19. https://doi.org/10.55630/stem.2024.0612.

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Visual simulation in circuit design involves creating a software application that provides a dynamic visual representation of a digital system modeled with Hardware Description Languages (HDLs). This allows users to gain a deeper understanding of the system's behavior by observing the simulation in real-time. Additionally, the simulation data facilitates easier identification and correction of malfunctions in digital circuits models. This report explores the capabilities of the Visual Debug (VIZ) feature in the Makerchip IDE for creating a visual simulation of a stack-based calculator model. T

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24

Banik, Subhadeep, and Francesco Regazzoni. "Compact Circuits for Efficient Möbius Transform." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 2 (2024): 481–521. http://dx.doi.org/10.46586/tches.v2024.i2.481-521.

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The Möbius transform is a linear circuit used to compute the evaluations of a Boolean function over all points on its input domain. The operation is very useful in finding the solution of a system of polynomial equations over GF(2) for obvious reasons. However the operation, although linear, needs exponential number of logic operations (around n · 2n−1 bit xors) for an n-variable Boolean function. As such, the only known hardware circuit to efficiently compute the Möbius Transform requires silicon area that is exponential in n. For Boolean functions whose algebraic degree is bound by some para

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Bordoni, Simone, Denis Stanev, Tommaso Santantonio, and Stefano Giagu. "Long-Lived Particles Anomaly Detection with Parametrized Quantum Circuits." Particles 6, no. 1 (2023): 297–311. http://dx.doi.org/10.3390/particles6010016.

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We investigate the possibility to apply quantum machine learning techniques for data analysis, with particular regard to an interesting use-case in high-energy physics. We propose an anomaly detection algorithm based on a parametrized quantum circuit. This algorithm was trained on a classical computer and tested with simulations as well as on real quantum hardware. Tests on NISQ devices were performed with IBM quantum computers. For the execution on quantum hardware, specific hardware-driven adaptations were devised and implemented. The quantum anomaly detection algorithm was able to detect si

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26

Rentería, Leonardo, Margarita Mayacela, Klever Torres, Wladimir Ramírez, Rolando Donoso, and Rodrigo Acosta. "FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits." Computation 12, no. 9 (2024): 174. http://dx.doi.org/10.3390/computation12090174.

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The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iteratio

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27

Vahid, Frank. "It's Time to Stop Calling Circuits "Hardware"." Computer 40, no. 9 (2007): 106–8. http://dx.doi.org/10.1109/mc.2007.322.

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Acharya, Nikita, Miroslav Urbanek, Wibe A. De Jong, and Samah Mohamed Saeed. "Test Points for Online Monitoring of Quantum Circuits." ACM Journal on Emerging Technologies in Computing Systems 18, no. 1 (2022): 1–19. http://dx.doi.org/10.1145/3477928.

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Noisy Intermediate-Scale Quantum (NISQ) computers consisting of tens of inherently noisy quantum bits (qubits) suffer from reliability problems. Qubits and their gates are susceptible to various types of errors. Due to limited numbers of qubits and high error rates, quantum error correction cannot be applied. Physical constraints of quantum hardware including the error rates are used to guide the design and the layout of quantum circuits. The error rates determine the selection of qubits and their operations. The resulting circuit is executed on the quantum computer. This study explores the ri

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Khan, Wilayat, Farrukh Aslam Khan, Abdelouahid Derhab, and Adi Alhudhaif. "CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover." Complexity 2021 (May 25, 2021): 1–12. http://dx.doi.org/10.1155/2021/5525539.

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Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of

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30

LAI, Y. M., C. K. TSE, and P. MEHTA. "A COMPUTER METHOD FOR THE FORMULATION OF AVERAGED MODELS FOR DC/DC POWER CONVERTER CIRCUITS." Journal of Circuits, Systems and Computers 05, no. 03 (1995): 373–91. http://dx.doi.org/10.1142/s0218126695000230.

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A computer method for deriving averaged circuit models for a class of power converter circuits is proposed. The proposed method is applicable to any dc/dc converter circuit whose switching frequency is much greater than the natural frequency of each constituent circuit topology. The method starts with decomposing the original circuit into two multiport sub-circuits. One contains the "fast" part, called the Minimum Separable Switching Configuration (MISSCO), and the other contains the remaining "slow" part of the circuit. A hybrid matrix that relates the port voltages and currents of the MISSCO

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Purushottam Kumar Maurya. "Smart Circuit Design Machine Learning-Driven Optimization for Enhanced Performance in Electronics and Computer Engineering." Tuijin Jishu/Journal of Propulsion Technology 45, no. 02 (2024): 2794–805. http://dx.doi.org/10.52783/tjjpt.v45.i02.6339.

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In the realm of Electronics and Computer engineering, achieving optimal performance of circuits amidst escalating complexity poses significant challenges. Traditional manual optimization techniques are often inadequate to navigate the intricacies of modern electronic systems. This paper advocates for the adoption of machine learning-driven optimization as a transformative approach to smart circuit design. By leveraging machine learning algorithms, engineers can systematically explore the expansive design space, discern complex relationships between circuit parameters and performance metrics, a

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Hsiao, Michael S. "Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits." VLSI Design 15, no. 1 (2002): 407–16. http://dx.doi.org/10.1080/1065514021000012020.

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Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic

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Koliver, Cristian, Cristina Meinhardt, and Mateus Grellert da Silva. "Por um Ensino de Arquitetura de Computadores para Cursos de Sistemas de Informação." International Journal of Computer Architecture Education 11, no. 1 (2022): 1–9. http://dx.doi.org/10.5753/ijcae.2022.4833.

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The subtle difference among the computer courses in Brazilian Universities has as common barrier the contents of computer architecture and computer organization. Engineering courses focus more on the design of integrated circuits, deepening the knowledge of circuit-level architectures. Science courses, on the other hand, seek to focus on the strategies for increasing the performance presented in the evolution of computing and the future challenges, using intermediate abstractions to circuits. However, for the information systems course, the relevant points are knowing the architecture to get t

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Feng, Cang Xu, Zhen Shui Liu, and Xiao Cui. "Hardware Design of a New Instrument to Control the Heat Pulse and Measure the Temperature of Stratum." Advanced Materials Research 614-615 (December 2012): 1422–26. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1422.

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In this work, we report the design of a new instrument including one heat pulse circuit and three temperature measure circuits. Heat pulse control circuit can control the heating time of heater strip. The heating power is 0.5W and the duty time of every heat pulse is 8s. Three temperature measure circuits can measure the change of stratum’s temperature before and after accurately. The temperature resolution is 0.001°C, precision is 0.01°C and sampling rate is 1 Hz. The instrument can save the temperature data for every measure process. It is also provided with the data communication interface.

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Mourad, Samiha. "Computer-Aided Testing Systems: Evaluation and Benchmark Circuits." VLSI Design 1, no. 1 (1993): 87–97. http://dx.doi.org/10.1155/1993/89495.

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As the demand on Computer-Aided Testing Systems (CATS)—Automatic Test Pattern Generation (ATPG) and logic and fault simulations as well as testability analysis—increases and the choice becomes more varied, a need to compare the merits of the different systems emerges. Benchmark circuits are used to carry out the comparisons.In this paper, criteria for selecting the benchmark circuits are discussed. These criteria are partly based on the results of experiments carried out to characterize CATS. The focus is particularly on Automatic Test Pattern Generators. The preliminary results show that ther

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Mao, Jiajie, Xiaowen Jiang, Dehong Liu, Jianjun Chen, and Kai Huang. "A Hardware Trojan-Detection Technique Based on Suspicious Circuit Block Partition." Electronics 11, no. 24 (2022): 4138. http://dx.doi.org/10.3390/electronics11244138.

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To ensure that a hardware Trojan remains hidden in a circuit, it is usually necessary to ensure that the trigger signal has a low testability, which has been widely recognized and proven. The most advanced testability-based detection methods are rather slow for large circuits, and the false-positive rate is not as low as that for small circuits. In this paper, a hardware Trojan, through the low testability of the trigger signal and its position characteristics in the circuit, was detected, which greatly improves the detection speed while maintaining a lower false positive rate when being appli

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Rojec, Žiga, Iztok Fajfar, and Árpád Burmen. "Evolutionary Synthesis of Failure-Resilient Analog Circuits." Mathematics 10, no. 1 (2022): 156. http://dx.doi.org/10.3390/math10010156.

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Analog circuit design requires large amounts of human knowledge. A special case of circuit design is the synthesis of robust and failure-resilient electronics. Evolutionary algorithms can aid designers in exploring topologies with new properties. Here, we show how to encode a circuit topology with an upper-triangular incident matrix and use the NSGA-II algorithm to find computational circuits that are robust to component failure. Techniques for robustness evaluation and evolutionary algorithm guidances are described. As a result, we evolve square root and natural logarithm computational circui

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Mirmohammadi, Zahra, and Shahram Etemadi Borujeni. "A New Optimal Method for the Secure Design of Combinational Circuits against Hardware Trojans Using Interference Logic Locking." Electronics 12, no. 5 (2023): 1107. http://dx.doi.org/10.3390/electronics12051107.

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Effective resistance to intellectual property theft, reverse engineering, and hardware Trojan insertion in integrated circuit supply chains is increasingly essential, for which many solutions have been proposed. Accordingly, strong attacks are also designed in this field. One way to achieve the above goal is obfuscation. The hardware obfuscation method hides the primary function of the circuit and the normal Netlist from the attacker by adding several key gates in the original Netlist. The functionality circuit is correct only if the correct key is applied; otherwise, the circuit is obfuscated

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Kaufmann, Daniela, Armin Biere, and Manuel Kauers. "Incremental column-wise verification of arithmetic circuits using computer algebra." Formal Methods in System Design 56, no. 1-3 (2019): 22–54. http://dx.doi.org/10.1007/s10703-018-00329-2.

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AbstractVerifying arithmetic circuits and most prominently multiplier circuits is an important problem which in practice still requires substantial manual effort. The currently most effective approach uses polynomial reasoning over pseudo boolean polynomials. In this approach a word-level specification is reduced by a Gröbner basis which is implied by the gate-level representation of the circuit. This reduction returns zero if and only if the circuit is correct. We give a rigorous formalization of this approach including soundness and completeness arguments. Furthermore we present a novel incr

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Joshi, Viraj, Pravin Mane, and Bits Pilani. "Approximate Arithmetic Circuit Design for Error Resilient Applications." International Journal of VLSI Design & Communication Systems 13, no. 1/2/3/4/5/6 (2022): 01–16. http://dx.doi.org/10.5121/vlsic.2022.13601.

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When the application context is ready to accept different levels of exactness in solutions and is supported by human perception quality, then the term ‘Approximate Computing’ tossed before one decade will become the first priority . Even though computer hardware and software are working to generate exact results, approximate results are preferred whenever an error is in predefined bound and adaptive. It will reduce power demand and critical path delay and improve other circuit metrics. When it comes to traditional arithmetic circuits, those generating correct results with limitations on perfor

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Huo, Mingxia, and Ying Li. "Error-resilient Monte Carlo quantum simulation of imaginary time." Quantum 7 (February 9, 2023): 916. http://dx.doi.org/10.22331/q-2023-02-09-916.

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Computing the ground-state properties of quantum many-body systems is a promising application of near-term quantum hardware with a potential impact in many fields. The conventional algorithm quantum phase estimation uses deep circuits and requires fault-tolerant technologies. Many quantum simulation algorithms developed recently work in an inexact and variational manner to exploit shallow circuits. In this work, we combine quantum Monte Carlo with quantum computing and propose an algorithm for simulating the imaginary-time evolution and solving the ground-state problem. By sampling the real-ti

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Liu, Jia, Yan Shi, Desheng Meng, and Zhongfeng Liu. "Design and Performance Analysis of Monitoring System for Seed Metering and Fertilization of Precision Seeder Based on Photoelectric Sensor." Journal of Nanoelectronics and Optoelectronics 18, no. 8 (2023): 971–77. http://dx.doi.org/10.1166/jno.2023.3466.

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In order to realize accurate monitoring of wheat sowing and fertilization process and ensure efficient and reliable sowing operation, an integrated monitoring system of wheat sowing and fertilization based on variable-distance photoelectric sensor is designed. The monitoring system includes the hardware circuit of STM32F103 lower computer and the human-machine interface of the upper computer touch screen. The hardware circuit of the lower computer is composed of OH-1021 photoelectric sensor, signal shaping and amplifying circuit, encoder speed acquisition module, communication module, central

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Wang, Yao, Lijun Sun, Haibo Wang, Lavanya Gopalakrishnan, and Ronald Eaton. "Novel prioritized LRU circuits for shared cache in computer systems." Modern Physics Letters B 34, no. 23 (2020): 2050242. http://dx.doi.org/10.1142/s0217984920502425.

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Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the

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Xu, Peilong, Dan Lan, Fengyun Wang, and Incheol Shin. "In-Memory Computing Integrated Structure Circuit Based on Nonvolatile Flash Memory Unit." Electronics 12, no. 14 (2023): 3155. http://dx.doi.org/10.3390/electronics12143155.

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Artificial intelligence has made people’s demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method for neural morphology computation has problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read and write to build a convolutional neural network structure to improve the performance of neural morphological computing. In the experiment, floating-gate transistors were used to simulate neural network synapses to design core cross-array circuits. A voltage subtr

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HASUO, SHINYA. "JOSEPHSON DEVICES FOR COMPUTER APPLICATIONS." International Journal of High Speed Electronics and Systems 03, no. 01 (1992): 13–52. http://dx.doi.org/10.1142/s0129156492000035.

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Josephson integrated circuit technology has progressed remarkably since the introduction of the reliable niobium junction. Josephson microprocessors and memory circuits that were once considered impracticable have been demonstrated. All the functions required for a Josephson computer can now be fabricated, although integration densities are still much lower than those achievable with semiconductor devices. The next step is to demonstrate a small-scale special-purpose Josephson computer system.

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Xu, Jie, Dingjun Qian, and Gensheng Hu. "Analysis on Simplified Method of IoT-based HHL Algorithm Corresponding Quantum Circuit for Quantum Computer Application." Mobile Information Systems 2023 (April 17, 2023): 1–10. http://dx.doi.org/10.1155/2023/1063505.

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Whether it is a traditional industry or a Frontier field, it has unveiled the trend of industrial IoT construction and application, which plays a vital role in building a strong manufacturing country and promoting high-quality economic development in China. HHL algorithm has become one of the important quantum algorithms, but there are few researches on the construction of quantum circuits and the application of quantum sequencing. In this paper, a model based on the quantum circuit corresponding to the HHL algorithm to deal with the quantum application problem is proposed. A quantum circuit b

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Zhang, Xiang, Xu Dong Pan, and Guang Lin Wang. "Distributed Control System Based on PIC Microcomputers." Key Engineering Materials 522 (August 2012): 682–85. http://dx.doi.org/10.4028/www.scientific.net/kem.522.682.

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This paper describes a distributed control system, which is based on PIC microcomputers. The hardware of this system included industrial personal computer, RS232-RS485 converter, control circuit, motor driver and so on. The PIC microcomputers on control circuits are used as basic control chips. The software of system is developed by Visual C++, communicates through the RS485 bus. The human-machine interface is developed, which is intuitive and friendly. Test result shows that the control system is effective and reliable.

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Cancare, Fabio, Davide B. Bartolini, Matteo Carminati, Donatella Sciuto, and Marco D. Santambrogio. "On the Evolution of Hardware Circuits via Reconfigurable Architectures." ACM Transactions on Reconfigurable Technology and Systems 5, no. 4 (2012): 1–22. http://dx.doi.org/10.1145/2392616.2392620.

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Qin, Xing, Chaojie Li, Haitao He, Zejun Pan, and Chenxiao Lai. "Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network." Electronics 12, no. 11 (2023): 2351. http://dx.doi.org/10.3390/electronics12112351.

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Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after us

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Erata, Ferhat, Chuanqi Xu, Ruzica Piskac, and Jakub Szefer. "Quantum Circuit Reconstruction from Power Side-Channel Attacks on Quantum Computer Controllers." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 2 (2024): 735–68. http://dx.doi.org/10.46586/tches.v2024.i2.735-768.

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The interest in quantum computing has grown rapidly in recent years, and with it grows the importance of securing quantum circuits. A novel type of threat to quantum circuits that dedicated attackers could launch are power trace attacks. To address this threat, this paper presents first formalization and demonstration of using power traces to unlock and steal quantum circuit secrets. With access to power traces, attackers can recover information about the control pulses sent to quantum computers. From the control pulses, the gate level description of the circuits, and eventually the secret alg

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